DESIGN AND ANALYSIS OF 2 GHz 130nm CMOS CASCODE LOW NOISE AMPLIFIER WITH INTEGRATED CIRCULARLY POLARIZED PATCH ANTENNA
Authors/Creators
Description
Circuits and Systems: An International Journal (CSIJ)
ISSN : 2349 - 2171
Article Title: DESIGN AND ANALYSIS OF 2 GHz 130nm CMOS CASCODE LOW NOISE AMPLIFIER WITH INTEGRATED CIRCULARLY POLARIZED PATCH ANTENNA
Varun D
ABSTRACT
This work, illustrates the development of 2 GHz Low Noise Amplifier (LNA) interfaced with square truncated edge-fed right circularly polarized patch antenna. The LNA is simulated on Agilent ADS platform with TSMC 130nm RF CMOS process. The development of cascode amplifier and its optimization has been further exemplified. The developed LNA is tuned for 2 GHz and the performance is tuned for high stability factor of 4, Gain of 19 dB which is essential for any mobile device, Noise Figure (NF) of 1.15 dB with a P1dB point at -9 dBm. Further a truncated patch antenna with right circular polarization has been simulated on EMpro. The antenna has a gain of 6.1 dB in the azimuth plane. The simulated system can be further integrated to form the RF front end of TDD2000 LTE standard mobile device.
KEYWORDS
Cascode, LNA, 130nm, azimuth, cascade
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Original Source URL: http://airccse.com/csij/papers/1314csij05.pdf