Application of Electrical Effective Channel Length and External Resistance Measurement Techniques to a Submicrometer CMOS Process

The practical applications and limitations of four methods for extracting the effective channel length (Leff) and series resistance (Rext) parameters for MOS devices are studied. The methods are: GD (gate drive) using fixed-current Vt or GD(Ids); SBGD (substrate-bias GD) using fixed-current Vt or SBGD (Ids); GD using maximum slope Vt or GD (Gm); and SBGD using maximum slope Vt or SBGD (Gm). Conventional and two LDD (lightly doped drain) structures fabricated in a submicrometer CMOS process are used. The results indicate that all the extraction methods are applicable to both n-channel and p-channel devices, although some are only valid over a small range of gate biases. Inconsistencies in applying Vt calculations to the extraction equations set a lower limit for Vgst of approximately 0.5 V, while the upper limit of 2.0-4.0 V arises due to imprecision in Rds measurements influencing the double regression steps involved in the techniques. The SBGD (Ids) method was applicable over a wider range of bias conditions than the other techniques analyzed and is easier to implement.