On-Chip Implementation of high speed and High resolution pipeline Radix 2 FFT algorithm

A new on-chip implementation of Fast Fourier Transform (FFT) based on Radix 2 is presented. The pipeline and parallel approaches are combined to introduce a new high-speed FFT algorithm which increases resolution by using floating point calculations in its structures. The design has the merits of low complexity and high-speed performance. Furthermore, latency reduction is an important issue to implement the high-speed FFT on FPGA. The proposed FFT algorithm shows the latency of (N/2 log(2) N) + 11. Moreover, this algorithm has the advantage of low mean squared error (MSE) of 0.0001 which is preferable to Radix 2 FFT.