/*
 * pipenet1.cpp - device implementations for pipenet1 module
 * dynamically linked library for QucsStudio
 * created from VerilogAMS file by ADMS
 */

#include <qucsstudio_library.h>
#include <qucsstudio_vams.h>

// --------------------------------------------------------------
// component parameter definition
tParameterDef params[] = {
  {"k", "1", false, "-"},
  {"n", "1.852", false, "-"},
};

// -----------------------------------------------------
// external nodes
#undef Pi
#define Pi Nodes[0]
#undef Po
#define Po Nodes[1]

// internal nodes

// -----------------------------------------------------
// VerilogA analog functions.


// -----------------------------------------------------
// Evaluate VerilogA equations in analog block.
void fillMatrix(Component *theComp, Node **Nodes, tParameter *Parameters, tGlobalVar *gVar, EqnSystem *sys, double freq, double)
{
  // global variables.

  // general variables.

  // Load device model input parameters.
  double k = getNumber(Parameters[0]);
  double n = getNumber(Parameters[1]);


  // ----------------- evaluate verilog initial model -----------------------


  // ----------------- evaluate verilog initial step ------------------------


  // ----------------- evaluate verilog initial instance --------------------


  // ----------------- evaluate verilog analog equations --------------------
  double v;
  double i;
  double v_VPi_Po;
  double i_VPi_Po;
  v_VPi_Po=(1/k);
  v=(sys->getV(Pi, Po)/k);
  if((v>=0.0))
  {
  {
    double m00_sqrt(d00_sqrt0,((v*v)+1.0e-30))
    double m10_sqrt(d10_sqrt0,d00_sqrt0,((v*v)+1.0e-30))
    v_VPi_Po=((v_VPi_Po+((v_VPi_Po*v)+(v*v_VPi_Po))*d10_sqrt0)/2);
    v=((v+d00_sqrt0)/2);
  }
  {
    double m00_logE(d00_logE0,v)
    double m00_exp(d00_exp1,((d00_logE0*1)/n))
    double m10_logE(d10_logE0,d00_logE0,v)
  #define d10_exp1 d00_exp1
    i_VPi_Po=(v_VPi_Po*d10_logE0*1/n)*d10_exp1;
    i=d00_exp1;
  }
  }
  else
  {
  {
    double m00_fabs(d00_fabs0,v)
    double m00_logE(d00_logE1,d00_fabs0)
    double m00_exp(d00_exp2,((d00_logE1*1)/n))
    double m10_fabs(d10_fabs0,d00_fabs0,v)
    double m10_logE(d10_logE1,d00_logE1,d00_fabs0)
  #define d10_exp2 d00_exp2
    i_VPi_Po=((-1)*(v_VPi_Po*d10_fabs0*d10_logE1*1/n)*d10_exp2);
    i=((-1)*d00_exp2);
  }
  }

  sys->setIQ(Pi,Po,i,0);
  sys->setGC(Pi,Po,Pi,Po,i_VPi_Po,0);
  printWarning("I(Pi,Po)=%e", i);
}



// --------------------------------------------------------------
// component definition
EXPORT tComponentInfo compInfo = {
  isNonLinear,                // component type ('isNonLinear' or 'isLinear')
  "pipenet1",                // model identifier
  "VerilogAMS model of pipenet1",  // component description
  2,                          // number of external nodes
  0,                          // number of internal nodes
  0,                          // number of inputs (system simulations only)
  2,                         // number of parameters
  params,                     // pointer to list of parameters
  0,                          // size of global variable buffer in bytes
  0,                          // pointer to component icon (0 = unused)
  0,                          // size of component icon
  -1,                         // index of parameter determining schematic symbol (-1 = unused)
  0,                          // pointer to list of schematic symbols
  (tEvaluate)fillMatrix,      // function calculating analog model (0 = no model exists)
  0,                          // function calculating noise model (0 = noise free)
  0,                          // function calculating system model (0 = no model exists)
  0,                          // string with digital Verilog model (0 = no model exists)
  0                           // string with digital VHDL model (0 = no model exists)
};