Register Tiling for Unstructured Sparsity in Neural Network

This artifact generates figures of the submitted draft of “Register Tiling for Unstructured Sparsity in Neural Network Inference”. The artifact generates graphs of the paper for an intel processor with 20 cores. The tested dataset is a collection of matrices from deep learning matrix collection (DLMC). The artifact is packaged as a singularity container and is set up on a supercomputer, Niagara in the Digital Research Alliance of Canada. For the latest version of the artifact, please check https://github.com/SpRegTiling/sparse-register-tiling