Published August 31, 2020
| Version v1
Conference paper
Open
Tunneling-based CMOS Floating Gate Synapse for Low Power Spike Timing Dependent Plasticity
- 1. Dipartimento di elettronica, informazione e bioingegneria, Politecnico di Milano, Piazza Leonardo da Vinci 32, I-20133 Milano, Italy; Faculty of Technology and Cognitive Interaction Technology Center of Excellence (CITEC), Universitat Bielefeld, Universitatsstraße 25, 33615 Bielefeld, Germany
- 2. Dipartimento di elettronica, informazione e bioingegneria, Politecnico di Milano, Piazza Leonardo da Vinci 32, I-20133 Milano, Italy
- 3. Istituto di Fotonica e Nanotecnologie, Consiglio Nazionale delle Ricerche, Piazza Leonardo da Vinci 32, I-20133 Milano, Italy
Description
We propose a CMOS architecture for spiking neural networks with permanent memory and online learning. It uses a three-transistors synapse with a floating node that stores the synaptic weight, programmed by using only Fowler-Nordheim tunneling current in the pA range for ultra-low power operation. A neuron with a conditioning circuit programs the floating gate synapse following the spike timing dependent plasticity rule. Simulations using a standard 150 nm CMOS process show the online learning capabilities of the architecture.
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Additional details
Funding
- European Commission
- NeuTouch - Understanding neural coding of touch as enabling technology for prosthetics and robotics 813713
- European Commission
- ICT-STREAMS - Silicon Photonics Transceiver and Routing technologies for High-End Multi-Socket Server Blades with Tb/s Throughput interconnect interfaces 688172