Dataset for: "Reducing OpenMP to FPGA Round-trip Times with Predictive Modelling"
This archive contains the samples generated for the conference paper "Reducing OpenMP to FPGA Round-trip Times with Predictive Modelling" (In Proc. 18th Intl. Workshop on OpenMP (IWOMP), Chattanooga, TN, Sept. 2022, Springer LNCS vol. 13527, pp. 94–108, https://doi.org/10.1007/978-3-031-15922-0_7).
Abstract: Recent works aimed at expanding the target offloading capabilities of OpenMP to FPGA platforms. While enabling the easy construction of heterogeneous systems, the approach has to face a major hurdle: by blurring the line between software and hardware development, it forces software developers to consider hardware limitations. This can be difficult through the abstractions that OpenMP introduces over the generated hardware. The high level synthesis tools used by OpenMP compilers to generate hardware already offer predictions on hardware usage. Their value for OpenMP offloading however is questionable. This paper is based on the data mining we conducted on thousands of kernel variations. It demonstrates and proofs under which circumstances these predictions can be trusted in the context of OpenMP to FPGA offloading and concludes by showing how to derive runtime performance predictions from them. The model we present can be used without experience in hardware development and quickly predicts runtime on our benchmarks with an average Pearson correlation of 0.897. This knowledge allows developers to make fast, informed design decisions.
- Is supplement to
- https://github.com/FAU-Inf2/OpenMP2FPGASamples/tree/1.0 (URL)