Research Artifact for ISFPGA'23: Eliminating Excessive Dynamism of Dataflow Circuits Using Model Checking

This is the public repo for the research artifact used in the submission of ISFPGA'23: Eliminating Excessive Dynamism of Dataflow Circuits Using Model Checking. In particular:

The file "fpga23-artifact-dhls-dhls-30-nov-spr-1-dec.zip" contains our contribution, and experiment results in raw log files;

The file "fpga23-artifact-shls.zip" contains the results produced from Vivado HLS, which are used for creating figure 10.