Bus interface editor

Bus interface editor is used to edit the details of a single bus interface. A bus interface is used to group ports together to form an interface that fulfills the requirements for a bus protocol. The editor has two tabs: the general tab which is used to set the details of the bus interface, and the port maps tab which is used to group the ports to the bus interface.

Name is a mandatory identifier for the bus interface.

Display name is an optional and used for a more user-friendly identifier.

Description is an optional field for textual description of the bus interface.

General settings

Interface mode is mandatory and has 7 possible choices:

Settings on the right side are mode-specific and change when the mode changes. The different modes are detailed in their respective sections below.

Addressable unit size defines how many bits are included in the least addressable unit of the bus interface. The default setting is byte addressable (8 bits).

Endianness indicates whether the interface is 'big-endian' or 'little-endian' (default).

Bit steering='on' implies that the interface is able to dynamically align data on different byte channels in case of addressable interfaces. The default setting when the bit steering is not set is off. Bit steering is not allowed in mirrored-masters, system or mirrored-system interface modes.

Connection required indicates that when instantiated in a design, this interface must be connected to some other interface and cannot be left unconnected.

Master

Address space defines the address space available for transactions on the bus interface. Address space is optional, but, if defined, base address becomes mandatory as well.

Base address is defines the starting address of the address space. Typically base address is 0.

Mirrored master

Mirrored master has no mode-specific options.

Slave

Memory map is optional and defines the memory map accessible through the bus interface. If a memory map has been defined, transparent bridges must be left empty.

Transparent bridges are optional and define the master bus interface(s) that all transactions to this bus interface are directed out of. If transparent bridges have been defined, memory map must be left empty.

Mirrored slave

Remap address defines an address offset for the slave bus interface conneted to this interface. Remap addressis optional, but, if defined, range becomes mandatory as well.

Range defines the address range available for the connected slave bus interface.

System and mirrored system

System group defines the group this bus interface is part of. The available system groups are defined in the referenced bus definition (see below).

Monitor

Interface mode is mandatory and defines the interface mode the monitor can be connected to.

Group defines the group this bus interface is part of when system or mirrored system interface mode is selected. For other modes group has no effect.

Bus definition

Bus definition is mandatory and contains a VLNV-reference to the bus definition document that defines the qualities that the bus interface must meet.

Abstraction definition

Abstraction definition contains an optional VLNV-reference to the abstraction definition document that defines the logical signals on the bus. Port maps define how they are connected to the physical ports on the component.

Parameters

Parameters are optional and can specify any parameter data value(s) specific for this bus interface. For more information on parameters, see the component parameter editor.