Ports editor provides a table containing all the ports of a component. This editor is used to add, remove and edit the ports.
Port name is a unique identifier and must match the name of the port in the implementation language. For example, the ports listed in the VHDL entity declaration are listed here.
Direction has four options:
Left and right bounds define the indices of a vectored port. The width of the port is higher bound - lower bound + 1, e.g. 3 downto 0 requires 4 bits. For scalar ports left bound = right bound. If either left bound or right bound is an expression, width cannot be set manually.
The port type is optional. Typical values in VHDL are 'std_logic' for scalar ports (i.e. 1 bit) and and 'std_logic_vector' for vectored ports (multibit).
The type definition is an optional language specific reference to where the type is defined, e.g. package or header file. Type definition will be included at the beginnig of the generated top-level code. In VHDL, 'std_logic' types are defined in 'IEEE.std_logic_1164.all' ('all' means that the whole package is included). In SystemC, the type definition is the include file name, e.g. 'systemc.h'. Type definition has no effect if type is not set.
Default value is optional and can be used to assign a value for an unconnected (input) port. This is used, for example, when generating a structural top-level VHDL for the hierarchical component where some input ports are not connected any other port in the design.
Array left and array right are optional and define the indices of an array port. The values can be given as an equation, but it must resolve into a decimal number. If either left or right value is given, the port is considered to be of an array type.
Port tags column displays the optional tags for a port. These can be used to group ports together
to, for example, create bus interfaces.
Ad-hoc column is a Kactus2-specific extension which is used in the graphical user interface of a
hierarchical design. Ad-hoc determines whether the port is shown as an ad-hoc port when the
component is instantiated in a design.
EXAMPLE: The component instances are
drawn as rectangles and their external interfaces are drawn to
the edges of the rectangle. There are different symbols for
different directions. The example instance in figure has 5
bus interfaces: clk, led, rst_n, from_hibi and
pkt_codec. Each interface includes 1 or multiple ports, and the
interface definition has its own VLNV. Moreover, user can select
that some ports are shown as Ad-hoc, e.g. if they are not
necessarily associated in any bus interface. Example figure
displays 2 ad-hoc ports: rx_av_in and led_out.
Description is an optional free text for further details.
Ports editor provides a context menu (right mouse button) that contains following options:
EXAMPLE. Figure shows the relation between VHDL source code and
port editor. Names, directions, and bounds are obvious. Width is extremely simple and
type and its definition are optinal.