Component instantiation editor

Component instantiation defines how a specific component instance is associated with a view. This editor can be used to edit the details of a component instantiation.

Name is a mandatory identifier for the component instantiation.

Display name is an optional and used for a more user-friendly identifier.

Description is an optional field for textual description of the component instantiation.

Implementation details

Language specifies the HDL used for a specific instantiation, for example, verilog or vhdl. Strict determines if the language shall be strictly enforced.

Library specifies the library name in which the model should be compiled.

Package describes the VHDL package containing the interface of the model. Defaults to the component VLNV name concatenated with the postfix _cmp_pkg, which stands for component package.

Module name describes the Verilog, SystemVerilog or SystemC module name or the VHDL entity name. Defaults to the component VLNV name.

Architecture describes the VHDL architecture name. Defaults to rtl.

Configuration describes the Verilog, SystemVerilog or VHDL configuration name. Defaults to the design configuration VLNV name of the design configuration referenced in the view, or to the component VLNV name concatenated with the postfix _rtl_cfg.

File set references

File set references is an optional list of file set names that are associated with the component instance. For example, the file set containing the RTL implementation file(s) of the module detailed in Implementation details could be referenced.

Default file build commands

Default file build commands is a list of build options for the file sets referenced in the containing view.

File type defines which files are build by the given command.

Build command defines how to build the files within the file set by e.g. running 'gcc' for C files or 'vcom' for VHDL.

Flags define the command line options for the command e.g. '-Wall'.

Replace default flags selects whether the given flags override the flags defined in the target file or are they appended to them. Replace default flags can be given as an expression, but it must evaluate to 1 or 0.

The defult file build commands contains a context menu, with the following functionalities:

Module parameters

Module parameters editor can be used to add, remove and modify module parameters. Module parameters are often used in HDL to configure component instances. They represent e.g VHDL generics and Verilog parameters.

All columns of the editor are editable. Double-clicking an empty space adds a new row.

Name column is mandatory. Display name provides a more user-friendly name for the module parameter. Description is free text for further details.

Legal data type depends on the language of the model. For example in VHDL this could be 'integer' or 'std_logic', whereas in C-language int or 'char*' could be used.

Type is an optional constraint for the type to which the module parameter value resolves. Possible types are:

Value contains the mandatory default value of the module parameter. This value can be overridden in a design that instantiates this component. The value is given in SystemVerilog format and may be given as an expression. Any other text must be enclosed within quotes e.g. "Any text".

By selecting a choice, the user can restrict the allowed module parameter values to a set of predefined values. Possible values are defined in the choices of the containing component.

Minimum value and maximum value define the lower and upper boundary for the module parameter value. If the selected type is bit or string, these fields have no effect.

OO usage specifies how this model parameter is used. Default is 'non-typed' since such parameters are found in all languages, i.e. all VHDL types are non-typed. 'Typed' parameters appear in object-oriented languages, i.e. in C++.

Resolve specifies the configuration of the model parameter. Possible resolve values are:

Bit vector left and bit vector right define the left and right bounds of the bit vector. These are valid only for a bit type parameter. A valid bit vector requires both the left and the right bit vector values.

Array left and Array right specify the left and right sides of array dimension for the parameter in an output language e.g. Verilog. Both of these are vendor attributes. The values can be given as an expression, but they must resolve into a decimal number. In order to get a valid array, both array left and array right values must be given.

Usage count displays the number of references made to this module parameter. Selecting the usage count of a module parameter displays a reference analysis for it. The usage count can not be changed manually.

Module parameters editor contains a context menu (rigth mouse button) that has the following options: