Address space editor

Address space editor can be used to edit the details of an address space within component. Address space defines a logical address space seen by a master bus interface. It can be split into smaller sgements.

On the left side are the editor fields that can be used to set the details of an address space. The right side contains a visualization displaying the address space in its current state and automatically updates on changes. It displays how the segments are positioned within the address space. Mismatches, e.g. sum of segment ranges being greater than address block range, can be easily spotted from the visualization.

Name is a mandatory identifier for the address space.

Display name is an optional and used for a more user-friendly identifier.

Description is an optional field for textual description of the address space.

Addressable unit bits (AUB) specifies the number of bits each address increment contains, e.g. 8 bits or 32 bits. The AUB is mandatory if the address space contains a local memory map.

Range is the size of the address space expressed as addressable units, i.e. the number of separate addresses.

Width is the data width of a row in bits. It defines the maximum size for a single transfer.

Is present is optional and allows enabling/disabling of a address space presence in a component. Value 1 indicates that the address space is present in the component whereas value 0 marks the address space to be treated as if it does not exist. Is present can be given as a SystemVerilog expression, but it must evaluate to 1 or 0.

Master interface binding shows the master bus interfaces bound to the address space. The binding can be set in the bus interface editor.

Segments

Segments editor can be used to describe sections of the address space, i.e. split it into smaller segments.

Name is a mandatory identifier for the segment.

Offset is mandatory and defines the starting address of the segment in address unit bits.

Range is mandatory and defines the size of the segment in address unit bits.

Is present is optional and allows enabling/disabling of a segment presence in an address space. Value 1 indicates that the segment is present in the address space whereas value 0 marks the segment to be treated as if it does not exist. Is present can be given as a SystemVerilog expression, but it must evaluate to 1 or 0.

Description is an optional field for textual description of the segment.

Local memory map

Local memory map is optional but some processors require specifying a memory map that is local to the component. It consists of address blocks similarly to the memory map of a slave bus interface. Hence, the address blocks can contain either memory or registers, and registers can contain bit fields.

Local memory map is useful for storing the programmer's view to interrupts registers, timers, and other local things. The overall address space of a component is a concatenation of local memory map (e.g. timers) and the memory maps of other units (e.g. registers of accelerator A, registers of accelerator B etc.)