General editor

General editor contains the general information of a component.

VLNV-identifier and the file path to the xml-file are shown on top. These fields cannot be modified after creation. Changes require that the component must be saved as new component with new VLNV.

Kactus attributes


Kactus-extension

Kactus attributes help to classify and categorize one's IPs. They are Kactus2-specific extension to the IP-XACT standard and describe the level (single IP vs. system), implementation style, and whether modification is allowed. Only the implementation style applies for SW components.

Attribute name Attribute value Value description
Product hierarchy Flat Does not fit into any other category.
Product Whole product, which may contain multiple boards and computers.
Board Represents circuit board, e.g. develoment- or final hardware platform.
Chip Represents a physical chip i.e. some specific FPGA-chip.
SoC A system on chip, set of intercconected IPs.
IP A single IP-block (which might be hierarchical)
Firmness Template Used as a base for creating new components, but must not be used as such. It should be copied and then saved with new VLNV.
Mutable Component is fully modifiable.
Fixed Component cannot be configured in any way and it is frozen to it's final state.
Implementation
(cannot be modified after creation)
HW Hardware implementation, such as VHDL or Verilog
SW Software implementation, such as C
SYS Contains information about the SW component mapping to the underlying HW platform.

Copyright information


Kactus-extension

Author is an optional field for the author of the component.

License is an optional field for identifying the license applicable to the component.

Description and XML header

Description text box can store a textual description of the component.

XML header shows and allows editing the comment lines in the beginning of XML file, i.e. those inside tags <!-- and -->.

Component preview

Component preview box at the bottom of the editor displays how the component will look like when instantiated in a design. The preview displays the bus interfaces of the component and also the ports that are marked as ad-hoc.