User can map the logical signals of a bus interface to the physical ports of the component. The physical ports are located in the top table, while the logical signals and port maps are located in the bottom table.
The port maps table consists of both the logical signals and the port maps referencing
logical signals. The table is constructed as a tree, where the port maps are child items of a logical
signal. Values for columns with an f(x) symbol can be given as expressions.
If a logical signal has been referenced only was in the port maps of the bus interface, information
of the port map is displayed on the same row as the logical signal.
If a single physical port is referenced in all the port maps referencing the logical signal, the
physical port name is displayed on the same row as the logical signal. If multiple port maps referencing
the same logical signal contain different physical ports, the name is displayed as [multiple].
The logical signal of a port map can be changed from the logical port column. This moves the
selected port map from its current position to the selected logical signal.
The physical port can be changed from the physical port column.
A port map can be defined by giving ranges for the logical and physical sides. These ranges determine how many and which bits are connected between the port and signal. These can be defined in the columns for the logical left, logical right, physical left and physical right.
Requirement informs the user of the port map requirement of the logical signal. The requirement is set in the abstraction abstraction definition of a bus definition, and cannot be edited here. The possible values are:
Tie off displays the possible logical tie off of the port map. A port map must contain either a reference to a physical port, or a logical tie off. The logical tie off indicates thate the physical connection for this logical port is the specified value.
The port maps tab of a bus interface editor is used to group the physical ports of the containing component to the logical signals listed in the associated abstraction definition.
The lower table contains the logical signals that were defined in the associated abstraction definition. The upper table contains a list of the physical ports in the component. The bottom table displays the mappings between logical signals and physical ports. The mapped physical ports are removed from the physical ports table unless Hide connected ports is unchecked.
The port directions are shown using the following icons:
Picture below depicts how the physical ports between two component instances are connected through their
bus interfaces.
The physical ports of the component
A are on the left and those of component B on the right. Logical signals are in the middle and the lines
denote port mappings. For example component A has mapped its port 'comm_out' to the logical signal 'COMM'
and component B has mapped its port comm_in to it. When user connects these interfaces together in a
design, the physical ports get connected.
All ports of the component do not need to be mapped in the interface nor do all the logical signals of the
abstraction definition need to be associated with a physical port. Abstraction definition defines the
directions of the signals in different interface modes thus making it possible to validate connections so
that two output ports are not accidentally connected to each other. In the figure above the abstraction
definition could have defined the DATA signal to have direction out in master interfaces and in at slave
interfaces.
A vectored physical port can be sliced to connect only part of it by assigning left and right bounds in the
mapping table. Picture below depicts how a part of the physical port can be connected.