Memory map editor

Memory map editor can be used to edit the details of a memory map.

Memory maps visualization is shown on the right of the editor. The visualization can be expandped and minimized by clicking the expand arrow expand and the minimize arrow minimize. Selecting any part of the visualization will open the editor set for that item. The visualization can be resized by dragging the border between the editor and the visualization. Holding Ctrl-key while scrolling with the mouse wheel increases/decreases the width of the items.

Name is a mandatory identifier for the memory map.

Display name is an optional and used for a more user-friendly identifier.

Description is an optional field for textual description of the memory map.

Address unit bits (AUB) defines the number of data bits each address increment of the memory map contains, e.g. 8b or 32b. The default setting for a memory map is byte addressable (8 bits). E.g. if AUB=8, then 32-bit registers are at addresses 0x0, 0x4, 0x8... If AUB=32, they are in addresses 0x0, 0x1, 0x2... AUB is the unit for base addresses and ranges within the address map.

Is present is optional and allows enabling/disabling of a memory map presence in a component. Value 1 indicates that the memory map is present in the component whereas value 0 marks the memory map to be treated as if it does not exist. Is present can be given as a SystemVerilog expression, but it must evaluate to 1 or 0.

Remap state identifies the name of the remap state for which the optional memory map elements are active. Memory maps are labeled with a default remap state, while memory remaps must be given a remap state. For more information on the remap states, see the remap states editor.

Slave interface binding shows which slave bus interfaces are used to access the memory map. The binding can only be set in the bus interface editor, but is shown here for convenience.

Address blocks table

Address block specifies a single contiguous block, either a set of registers or a block of memory. Registers within the address block are further divided into bit fields. (IP-XACT allows bank or subspaceMap elements within the address block, but they are not yet supported by Kactus2 (v3.3, December 2016)).

Name is a mandatory identifier for the address block.

Base address is mandatory and specifies the starting address for the address block. It is expressed as address unit bits as defined in the containing memory map, e.g. 8 or 32 bits.

Range is mandatory and specifies the size of the block in address unit bits.

Width is mandatory and specifies the data width in bits of a row in the address block. It sets the maximum allowed size of a single transfer and also defines the maximum size of a single register. Register can be smaller but not wider than the value.

Usage is optional and is used to categorize the usage of the address block. The possible values are:

Access is optional and is used to specify the accessibility of the address block. The possible values are:

Volatile is optional and indicates that the stored value may change without master's write operation. For example, the timer value gets updated automatically and master must always issue a read to get the latest value.

Is present is optional and allows enabling/disabling of a address block presence in a memory map. Value 1 indicates that the address block is present in the memory map whereas value 0 marks the memory map to be treated as if it does not exist. Is present can be given as a SystemVerilog expression, but it must evaluate to 1 or 0.

Description is an optional field for textual description of the address block.


EXAMPLE. A simple IP could have 1 memory map, 1 address block inside it, and three 32-bit registers: ctrl, data_in, and data_out. Ctrl allows both read and write accesses, data_in is write-only, and data_out is read-only. The lower part of ctrl register is divided into two 8-bit fields and designer can describe how they are used. The upper bits are not used. Data registers do not have field definitions.

Number of Addresss unit bits(AUB) of the memory map is set to 8 bits. There are 3 registers with identical size (32b), Hence, range = 12 = 3 * 32/AUB = 3 * 32/8 = 3 * 4. Let's assume base address=0x100. Since address block has 12 Bytes in total, it reserves the (byte) addresses 0x100-0x10B. It is good to set the width of the address block 32 b so that full register can be accessed at once. Smaller accesses (e.g. 1 byte at a time) are also allowed. screen_cap_of_mem_map_visualization