Address block editor

Address block editor is used to edit the details of an address block and the registers contained within it.

Name is a mandatory identifier for the address block. The name must be unique within all the address blocks of the containing memory map.

Display name is an optional and used for a more user-friendly identifier.

Description is an optional field for textual description of the address block.

Base address is mandatory and specifies the starting address for the address block in address unit bits.

Range is mandatory and specifies the size of the block in address units bits.

Width is mandatory and defines the data width of a row in the address block. The width value is given in bits.

Is present is optional and allows enabling/disabling of a address block presence in a memory map. Value 1 indicates that the address block is present in the memory mape whereas value 0 marks the address block to be treated as if it does not exist. Is present can be given as a SystemVerilog expression, but it must evaluate to 1 or 0.

Usage is a mandatory value to specify the usage of the address block and may have one of the following values:

Access is optional and specifies the accessability of the address block. The possible values are:

Volatile is optional and indicates whether the stored value may change without the master's write operation or not.

Registers table

The register table enables the user to define registers for the address block, with each row representing a single register. Each register must also contain at least one bit field.

Name is a mandatory identifier for the register.

Offset is mandatory and specifies the location of the register from the start of the containing address block expressed as number of addressing units. The actual address of the register is the sum of address block's base address and the register offset. E.g. if the base address is 'h100 and the register offset is 'h4, the register's address is 'h104. Offset can be given as a SystemVerilog expression.

Size is mandatory and defines the number of data bits the register contains. Size must be less than or equal to the width of the containing address block.

Dimension is optional and assigns an array dimension to the register. The register will be repeated in the address block as many times as indicated by the dimension value. By default, the dimension is presumed to be 0. Dimension 0 means that the register is not an array and will appear exactly once.

Volatile is optional and indicates whether the register value may change without a write operation to it, i.e. by an interrupt event, or not.

Access is optional and specifies the accessibility of the register. The possible values are:

Is present is optional and allows enabling/disabling of a register presence in an address block. Value 1 indicates that the register is present in the address block whereas value 0 marks the register to be treated as if it does not exist. Is present can be given as a SystemVerilog expression, but it must evaluate to 1 or 0.

Description is an optional field for textual description of the register.