Published February 29, 2020 | Version v1
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Sense Amplifier Half Buffer Based Ripple Carry Adder for IEEE 754 Standards

  • 1. Electronics & Communication Engineering Department, Vignan's Institute of Engineering for Women college, JNTUK, Visakhapatnam, Andhra Pradesh, India.
  • 2. Electronics & Communication Engineering Department, Vignan's Institute of Engineering for Women college, JNTUK Visakhapatnam, Andhra Pradesh, India.
  • 1. Publisher

Description

Addition is a specifically used indispensable computation used for most of the applications including digital systems and control systems. Adder is a primitive constituent used in the construction of digital IC; also it is an essential part of signal processing applications like DSP. The speed of an adder circuit holds a considerable influence on the total performance of digital circuits. The prime objective of this research is to design ripple carry adder using different asynchronous logics like Multithreshold null convention logic (MTNCL), Multi-threshold dual spacer dual rail delay insensitive logic (MTD3L) and proposed Sense amplifier half buffer logic (SAHB). SAHB is an asynchronous Quasi-Delay -Insensitive (QDI) method used to achieve significant functional speed of the circuit. The standard library cells (2-input AND/NAND, 2-input OR/NOR, 2-input XOR/XNOR) are designed using proposed SAHB logic to design an 8- bit Ripple Carry Adder circuit. The proposed SAHB logic design provides the solution of minimum delay with improved speed compared to the existing logic design techniques. The asynchronous logics are designed using mentor graphics tool with 130nm technology. Various performances attributes like power dissipation, delay and energy are tabulated and compared with existing logics.

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Journal article: 2249-8958 (ISSN)

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ISSN
2249-8958
Retrieval Number
C5312029320/2020┬ęBEIESP