a

Precision, Low Power

BiFET Op Amp

AD548

FEATURES

Enhanced Replacement for LF441 and TL061 DC Performance:

200 µA max Quiescent Current

2

10 pA max Bias Current, Warmed Up (AD548C) 250 µV max Offset Voltage (AD548C)

CONNECTION DIAGRAMS

Plastic Mini-DIP (N) Package and

1

SOIC (R)Package

2 µV/°C max Drift (AD548C)

2 µV p-p Noise, 0.1 Hz to 10 Hz AC Performance:

1.8 V/µs Slew Rate

OFFSET NULL

INVERTING

INPUT NONINVERTING

INPUT

NC V+


AD548

TOP VIEW

6

7

8

OUTPUT

3

1 MHz Unity Gain Bandwidth

Available in Plastic and Hermetic Metal Can Packages and in Chip Form

Available in Tape and Reel in Accordance with EIA-481A Standard

MIL-STD-883B Parts Available Dual Version Available: AD648

Surface-Mount (SOIC) Package Available

PRODUCT DESCRIPTION

The AD548 is a low power, precision monolithic operational amplifier. It offers both low bias current (10 pA max, warmed up) and low quiescent current (200 A max) and is fabricated with ion-implanted FET and laser wafer trimming technologies. Input bias current is guaranteed over the AD548’s entire common-mode voltage range.

The economical J grade has a maximum guaranteed input offset voltage of less than 2 mV and an input offset voltage drift of less than 20 V/C. This level of dc precision is achieved utilizing Analog’s laser wafer drift trimming process. The combination of low quiescent current and low offset voltage drift minimizes changes in input offset voltage due to self-heating effects.

The AD548 is recommended for any dual supply op amp applica- tion requiring low power and excellent dc and ac performance. In applications such as battery-powered, precision instrument front ends and CMOS DAC buffers, the AD548’s excellent com- bination of low input offset voltage and drift, low bias current, and low 1/f noise reduces output errors. High common-mode rejection (82 dB, min on the “B” grade) and high open-loop gain ensures better than 12-bit linearity in high impedance, buffer applications.

The AD548 is pinned out in a standard op amp configuration and is available in three performance grades. The AD548J and AD548K are rated over the commercial temperature range of 0C to 70C. The AD548B is rated over the industrial tempera- ture range of –40C to +85C.

The AD548 is available in an 8-lead plastic mini-DIP and surface-mount (SOIC) packages.

V– OFFSET

5

4

NULL


NOTE: PIN 4 CONNECTED TO CASE NC = NO CONNECT


10kfi

1 5


4 –15V

VOS TRIM TOP VIEW


PRODUCT HIGHLIGHTS

  1. A combination of low supply current, excellent dc and ac performance and low drift makes the AD548 the ideal op amp for high performance, low power applications.

  2. The AD548 is pin compatible with industry standard op amps such as the LF441, TL061, and AD542, enabling designers to improve performance while achieving a reduction in power dissipation of up to 85%.

  3. Guaranteed low input offset voltage (2 mV max) and drift (20 V/C max) for the AD548J are achieved utilizing Analog Devices’ laser drift trimming technology, eliminating the need for external trimming.

  4. Analog Devices specifies each device in the warmed-up condition, insuring that the device will meet its published specifications in actual use.

  5. A dual version, the AD648, is also available.

  6. Enhanced replacement for LF441 and TL061.


REV. D

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.


One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 www.analog.com

Fax: 781/326-8703 © Analog Devices, Inc., 2002

AD548–SPECIFICATIONS (@ 25°C and VS = ±15 V dc unless otherwise noted.)


Parameter

AD548J

Min Typ


Max


Min

AD548K/B

Typ


Max


Unit

INPUT OFFSET VOLTAGE1

Initial Offset TMIN to TMAX

vs. Temperature

vs. Supply

vs. Supply, TMIN to TMAX Long-Term Offset Stability


80

76/76/76


0.75


15


2.0

3.0/3.0/3.0

20


86

80


0.3


15


0.5

0.7/0.8

5


mV mV

V/C

dB dB

V/Month

INPUT BIAS CURRENT

Either Input2, VCM = 0

Either Input2 at TMAX, VCM = 0 Max Input Bias Current Over

Common-Mode Voltage Range Offset Current, VCM = 0

Offset Current at TMAX



5


20



3


10


pA



0.45/1.3/20



0.25/0.65

nA



30



15

pA


5

10


2

5

pA



0.25/0.65/10



0.15/0.35

nA

INPUT IMPEDANCE

Differential Common Mode


1 1012 3

3 1012 3


1 1012 3

3 1012 3


pF

pF

INPUT VOLTAGE RANGE

Differential3 Common Mode

Common-Mode Rejection VCM = 10 V

TMIN to TMAX VCM = 11 V

TMIN to TMAX


11


20

12



11


20

12



V V

76

90


82

92


dB

76/76/76

90


82

92


dB

70

84


76

86


dB

70/70/70

84


76

86


dB

INPUT VOLTAGE NOISE

Voltage 0.1 Hz to 10 Hz f = 10 Hz

f = 100 Hz

f = 1 kHz f = 10 kHz


2

80

40

30

30


2

80

40

30

30


V p-p nV/Hz nV/Hz

nV/Hz nV/Hz

INPUT CURRENT NOISE

f = 1 kHz


1.8


1.8


fA/Hz

FREQUENCY RESPONSE

Unity Gain, Small Signal Full Power Response

Slew Rate, Unity Gain Settling Time to 0.01%


0.8


1.0


1.0

30

1.8

8



0.8


1.0


1.0

30

1.8

8



MHz kHz V/s

s

OPEN LOOP GAIN

VO = 10 V, RL 10 k TMIN to TMAX, RL 10 k VO = 10 V, RL 5 k

TMIN to TMAX, RL 5 k


300

300/300/300

150

150/150/150


1000

700

500

300



300

300

150

150


1000

700

500

300



3V/mV V/mV V/mV

V/mV

OUTPUT CHARACTERISTICS


12

12/ 12/ 12

11

11/ 11/ 11


13

12.3


15



12

12

11

11


13

12.3


15



Voltage @ RL 10 k,

V

TMIN to TMAX


Voltage @ RL 5 k,

V

TMIN to TMAX

Short Circuit Current


mA

AD548

SPECIFICATIONS (continued)




Min

AD548J

Typ


Max


Min

AD548K/B

Typ


Max


Unit

POWER SUPPLY

Rated Performance

Operating Range Quiescent Current


4.5


15


170


18

200


4.5


15


170


18

200


V V

A

TEMPERATURE RANGE

Operating, Rated Performance Commercial (0C to 70C) Industrial (–40C to +85C)

Military (–55C to +125C)


AD548J AD548A AD548S


AD548K AD548B


PACKAGE OPTIONS SOIC (R-8)

Plastic (N-8) Tape and Reel


AD548JR

AD548JN4 AD548JR-REEL


AD548KR4

AD548KN AD548KR-REEL4


NOTES

1Input Offset Voltage specifications are guaranteed after five minutes of operation at TA = 25C.

2Bias Current specifications are guaranteed maximum at either input after five minutes of operation at TA = 25C. For higher temperature, the current doubles every 10C.

3Defined as voltages between inputs, such that neither exceeds 10 V from ground.

4Not recommended for new designs; obsolete April 2002.

Specifications subject to change without notice.

AD548

ABSOLUTE MAXIMUM RATINGSl

Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 V

Internal Power Dissipation2 . . . . . . . . . . . . . . . . . . . . 500 mW Input Voltage3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 V

Output Short Circuit Duration . . . . . . . . . . . . . . . . . Indefinite

Differential Input Voltage . . . . . . . . . . . . . . . . . . +VS and –VS Storage Temperature Range (Q, H) . . . . . . . –65C to +150C

(N, R) . . . . . . . . –65C to +125C

Operating Temperature Range

AD548J/K . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0C to 70C

AD548B . . . . . . . . . . . . . . . . . . . . . . . . . . . . –40C to +85C

Lead Temperature Range (Soldering 60 sec) . . . . . . . . . 300C


NOTES

1Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2Thermal Characteristics: 8-Pin SOIC Package: JA = 160C/W, JC = 42C/W; 8-Lead Plastic Package: JA = 90C/W.

3For supply voltages less than 18 V, the absolute maximum input voltage is equal to the supply voltage.


CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD548 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.


WARNING!


ESD SENSITIVE DEVICE

Typical Performance Characteristics– AD548


+VOUT

20 20 30




+VIN

INPUT VOLTAGE – V

15



–VIN

10


5


0 0 5 10 15 20

SUPPLY VOLTAGE – ±V


TPC 1. Input Voltage Range vs. Supply Voltage


15


25C

RL = 10kfi


–VOUT

OUTPUT VOLTAGE SWING – V

10


5


0 0 5 10 15 20

SUPPLY VOLTAGE – ±V


TPC 2. Output Voltage Swing vs. Supply Voltage

25


OUTPUT VOLTAGE SWING – V p-p

20


15


10


5


0

10 100 1k 10k

LOAD RESISTANCE –


TPC 3. Output Voltage Swing vs. Load Resistance



















200


QUIESCENT CURRENT – µA

180


160


140


120 0

10 100nA





































































10nA

INPUT BIAS CURRENT – pA

INPUT BIAS CURRENT

8

1nA


6 100pA


10pA

4

1pA


2

100fA


5 10 15

20

0

0

4

8 12

16

20


–25 5 35 65

95 125

SUPPLY VOLTAGE – ±V




SUPPLY VOLTAGE – ±V




TEMPERATURE – C


10fA

–55


TPC 4. Quiescent Current vs. Supply Voltage

TPC 5. Input Bias Current vs. Supply Voltage

TPC 6. Input Bias Current vs. Temperature




























10


INPUT BIAS CURRENT – pA

8


6


4


2


0

–10 –6 –2 2 6 10

COMMON-MODE VOLTAGE – V


TPC 7. Input Bias Current vs. Common-Mode Voltage

30












































25


IVOSI µV

20


15


10


5


0

0 10 20 30 40 50 60 70

WARM-UP TIME – Sec


TPC 8. Change in Offset Voltage vs. Warm-Up Time

1500


OPEN LOOP GAIN – V/mV







RL = 10kfi































1250


1000


750


500


250


0

–55 –25 5 35 65 95 125

TEMPERATURE – C


TPC 9. Open-Loop Gain vs. Temperature

AD548



100


80


OPEN LOOP GAIN – dB

60


40


20


0


–20


PHASE


GAIN


100


80


PHASE IN DEGREES

60


40


20


0


–20

120


OPEN LOOP VOLTAGE GAIN – dB























































110


100


90


80


70


120


POWER SUPPLY REJECTION – dB

100


80


60


40


20


0


+SUPPLY


–SUPPLY


–40


–40 1k 10k 100k 1M 10M

FREQUENCY – Hz


60

0 2 4 6 8 10 12 14 16 18

SUPPLY VOLTAGE – ±V


–20


100 1k 10k 100k 1M FREQUENCY – Hz

TPC 10. Open-Loop Frequency Response

TPC 11. Open-Loop Voltage Gain vs. Supply Voltage

TPC 12. PSRR vs. Frequency







































































































































































































































































































































90 22

80 20

OUTPUT VOLTAGE – V p-p

18

70 16

CMRR – dB

14

60

12

50 10

8

40 6

30 4

2

20 0

1k 10k 100k 1M


10


OUTPUT VOLTAGE SWING – V

5


0


–5


–10


10mV



1mV


10mV

1mV


FREQUENCY – Hz


TPC 13. CMRR vs. Frequency

10 100 1k 10k 100k 1M

FREQUENCY – Hz


TPC 14. Large Signal Frequency Response

0 2 4 6 8

SETTLING TIME – µs


TPC 15. Output Swing and Error Voltage vs. Output Settling Time



TOTAL HARMONIC DISTORTION – %




























































































FOLLOWER

WITH GAIN = 10









































































































































UNITY GAIN FOLLOWER



























4


1


0.1


0.01


0.001


160


INPUT NOISE VOLTAGE – nV/Hz

140


120


100


80


60


40


20


0


10,000


INPUT NOISE VOLTAGE – µV p-p

1,000


100


10


1


0


WHENEVER JOHNSON NOISE IS GREATER THAN AMPLIFIER NOISE, AMPLIFIER NOISE CAN BE CONSIDERED NEGLIGIBLE FOR APPLICATION

1kHz BANDWIDTH


RESISTOR JOHNSON NOISE


10Hz BANDWIDTH


AMPLIFIER GENERATED NOISE

100 1k 10k FREQUENCY – Hz


TPC 16. Total Harmonic Distortion vs. Frequency

100k

10 100 1k 10k 100k

FREQUENCY – Hz


TPC 17. Input Noise Voltage Spectral Density

100k 1M 10M 100M 1G 10G 100G SOURCE IMPEDANCE – fi

TPC 18. Total Noise vs. Source Impedance

AD548


TPC 19a. Unity Gain Follower

TPC 19b. Unity Gain Follower Pulse Response (Large Signal)

TPC 19c. Unity Gain Follower Pulse Response (Small Signal)


TPC 20a. Utility Gain Inverter

TPC 20b. Utility Gain Inverter Pulse Response (Large Signal)

TPC 20c. Unity Gain Inverter Pulse Response (Small Signal)


APPLICATION NOTES

The AD548 is a JFET-input op amp with a guaranteed maxi- mum IB of less than 10 pA, and offset and drift laser-trimmed to

0.5 mV and 5 V/C, respectively (AD548B). AC specs include 1 MHz bandwidth, 1.8 V/s typical slew rate and 8 s settling time for a 20 V step to 0.01%—all at a supply current less than 200 A. To capitalize on the device’s performance, a number of error sources should be considered.

The minimal power drain and low offset drift of the AD548 reduce self-heating or “warm-up” effects on input offset voltage, making the AD548 ideal for on/off battery-powered applica- tions. The power dissipation due to the AD548’s 200 A supply current has a negligible effect on input current, but heavy out-


LAYOUT


Figure 1. Offset Null Configuration

put loading will raise the chip temperature. Since a JFET’s input current doubles for every 10C rise in chip temperature, this can be a noticeable effect.

The amplifier is designed to be functional with power supply voltages as low as 4.5 V. It will exhibit a higher input offset voltage than at the rated supply voltage of 15 V, due to power supply rejection effects. The common-mode range of the AD548 extends from 3 V more positive than the negative supply to 1 V more negative than the positive supply. Designed to cleanly drive up to 10 k and 100 pF loads, the AD548 will drive a 2 k load with reduced open-loop gain.


OFFSET NULLING

Unlike bipolar input amplifiers, zeroing the input offset voltage of a BiFET op amp will not minimize offset drift. Using balance Pins 1 and 5 to adjust the input offset voltage as shown in Figure 1 will induce an added drift of 0.24 V/C per 100 V of nulled offset. The low initial offset (0.5 mV) of the AD548B results in only 0.6 V/C of additional drift.

To take full advantage of the AD548’s 10 pA max input current, parasitic leakages must be kept below an acceptable level. The practical limit of the resistance of epoxy or phenolic circuit board material is between 1 1012 and 3 1012 . This can result in an additional leakage of 5 pA between an input of 0 V and a –15 V supply line. Teflon® or a similar low leakage mate- rial (with a resistance exceeding 1017 ) should be used to isolate high impedance input lines from adjacent lines carrying high voltages. The insulator should be kept clean, since con- taminants will degrade the surface resistance.

A metal guard completely surrounding the high impedance nodes and driven by a voltage near the common-mode input potential can also be used to reduce some parasitic leakages. The guarding pattern in Figure 2 will reduce parasitic leakage due to finite board surface resistance; but it will not compensate for a low volume resistivity board.


Teflon is a registered trademark of DuPont.

AD548


Figure 2. Board Layout for Guarding Inputs

INPUT PROTECTION

The AD548 is guaranteed to withstand input voltages equal to the power supply potential. Exceeding the negative supply volt- age on either input will forward bias the substrate junction of the chip. The induced current may destroy the amplifier due to excess heat.

Input protection is required in applications such as a flame detector in a gas chromatograph, where a very high potential may be applied to the input terminals during a sensor fault condition. Figure 3 shows a simple current limiting scheme that can be used. RPROTECT should be chosen such that the maxi- mum overload current is 1.0 mA (l00 k for a 100 V overload, for example).

Exceeding the negative common-mode range on either input terminal causes a phase reversal at the output, forcing the amplifier output to the corresponding high or low state. Exceed- ing the negative common-mode on both inputs simultaneously forces the output high. Exceeding the positive common-mode range on a single input does not cause a phase reversal, but if both inputs exceed the limit the output will be forced high. In all cases, normal amplifier operation is resumed when input voltages are brought back within the common-mode range.


Figure 4. AD548 Used as DAC Output Amplifier

That is:

R

VOS Output VOS Input 1 RFB

O

RFB is the feedback resistor for the op amp, which is internal to the DAC. RO is the DAC’s R-2R ladder output resistance. The value of RO is code dependent. This has the effect of changing the offset error voltage at the amplifier’s output. An output amplifier with a sub millivolt input offset voltage is needed to preserve the linearity of the DAC’s transfer function.

The AD548 in this configuration provides a 700 kHz small signal bandwidth and 1.8 V/s typical slew rate. The 33 pF capacitor across the feedback resistor optimizes the circuit’s response. The oscilloscope charts in Figures 5 and 6 show small and large signal outputs of the circuit in Figure 4. Upper traces show the input signal VIN. Lower traces are the resulting output voltage with the DAC’s digital input set to all 1s. The AD548 settles to 0.01% for a 20 V input step in 14 s.



5V

20V




5µS












00










0




























































%










1

9



Figure 3. Input Protection of IV Converter

D/A CONVERTER OUTPUT BUFFER

The circuit in Figure 4 shows the AD548 and AD7545 12-bit CMOS D/A converter in a unipolar binary configuration. VOUT will be equal to VREF attenuated by a factor depending on the digital word. VREF sets the full scale. Overall gain is trimmed by adjusting RIN. The AD548’s low input offset voltage, low drift, and clean dynamics make it an attractive low power output buffer.

The input offset voltage of the AD548 output amplifier results in an output error voltage. This error voltage equals the input offset voltage of the op amp times the noise gain of the amplifier.


10

0


50mV


200mV



2µS






















0




























































%










Figure 5. Response to 20 V p-p Reference Square Wave


100

9


10

0


Figure 6. Response to 100 mV p-p Reference Square Wave

Application Hints–AD548

PHOTODIODE PREAMP

The performance of the photodiode preamp shown in Figure 7 is enhanced by the AD548’s low input current, input voltage offset, and offset voltage drift. The photodiode sources a current proportional to the incident light power on its surface. RF converts the photodiode current to an output voltage equal to RF IS.


Figure 7.

An error budget illustrating the importance of low amplifier input current, voltage offset, and offset voltage drift to minimize output voltage errors can be developed by considering the equi- valent circuit for the small (0.2 mm2 area) photodiode shown in Figure 7. The input current results in an error proportional to the feedback resistance used. The amplifier’s offset will produce an error proportional to the preamp’s noise gain (I + RF/RSH), where RSH is the photodiode shunt resistance. The amplifier’s input current will double with every 10C rise in temperature, and the photodiode’s shunt resistance halves with every 10C rise. The error budget in Figure 8 assumes a room temperature photodiode RSH of 500 M, and the maximum input current and input offset voltage specs of an AD548C.


TEMP

°C


RSH (Mfi)


VOS (µV)


(1+ RF/RSH) VOS


IB (pA)


IBRF


TOTAL

25

0

15,970

2,830

150

200

151 V

207 V

0.30

2.26

30 V

262 V

181 V

469 V

25

500

250

300 V

10.00

1.0 mV

1.30 mV

50

88.5

300

640 V

56.6

5.6 mV

6.24 mV

75

15.6

350

2.6 mV

320

32 mV

34.6 mV

85

7.8

370

5.1 mV

640

64 mV

69.1 mV

Figure 8. Photodiode Preamp Errors Over Temperature

The capacitance at the amplifier’s negative input (the sum of the photodiode’s shunt capacitance, the op amp’s differential input capacitance, stray capacitance due to wiring, etc.) will cause a rise in the preamp’s noise gain over frequency. This can result in excess noise over the bandwidth of interest. CF reduces the noise gain “peaking” at the expense of bandwidth.


INSTRUMENTATION AMPLIFIER

The AD548C’s maximum input current of 10 pA makes it an excellent building block for the high input impedance instru- mentation amplifier shown in Figure 9. Total current drain for this circuit is under 600 A. This configuration is optimal for conditioning differential voltages from high impedance sources.

The overall gain of the circuit is controlled by RG, resulting in the following transfer function:


Figure 9. Low Power Instrumentation Amplifier

Gains of 1 to 100 can be accommodated with gain nonlinearities of less than 0.01%. Input errors, which contribute an output error proportional to in amp gain, include a maximum untrimmed input offset voltage of 0.5 mV and an input offset voltage drift over temperature of 4 V/C. Output errors, which are indepen- dent of gain, will contribute an additional 0.5 mV offset and 4 V/C drift. The maximum input current is 15 pA over the common-mode range, with a common-mode impedance of over 1 1012 . Resistor pairs R3/R5 and R4/R6 should be ratio matched to 0.01% to take full advantage of the AD548’s high common-mode rejection. Capacitors C1 and C1 compensate for peaking in the gain over frequency caused by input capacitance when gains of 1 to 3 are used.

The –3 dB small signal bandwidth for this low power instrumenta- tion amplifier is 700 kHz for a gain of 1 and 10 kHz for a gain of

100. The typical output slew rate is 1.8 V/s.


LOG RATIO AMPLIFIER

Log ratio amplifiers are useful for a variety of signal conditioning applications, such as linearizing exponential transducer outputs and compressing analog signals having a wide dynamic range. The AD548’s picoamp level input current and low input offset voltage make it a good choice for the front-end amplifier of the log ratio circuit shown in Figure 10. This circuit produces an output voltage equal to the log base 10 of the ratio of the input currents I1 and I2. Resistive inputs R1 and R2 are provided for voltage inputs.

Input currents I1 and I2 set the collector currents of Q1 and Q2, a matched pair of logging transistors. Voltages at points A and B are developed according to the following familiar diode equation:

VBE (kT/q) ln ( IC /IES )

In this equation, k is Boltzmann’s constant, T is absolute tem- perature, q is an electron charge, and IES is the reverse saturation current of the logging transistors. The difference of these two voltages is taken by the subtractor section and scaled by a factor

VOUT VIN

1 ( R1 R2 )

RG

of approximately 16 by resistors R9, R10, and R8. Temperature

AD548

compensation is provided by resistors R8 and R15 that have a positive 3500 ppm/C temperature coefficient. The transfer function for the output voltage is:

VOUT 1V log10 ( I2/ I1)

Frequency compensation is provided by R11, R12, C1, and C2. Small signal bandwidth is approximately 300 kHz at input cur- rents above 100 A and will proportionally decrease with lower signal levels. D1, D2, R13, and R14 compensate for the effects of the two logging transistors’ ohmic emitter resistance.

To trim this circuit, set the two input currents to 10 A and adjust VOUT to zero by adjusting the potentiometer on A3. Then set I2 to 1 A and adjust the scale factor such that the output voltage is 1 V by trimming potentiometer R10. Offset adjustment for A1 and A2 is provided to increase the accuracy of the voltage inputs.

This circuit ensures a 1% log conformance error over an input current range of 300 pA to 1 mA, with low level accuracy limited by the AD548’s input current. The low level input voltage accuracy of this circuit is limited by the input offset voltage and drift of the AD548.



Figure 10. Log Ratio Amplifier

AD548

OUTLINE DIMENSIONS


Plastic Mini-DIP (N) Package

Dimensions shown in inches and (millimeters)

SOIC (R) Package

Dimensions shown in millimeters and (inches)


5.00 (0.1968)

4.80 (0.1890)


0.1574 (4.00)

0.1497 (3.80)


8

5

6.20 (0.2440)

4

1

5.80 (0.2284)


PIN 1


COPLANARITY 0.25 (0.0098)

0.10 (0.0040)


1.27 (0.0500) BSC


0.50 (0.0196)

0.25 (0.0099) X 45°

1.75 (0.0688)

1.35 (0.0532)

8°

SEATING PLANE

0.51 (0.0201)

0.33 (0.0130)

0.25 (0.0098) 0°

0.19 (0.0075)

1.27 (0.0500)

0.41 (0.0160)

CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN

COMPLIANT TO JEDEC STANDARDS MS-012 AA


Revision History

Location Page

Data Sheet changed from REV. C to REV. D.

Change to SOIC (R-8) Package 11

Edits to FEATURES 1

Deleted TO-99 CONNECTION DIAGRAM 1

Deleted AD548C from SPECIFICATIONS 2

Edits to ABSOLUTE MAXIMUM RATINGS 3

Deleted Metal Can from Figure 22 6

Deleted TO-99 (H) and Cerdip (Q) Packages from OUTLINE DIMENSIONS 8


PRINTED IN U.S.A.

C00510–0–5/02(D)

–12–

Mouser Electronics


Authorized Distributor


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