TSZ181, TSZ182


Datasheet


Very high accuracy (25 µV) high bandwidth (3 MHz) zero drift 5 V operational

amplifiers



DFN6 1.2x1.3 (TSZ181)


DFN8 2x2 (TSZ182)


SOT23-5 (TSZ181)


MiniSO8 (TSZ182)


SO8 (TSZ182)

Features


Description

Maturity status link

TSZ181

TSZ182

Related products

TSZ121

For zero drift amplifiers with more power savings

(400 kHz for 40 μA)

TSZ122

TSZ124

TSV711

For continuous-time precision amplifiers

TSV731

The TSZ181, TSZ182 are single and dual operational amplifiers featuring very low offset voltages with virtually zero drift versus temperature changes.

The TSZ181, TSZ182 offer rail-to-rail input and output, excellent speed/power consumption ratio, and 3 MHz gain bandwidth product, while consuming just 1 mA at 5 V. The device also features an ultra-low input bias current.

These features make the TSZ18x ideal for high-accuracy high-bandwidth sensor interfaces.



DS11863 - Rev 5 - August 2018

For further information contact your local STMicroelectronics sales office.


www.st.com

Package pin connections


  1. Package pin connections


    Figure 1. Pin connections for each package (top view)


    SOT23-5 (TSZ181)

    DFN6 1.2x1.3 (TSZ181)


    DFN8 2x2 (TSZ182) MiniSO8 and SO8 (TSZ182)


    1. The exposed pad of the DFN8 2x2 can be connected to VCC- or left floating.

      Absolute maximum ratings and operating conditions


  2. Absolute maximum ratings and operating conditions


    Table 1. Absolute maximum ratings (AMR)


    Symbol

    Parameter

    Value

    Unit

    VCC

    Supply voltage (1)

    6


    V

    Vid

    Differential input voltage (2)

    ±VCC

    Vin

    Input voltage (3)

    (VCC -) - 0.2 to (VCC +) + 0.2

    Iin

    Input current (4)

    10

    mA

    Tstg

    Storage temperature

    -65 to 150


    °C

    Tj

    Maximum junction temperature

    150


    Rthja


    Thermal resistance junction-to-ambient (5) (6)

    DFN8 2x2

    57


    °C/W

    DFN6 1.2x1.3

    232

    SOT23-5

    250

    MiniSO8

    190

    SO8

    125


    ESD

    HBM: human body model (7)

    4


    kV

    CDM: charged device model (8)

    1.5


    Latch-up immunity

    200

    mA

    1. All voltage values, except differential voltage, are with respect to network ground terminal.

    2. The differential voltage is the non-inverting input terminal with respect to the inverting input terminal.

    3. VCC - Vin must not exceed 6 V, Vin must not exceed 6 V.

    4. Input current must be limited by a resistor in series with the inputs.

    5. Rth are typical values.

    6. Short-circuits can cause excessive heating and destructive dissipation.

    7. Human body model: 100 pF discharged through a 1.5 kΩ resistor between two pins of the device, done for all couples of pin combinations with other pins floating.

    8. Charged device model: all pins plus package are charged together to the specified voltage and then discharged directly to ground.


      Table 2. Operating conditions


      Symbol

      Parameter

      Value

      Unit

      VCC

      Supply voltage

      2.2 to 5.5


      V

      Vicm

      Common mode input voltage range

      (VCC -) - 0.1 to (VCC +) + 0.1

      Toper

      Operating free-air temperature range

      -40 to 125

      °C


  3. Electrical characteristics


    Table 3. Electrical characteristics at V CC+ = 2.2 V with V CC- = 0 V, Vicm = V CC/2, T = 25 °C, and RL = 10 kΩ connected to V CC/2 (unless otherwise specified)


    Symbol

    Parameter

    Conditions

    Min.

    Typ.

    Max.

    Unit

    DC performance


    Vio


    Input offset voltage

    T = 25 °C


    3.5

    35


    µV

    -40 °C < T< 125 °C



    45

    ΔVio/ΔT

    Input offset voltage drift (1)

    -40 °C < T< 125 °C



    0.1

    µV/°C


    Iib


    Input bias current (Vout = VCC/2)

    T = 25 °C


    30

    200 (2)


    pA

    -40 °C < T< 125 °C



    300 (2)


    Iio


    Input offset current (Vout = VCC/2)

    T = 25 °C


    60

    400 (2)

    -40 °C < T< 125 °C



    600 (2)


    CMR1

    Common-mode rejection ratio, 20 log (ΔVicm/ ΔVio), Vic = 0 V to VCC, Vout = VCC/2,

    RL > 1 MΩ

    T = 25 °C

    96

    115



    dB

    -40 °C < T< 125 °C

    94




    CMR3

    Common mode rejection ratio, 20 log (ΔVicm/ ΔVio), Vic = 1.1 V to VCC, Vout = VCC/2,

    RL > 1 MΩ

    T = 25 °C

    102

    120


    -40 °C < T< 125 °C

    100




    Avd

    Large signal voltage gain, Vout = 0.5 V to (Vcc - 0.5 V)

    T = 25 °C

    112

    130


    -40 °C < T< 125 °C

    100




    VOH


    High-level output voltage, VOH = Vcc - Vout

    T = 25 °C


    15

    40


    mV

    -40 °C < T< 125 °C



    70


    VOL


    Low-level output voltage

    T = 25 °C


    10

    30

    -40 °C < T< 125 °C



    70


    Iout


    Isink (Vout = VCC)

    T = 25 °C

    4

    6



    mA

    -40 °C < T< 125 °C

    2.5




    Isource (Vout = 0 V)

    T = 25 °C

    3.5

    4


    -40 °C < T< 125 °C

    2




    ICC

    Supply current (per channel, Vout = VCC/2, RL > 1 MΩ)

    T = 25 °C


    0.7

    1

    -40 °C < T< 125 °C



    1.2

    AC performance


    GBP


    Gain bandwidth product

    T = 25 °C, RL = 10 kΩ,

    CL = 100 pF


    1.6


    2.3



    MHz

    -40 °C < T< 125 °C,

    RL = 10 kΩ, CL = 100 pF


    1.2



    Φm

    Phase margin


    RL = 10 kΩ, CL = 100 pF


    59


    degrees

    Gm

    Gain margin


    16


    dB


    SR


    Slew rate (3)

    T = 25 °C

    3

    4.6



    V/µs

    -40 °C < T< 125 °C

    2.5



    ts

    Settling time

    To 0.1%, Vin = 0.8 Vpp


    500


    ns


    Symbol

    Parameter

    Conditions

    Min.

    Typ.

    Max.

    Unit


    en


    Equivalent input noise voltage density

    f = 1 kHz


    50



    nV/√Hz

    f = 10 kHz


    50


    en-pp

    Voltage noise

    f = 0.1 to 10 Hz


    0.6


    µVpp

    Cs

    Channel separation

    f = 1 kHz


    120


    dB


    tinit


    Initialization time, G = 100 (4)

    T = 25 °C


    60



    µs

    -40 °C < T< 125 °C


    100


    1. See Section 5.5 Input offset voltage drift over temperature. Input offset measurements are performed on x100 gain configuration. The amplifiers and the gain setting resistors are at the same temperature.

    2. Guaranteed by design.

    3. Slew rate value is calculated as the average between positive and negative slew rates.

    4. Initialization time is defined as the delay between the moment when supply voltage exceeds 2.2 V and output voltage stabilization


    Table 4. Electrical characteristics at VCC+ = 3.3 V with VCC- = 0 V, Vicm = VCC/2, T = 25 °C, and RL = 10 kΩ connected to VCC/2 (unless otherwise specified)


    Symbol

    Parameter

    Conditions

    Min.

    Typ.

    Max.

    Unit

    DC performance


    Vio


    Input offset voltage

    T = 25 °C


    2

    30


    µV

    -40 °C < T< 125 °C



    40

    ΔVio/ΔT

    Input offset voltage drift (1)

    -40 °C < T< 125 °C



    0.1

    µV/°C


    Iib


    Input bias current (Vout = VCC/2)

    T = 25 °C


    30

    200 (2)


    pA

    -40 °C < T< 125 °C



    300 (2)


    Iio


    Input offset current (Vout = VCC/2)

    T = 25 °C


    60

    400 (2)

    -40 °C < T< 125 °C



    600 (2)


    CMR1


    Common mode rejection ratio, 20 log (ΔVicm/ ΔVio), Vout = VCC/2, RL > 1 MΩ

    Vic = 0 V to VCC,

    T = 25 °C


    104


    120



    dB

    Vic = 0 V to VCC,

    -40 °C < T< 125 °C


    102




    CMR2


    Common mode rejection ratio, 20 log (ΔVicm/ ΔVio), Vout = VCC/2, RL > 1 MΩ

    Vic = 0 V to VCC - 1.8 V,

    T = 25 °C


    106


    132


    Vic = 0 V to VCC - 2 V,

    -40 °C < T< 125 °C


    106




    Avd

    Large signal voltage gain, Vout = 0.5 V to (VCC - 0.5 V)

    T = 25 °C

    120

    138


    -40 °C < T< 125 °C

    110




    VOH


    High-level output voltage, VOH = Vcc - Vout

    T = 25 °C


    16

    40


    mV

    -40 °C < T< 125 °C



    70


    VOL


    Low-level output voltage

    T = 25 °C


    11

    30

    -40 °C < T< 125 °C



    70


    Symbol

    Parameter

    Conditions

    Min.

    Typ.

    Max.

    Unit


    Iout


    Isink (Vout = VCC)

    T = 25 °C

    10

    15



    mA

    -40 °C < T< 125 °C

    7.5




    Isource (Vout = 0 V)

    T = 25 °C

    6

    11


    -40 °C < T< 125 °C

    4




    ICC

    Supply current (per channel, Vout = VCC/2, RL > 1 MΩ)

    T = 25 °C


    0.7

    1


    mA

    -40 °C < T< 125 °C



    1.2

    AC performance


    GBP


    Gain bandwidth product

    T = 25 °C, RL = 10 kΩ,

    CL = 100 pF


    2


    2.8



    MHz

    -40 °C < T< 125 °C,

    RL = 10 kΩ, CL = 100 pF


    1.6



    Φm

    Phase margin


    RL = 10 kΩ, CL = 100 pF


    56


    degrees

    Gm

    Gain margin


    15


    dB


    SR


    Slew rate (3)

    T = 25 °C

    2.6

    4.5



    V/µs

    -40 °C < T< 125 °C

    2.1



    ts

    Settling time

    To 0.1%, Vin = 1.2 Vpp


    550


    ns


    en


    Equivalent input noise voltage density

    f = 1 kHz


    40



    nV/√Hz

    f = 10 kHz


    40


    en-pp

    Voltage noise

    f = 0.1 to 10 Hz


    0.5


    µVpp

    Cs

    Channel separation

    f = 1 kHz


    120


    dB


    tinit


    Initialization time, G = 100 (4)

    T = 25 °C


    60



    µs

    -40 °C < T< 125 °C


    100


    1. See Section 5.5 Input offset voltage drift over temperature. Input offset measurements are performed on x100 gain configuration. The amplifiers and the gain setting resistors are at the same temperature.

    2. Guaranteed by design.

    3. Slew rate value is calculated as the average between positive and negative slew rates.

    4. Initialization time is defined as the delay between the moment when supply voltage exceeds 2.2 V and output voltage stabilization


    Table 5. Electrical characteristics at VCC+ = 5 V with VCC- = 0 V, Vicm = VCC/2, T = 25 °C, and RL = 10 kΩ connected to VCC/2 (unless otherwise specified)


    Symbol

    Parameter

    Conditions

    Min.

    Typ.

    Max.

    Unit

    DC performance


    Vio


    Input offset voltage

    T = 25 °C


    1

    25


    µV

    -40 °C < T< 125 °C



    35

    ΔVio/ΔT

    Input offset voltage drift (1)

    -40 °C < T< 125 °C



    0.1

    µV/°C


    Iib


    Input bias current (Vout = VCC//2)

    T = 25 °C


    30

    200 (2)


    pA

    -40 °C < T< 125 °C



    300 (2)


    Iio


    Input offset current (Vout = VCC/2)

    T = 25 °C


    60

    400 (2)

    -40 °C < T< 125 °C



    600 (2)


    Symbol

    Parameter

    Conditions

    Min.

    Typ.

    Max.

    Unit


    CMR1


    Common mode rejection ratio, 20 log (ΔVicm/ ΔVio), Vout = VCC/2, RL > 1 MΩ

    Vic = 0 V to VCC ,

    T = 25 °C


    108


    126



    dB

    Vic = 0 V to VCC

    -40 °C < T< 125 °C


    108




    CMR2


    Common mode rejection ratio, 20 log (ΔVicm/ ΔVio), Vout = VCC/2, RL > 1 MΩ

    Vic = 0 V to VCC - 1.8 V,

    T = 25 °C


    112


    136


    Vic = 0 V to VCC - 2 V,

    -40 °C < T< 125 °C


    112




    SVR1

    Supply voltage rejection ratio, 20 log (ΔVCC/ ΔVio), VCC = 2.2 to 5.5 V, Vic = 0 V, RL > 1 MΩ

    T = 25 °C

    105

    123


    -40 °C < T< 125 °C

    104




    Avd

    Large signal voltage gain, Vout = 0.5 V to (Vcc - 0.5 V)

    T = 25 °C

    120

    144


    -40 °C < T< 125 °C

    110




    EMIRR

    (3)


    EMI rejection ratio, EMIRR = -20 log (VRFpeak/ ΔVio)

    VRF = 100 mVp, f = 400 MHz


    52


    VRF = 100 mVp, f = 900 MHz


    52


    VRF = 100 mVp, f = 1800 MHz


    72


    VRF = 100 mVp,f = 2400 MHz


    85



    VOH


    High-level output voltage, VOH = Vcc - Vout

    T = 25 °C


    18

    40


    mV

    -40 °C < T< 125 °C



    70


    VOL


    Low-level output voltage

    T = 25 °C


    13

    30

    -40 °C < T< 125 °C



    70


    Iout


    Isink (Vout = VCC)

    T = 25 °C

    20

    29



    mA

    -40 °C < T< 125 °C

    15




    Isource (Vout = 0 V)

    T = 25 °C

    15

    25


    -40 °C < T< 125 °C

    10




    ICC

    Supply current (per channel, Vout = VCC/2, RL > 1 MΩ)

    T = 25 °C


    0.8

    1

    -40 °C < T< 125 °C



    1.2

    AC performance


    GBP


    Gain bandwidth product

    T = 25 °C, RL = 10 kΩ,

    CL = 100 pF


    2


    3



    MHz

    -40 °C < T< 125 °C, RL = 10 kΩ,

    CL = 100 pF


    1.6



    Φm

    Phase margin


    RL = 10 kΩ, CL = 100 pF


    56


    degrees

    Gm

    Gain margin


    15


    dB


    SR


    Slew rate (4)

    T = 25 °C

    2.9

    4.7



    V/µs

    -40 °C < T< 125 °C

    2.4




    ts


    Settling time

    To 0.1 %, Vin = 1.5 Vpp


    600


    ns

    To 0.01 %, Vin = 1 Vpp


    4


    µs


    en


    Equivalent input noise voltage

    f = 1 kHz


    37



    nV/√Hz

    f = 10 kHz


    37


    en-pp

    Voltage noise

    f = 0.1 to 10 Hz


    0.4


    µVpp


    Symbol

    Parameter

    Conditions

    Min.

    Typ.

    Max.

    Unit

    Cs

    Channel separation

    f = 100 Hz


    135


    dB


    tinit


    Initialization time, G = 100 (5)

    T = 25 °C


    60



    µs

    -40 °C < T< 125 °C


    100


    1. See Section 5.5 Input offset voltage drift over temperature. Input offset measurements are performed on x100 gain configuration. The amplifiers and the gain setting resistors are at the same temperature.

    2. Guaranteed by design

    3. Tested on the MiniSO8 package, RF injection on the IN- pin

    4. Slew rate value is calculated as the average between positive and negative slew rates

    5. Initialization time is defined as the delay between the moment when supply voltage exceeds 2.2 V and output voltage stabilization


    Figure 6. Input offset voltage distribution at VCC = 5 V, T = 125 °C

    Figure 4. Input offset voltage distribution at VCC = 3.3 V

  4. Electrical characteristic curves


    Figure 2. Supply current vs. supply voltage

    Figure 3. Input offset voltage distribution at VCC = 5 V



    Figure 5. Input offset voltage distribution at VCC = 2.2 V



    Figure 7. Input offset voltage distribution at VCC = 5 V, T = -40 °C

    Figure 8. Input offset voltage distribution at VCC = 2.2 V, T = 125 °C

    Figure 12. Input offset voltage vs. input common-mode at VCC = 3.3 V

    Figure 13. Input offset voltage vs. input common-mode at VCC = 2.2 V


    Figure 9. Input offset voltage distribution at VCC = 2.2 V, T = -40 °C



    Figure 10. Input offset voltage vs. supply voltage

    Figure 11. Input offset voltage vs. input common-mode at VCC = 5.5 V






























































































































































































































































    Figure 18. Output current vs. output voltage at VCC = 2.2 V

    Figure 19. Input bias current vs. common-mode at VCC = 5 V

    Vcc=5V T=25°C



    Figure 14. Input offset voltage vs. temperature

    Figure 15. VOH vs. supply voltage


    Figure 16. VOL vs. supply voltage

    Figure 17. Output current vs. output voltage at VCC = 5.5 V

    Vcc = 5V

    Vicm = Vcc/2


    Figure 20. Input bias current vs. temperature at VCC = 5 V

    Figure 21. Output rail linearity


    Figure 22. Bode diagram at VCC = 5.5 V

    Figure 23. Bode diagram at VCC = 2.2 V



    Figure 24. Bode diagram at VCC = 3.3 V

    Figure 25. Open loop gain vs. frequency



    Figure 26. Positive slew rate vs. supply voltage

    Figure 27. Negative slew rate vs. supply voltage



    Figure 28. Noise 0.1 - 10 Hz vs. time

    Figure 29. Noise vs. frequency



    Figure 30. Noise vs. frequency and temperature

    Figure 31. Output overshoot vs. load capacitance

    Figure 36. Negative overvoltage recovery VCC = 2.2 V



    Figure 32. Small signal VCC = 5 V

    Figure 33. Small signal VCC = 2.2 V


























    Figure 34. Large signal VCC = 5 V

    Figure 35. Large signal VCC = 2.2 V


    Figure 37. Positive overvoltage recovery VCC = 2.2 V


    Figure 38. Output impedance vs. frequency Figure 39. Settling time positive step (-2 V to 0 V)


    Figure 40. Settling time negative step (2 V to 0 V) Figure 41. Settling time positive step (-0.8 V to 0 V)


    Figure 42. Settling time negative step (0.8 V to 0 V) Figure 43. Maximum output voltage vs. frequency



    Figure 44. Crosstalk vs. frequency

    Figure 45. PSRR vs. frequency

    Application information


  5. Application information


    1. Operation theory

      The TSZ18x is a high precision CMOS device. It can achieve a low offset drift and no 1/f noise thanks to its chopper architecture. Chopper-stabilized amps constantly correct low-frequency errors across the inputs of the amplifier.

      Chopper-stabilized amplifiers can be explained with respect to:

      • Time domain

      • Frequency domain


      1. Time domain

        The basis of the chopper amplifier is realized in two steps. These steps are synchronized thanks to a clock running at 2.4 MHz.


        Figure 46. Block diagram in the time domain (step 1)



        Vinp Vinn

        Chop 1 Chop 2



        A1(f)


        A2(f)


        Filter Vo ut


        Figure 47. Block diagram in the time domain (step 2)



        Vinp

        Chop 1 Chop 2


        V

        Vinn

        A1(f)

        A2 (f)

        Filter

        o ut


        Figure 46. Block diagram in the time domain (step 1) shows step 1, the first clock cycle, where Vio is amplified in the normal way.

        Figure 47. Block diagram in the time domain (step 2) shows step 2, the second clock cycle, where Chop1 and Chop2 swap paths. At this time, the Vio is amplified in a reverse way as compared to step 1.

        At the end of these two steps, the average Vio is close to zero.

        The A2(f) amplifier has a small impact on the Vio because the Vio is expressed as the input offset and is consequently divided by A1(f).

        In the time domain, the offset part of the output signal before filtering is shown in Figure 48. Vio cancellation principle.

        Operating voltages



        Figure 48. Vio cancellation principle


        Step 1 Step 1 S te p 1


        Vio


        Vio


        Time


        Step 2 Step 2 S te p 2



        The low pass filter averages the output value resulting in the cancellation of the Vio offset.

        The 1/f noise can be considered as an offset in low frequency and it is canceled like the Vio, thanks to the chopper technique.


      2. Frequency domain

        The frequency domain gives a more accurate vision of chopper-stabilized amplifier architecture.


        Figure 49. Block diagram in the frequency domain


        Chop1

        Vinn

        Vi np


        A(f)


        A(f)


        Filter


        Vout


        Chop2

        Vos + Vn

        1 2 3 4


        The modulation technique transposes the signal to a higher frequency where there is no 1/f noise, and demodulate it back after amplification.

        1. According to Figure 49. Block diagram in the frequency domain, the input signal Vin is modulated once (Chop1) so all the input signal is transposed to the high frequency domain.

        2. The amplifier adds its own error (Vio (output offset voltage) + the noise Vn (1/f noise)) to this modulated signal.

        3. This signal is then demodulated (Chop2), but since the noise and the offset are modulated only once, they are transposed to the high frequency, leaving the output signal of the amplifier without any offset and low frequency noise. Consequently, the input signal is amplified with a very low offset and 1/f noise.

        4. To get rid of the high frequency part of the output signal (which is useless) a low pass filter is implemented.

          To further suppress the remaining ripple down to a desired level, another low pass filter may be added externally on the output of the TSZ18x.


    1. Operating voltages

      The TSZ18x device can operate from 2.2 to 5.5 V. The parameters are fully specified for 2.2 V, 3.3 V, and 5 V power supplies. However, the parameters are very stable in the full VCC range and several characterization curves show the TSZ18x device characteristics at 2.2 V and 5.5 V. Additionally, the main specifications are guaranteed in extended temperature ranges from -40 to 125 °C.


    2. Input pin voltage ranges

      The TSZ18x device has internal ESD diode protection on the inputs. These diodes are connected between the input and each supply rail to protect the input MOSFETs from electrical discharge.

      Rail-to-rail input/output



      If the input pin voltage exceeds the power supply by 0.5 V, the ESD diodes become conductive and excessive current can flow through them. Without limitation this over current can damage the device.

      In this case, it is important to limit the current to 10 mA, by adding resistance on the input pin, as described in Figure 50. Input current limitation.


      Figure 50. Input current limitation


      VCC+


      -

      Vin +

      R


      VCC-


    3. Rail-to-rail input/output

      The TSZ18x has a rail-to-rail input, and the input common mode range is extended from (VCC -) - 0.1 V to (VCC+)

      + 0.1 V.

      The operational amplifier output levels can go close to the rails: to a maximum of 40 mV above and below the rail when connected to a 10 kΩ resistive load to VCC/2.


    4. Input offset voltage drift over temperature

      The maximum input voltage drift variation over temperature is defined as the offset variation related to the offset value measured at 25 °C. The operational amplifier is one of the main circuits of the signal conditioning chain, and the amplifier input offset is a major contributor to the chain accuracy. The signal chain accuracy at 25 °C can be compensated during production at application level. The maximum input voltage drift over temperature enables the system designer to anticipate the effect of temperature variations.

      The maximum input voltage drift over temperature is computed using Equation 1.

      Equation 1

      ∆Vio = ma x VioTVio 25 °C

      ∆T


      Where T = -40 °C and 125 °C.

      T 25 °C

      The TSZ18x datasheet maximum value is guaranteed by measurements on a representative sample size ensuring a Cpk (process capability index) greater than 1.3.


    5. Capacitive load

      Driving large capacitive loads can cause stability problems. Increasing the load capacitance produces gain peaking in the frequency response, with overshoot and ringing in the step response. It is usually considered that with a gain peaking higher than 2.3 dB an op amp might become unstable.

      Generally, the unity gain configuration is the worst case for stability and the ability to drive large capacitive loads.

      Figure 51. Stability criteria with a serial resistor at VCC = 5 V, Figure 52. Stability criteria with a serial resistor at VCC = 3.3 V, and Figure 53. Stability criteria with a serial resistor at VCC = 2.2 V show the serial resistors that must be added to the output, to make a system stable. Figure 54. Test configuration for Riso shows the test configuration using an isolation resistor, Riso.

      Capacitive load



      Figure 51. Stability criteria with a serial resistor at VCC = 5 V


      Figure 52. Stability criteria with a serial resistor at VCC = 3.3 V


      Figure 53. Stability criteria with a serial resistor at VCC = 2.2 V

      PCB layout recommendations



      Figure 54. Test configuration for Riso



      -

      VIN +


      +VCC


      -VCC


      Riso


      Cload


      VOUT 10 kΩ



      Note that the resistance Riso is in series with Rload and thus acts as a voltage divider, and reduces the output swing a little. Thanks to the natural good stability of TSZ18x, the Riso needed to keep the system stable when the capacitive load exceeds 200pF is lower than 50 Ω (VCC = 5 V), and so the error introduced is generally negligible.

      The Riso also modifies the open loop gain of the circuit, and tends to improve the phase margin as described in Table 6. Riso impact on stability.


      Table 6. Riso impact on stability


      Capacitive load



      100 pF

      1 nF

      10 nF

      100 nF

      1 µF

      Riso (Ω)

      0

      100

      47

      100

      22

      47

      8

      13

      10

      6

      Measured overshoot (%)

      20.9

      15

      23

      9

      16

      8

      21

      10

      12

      8

      Estimated phase margin (°)

      47

      53

      46

      59

      52

      61

      47

      58

      56

      61


    6. PCB layout recommendations

      Particular attention must be paid to the layout of the PCB tracks connected to the amplifier, load and power supply. It is good practice to use short and wide PCB traces to minimize voltage drops and parasitic inductance.

      To minimize parasitic impedance over the entire surface, a multi-via technique that connects the bottom and top layer ground planes together in many locations is often used.

      The copper traces that connect the output pins to the load and supply pins should be as wide as possible to minimize trace resistance.

      A ground plane generally helps to reduce EMI, which is why it is generally recommended to use a multilayer PCB and use the ground plane as a shield to protect the internal track. In this case, pay attention to separate the digital from the analog ground and avoid any ground loop.

      Place external components as close as possible to the op amp and keep the gain resistances, Rf and Rg, close to the inverting pin to minimize parasitic capacitances.


    7. Optimized application recommendation

      The TSZ18x is based on a chopper architecture. As the device includes internal switching circuitry, it is strongly recommended to place a 0.1 µF capacitor as close as possible to the supply pins.

      A good decoupling has several advantages for an application. First, it helps to reduce electromagnetic interference. Due to the modulation of the chopper, the decoupling capacitance also helps to reject the small ripple that may appear on the output.

      The TSZ18x has been optimized for use with 10 kΩ in the feedback loop. With this, or a higher value resistance, this device offers the best performance.

      EMI rejection ration (EMIRR)



    8. EMI rejection ration (EMIRR)

      The electromagnetic interference (EMI) rejection ratio, or EMIRR, describes the EMI immunity of operational amplifiers. An adverse effect that is common to many op amps is a change in the offset voltage as a result of RF signal rectification.

      The TSZ18x has been specially designed to minimize susceptibility to EMIRR and show an extremely good sensitivity. Figure 55. EMIRR on IN+ pin shows the EMIRR IN+, Figure 56. EMIRR on IN- pin shows the EMIRR IN- of the TSZ18x measured from 10 MHz up to 2.4 GHz.


      Figure 55. EMIRR on IN+ pin


      Figure 56. EMIRR on IN- pin



    9. 1/f noise

      1/f noise, also known as pink noise or flicker noise, is caused by defects, at the atomic level, in semiconductor devices. The noise is a non-periodic signal and it cannot be calibrated. So for an application requiring precision, it is extremely important to take this noise into account.

      1/f noise is a major noise contributor at low frequencies and causes a significant output voltage offset when amplified by the noise gain of the circuit. But, the TSZ18x, thanks to its chopper architecture, rejects 1/f noise and thus makes this device an excellent choice for DC high precision applications.

      As shown in Figure 28. Noise 0.1 - 10 Hz vs. time, 0.1 Hz to 10 Hz amplifier voltage noise is only 400 nVpp for a VCC = 5 V. Figure 29. Noise vs. frequency and Figure 30. Noise vs. frequency and temperature show the voltage noise density of the amplifier with no 1/f noise on a large bandwith. Figure 57. Noise vs frequency between 0.1 and 10 Hz exhibiting no 1/f noise below depicts noise vs frequency between 0.1 and 10 Hz exhibiting no 1/f noise.

      Overload recovery



      Figure 57. Noise vs frequency between 0.1 and 10 Hz exhibiting no 1/f noise



    10. Overload recovery

      Overload recovery is defined as the time required for the op amp output to recover from a saturated state to a linear state.

      The saturation state occurs when the output voltage gets very close to either rail in the application. It can happen due to an excessive input voltage or when the gain setting is too high.

      When the output of the TSZ18x enters in saturation state it needs 10 µs to get back to a linear state as shown in Figure 58. Negative overvoltage recovery VCC = 5 V and Figure 59. Positive overvoltage recovery VCC = 5 V.

      Figure 36. Negative overvoltage recovery VCC = 2.2 V and Figure 37. Positive overvoltage recovery VCC = 2.2 V show the overvoltage recovery for a VCC = 2.2 V.


      Figure 59. Positive overvoltage recovery VCC = 5 V


      Figure 58. Negative overvoltage recovery VCC = 5 V

    11. Phase reversal protection

      Some op amps can show a phase reversal when the common-mode voltage exceeds the VCC range.

      Phase reversal is a specific behavior of an op amp where its output reacts as if the inputs were inverted when at least one input is out of the specified common-mode voltage.

      The TSZ18x has been carefully designed to prevent any output phase reversal. The TSZ18x is a rail-to-rail input op amp, therefore, the common-mode range can extend up to the rails. If the input signal goes above the rail it does not cause any inversion of the output signal as shown in Figure 60. No phase reversal.

      If, in the application, the operating common-mode voltage is exceeded please read Section 5.3 Input pin voltage ranges.

      Open loop gain close to the rail



      Figure 60. No phase reversal



    12. Open loop gain close to the rail

      One of the key parameters of current measurement in low-side applications is precision. Moreover, it is generally interesting to be able to make a measurement when there is no current through the shunt resistance. But, when the output voltage gets close the rail some internal transistors saturate resulting in a loss of open loop gain.

      Therefore, the output voltage can be as high as several mV while it is expected to be close to 0 V.

      The TSZ18x has been designed to keep a high gain even when the op amp output is very close to the rail, to ensure good accuracy at low current.

      Figure 61. Gain vs. output voltage, VCC = 5 V, RI = 10 kΩ to GND shows the open loop gain of the TSZ18x vs. output voltage. A single power supply of 5 V and a common-mode voltage of 0 V is used, with a 10 kΩ resistor connected to GND.


      Figure 61. Gain vs. output voltage, VCC = 5 V, RI = 10 kΩ to GND










































































































































    13. Application examples


      1. Measuring gas concentration using the NDIR principle (thermopile)

        A thermopile is a serial interconnected array of thermocouples. Based on the Seebeck principle, a thermocouple is able to deliver an output voltage which depends on the temperature difference between a reference junction and an active junction.

        An NDIR sensor (non dispersive infrared) is generally composed of an infrared (IR) source, an optical cavity, a dual channel detector, and an internal thermistor. Both channels are made with a thermopile. One channel is considered as a reference and the other is considered as the active channel.


        Certain gases absorb IR radiation at a specific wavelength. Each channel has a specific wavelength filter. The active channel has a filter centered on gas absorption while the reference channel has a filter on another wavelength which is still in the IR range.

        When a gas enters the optical cavity, the radiation hitting the active channel decreases, whereas it remains the same on the reference channel.

        The difference between the reference and active channel gives the concentration of gas present in the optical cavity.

        As the thermopile delivers extremely low voltages (hundreds of µV to several mV) the output signal must be amplified with a high gain and a very low offset in order to minimize DC errors.

        Moreover, the drift of Vio depending on temperature must be as low as possible not to impact the measurement once the calibration has been made.

        An NDIR sensor generally works at low frequency and the noise of the amplifiers must be as low as possible (0.1-10 Hz en-pp = 0.4 µVpp).

        Thanks to its chopper architecture, the TSZ18x combines all these specifications, particularly in having a ΔVio/Δt of 0.1 µV/°C, no 1/f noise in low frequency, and a white noise of 37 nV/√Hz.

        Figure 62. Principle schematic shows an NDIR gas sensing schematic where the active and reference channels are pre-amplified before treatment by an ADC thanks to the TSZ18x.

        A Vref voltage (in hundreds of mV) can be used to ensure the amplifiers are not saturated when the signal is close to the low rail. A gain of 1000 is used to allow amplification of the signal coming from the NDIR sensor (3 mV).


        Figure 62. Principle schematic


        100 nF



        Vref

        10 Ω

        VL

        10 kΩ


        Vcc


        -


        Ref.ch


        Act. ch


        ADC3


        10 nF

        10 nF


        10 Ω

        TSZ182_a

        +


        +

        TSZ182_b

        -

        ADC1


        ADC2


        10 kΩ


        100 nF


      2. Precision instrumentation amplifier

        The instrumentation amplifier uses three op amps. The circuit, shown in Figure 63. Precision instrumentation amplifier schematic, exhibits high input impedance, so that the source impedance of the connected sensor has no impact on the amplification.


        Figure 63. Precision instrumentation amplifier schematic



        V1 +

        -

        TSZ182


        R2 R4


        Rf

        -

        Rg +

        Rf


        TSZ181


        Vout


        -

        V2 +


        TSZ182

        R1 R3



        The gain is set by tuning the Rg resistor. To have the best performance, it is suggested to have R1 = R2 = R3 = R4. The output is given by Equation 2.

        Equation 2


        The matching of R1, R2 and R3, R4 is important to ensure a good common mode rejection ratio (CMR).


      3. Low-side current sensing

Power management mechanisms are found in most electronic systems. Current sensing is useful for protecting applications. The low-side current sensing method consists of placing a sense resistor between the load and the circuit ground. The resulting voltage drop is amplified using the TSZ181 (see Figure 64. Low-side current sensing schematic).


Figure 64. Low-side current sensing schematic


C1



Rshunt


Rg 1


I

In

-

+

Ip


Rf1


5 V

+

-


T SZ181


Vout

Rg 2


Rf2


Vout can be expressed as follows:

Equation 3


Vou t


= Rshun t


× I 1 –

Rg2 Rg2 + Rf2

1 + Rf1

Rg1

+ I Rg2 × Rf2

p Rg2 + Rf2

× 1 + Rf1

Rg1


– ln


× Rf1


– Vio

1 + Rf1

Rg1

Assuming that Rf2 = Rf1 = Rf and Rg2 = Rg1 = Rg, Equation 3 can be simplified as follows:

Equation 4


Vout


= Rshunt

× I Rf

Rg


Vio

1 + Rf

Rg


+ Rf × Iio


The main advantage of using the chopper of the TSZ18x for a low-side current sensing, is that the errors due to Vio and Iio are extremely low and may be neglected.

Therefore, for the same accuracy, the shunt resistor can be chosen with a lower value, resulting in lower power dissipation, lower drop in the ground path, and lower cost.

Particular attention must be paid to the matching and precision of Rg1, Rg2, Rf1, and Rf2, to maximize the accuracy of the measurement.

Package information


6 Package information


In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark.


6.1 DFN6 1.2 x 1.3 package information


Figure 65. DFN6 1.2 x 1.3 package outline


BOTTOM VIEW

e


b


PIN#1 ID


L L3


SIDE VIEW






A1


SEATING PLANE



A C


C

8

0.05

TOP VIEW D


E


PIN 1


Table 7. DFN6 1.2 x 1.3 mechanical data



Ref

Dimensions

Millimeters

Inches

Min.

Typ.

Max.

Min.

Typ.

Max.

A

0.31

0.38

0.40

0.012

0.015

0.016

A1

0.00

0.02

0.05

0.000

0.001

0.002

b

0.15

0.18

0.25

0.006

0.007

0.010

c


0.05



0.002


D


1.20



0.047


E


1.30



0.051


e


0.40



0.016


L

0.475

0.525

0.575

0.019

0.021

0.023

L3

0.375

0.425

0.475

0.015

0.017

0.019


Figure 66. DFN6 1.2 x 1.3 recommended footprint



0.40


0.25


3 1


1.20


0.475


4 6

DFN8 2 x 2 package information



    1. DFN8 2 x 2 package information


      Figure 67. DFN8 2 x 2 package outline



      Table 8. DFN8 2 x 2 mechanical data



      Ref.

      Dimensions

      Millimeters

      Inches

      Min.

      Typ.

      Max.

      Min.

      Typ.

      Max.

      A

      0.51

      0.55

      0.60

      0.020

      0.022

      0.024

      A1



      0.05



      0.002

      A3


      0.15



      0.006


      b

      0.18

      0.25

      0.30

      0.007

      0.010

      0.012

      D

      1.85

      2.00

      2.15

      0.073

      0.079

      0.085

      D2

      1.45

      1.60

      1.70

      0.057

      0.063

      0.067

      E

      1.85

      2.00

      2.15

      0.073

      0.079

      0.085

      E2

      0.75

      0.90

      1.00

      0.030

      0.035

      0.039

      e


      0.50



      0.020


      L

      0.225

      0.325

      0.425

      0.009

      0.013

      0.017

      ddd



      0.08



      0.003

      MiniSO8 package information



      Figure 68. DFN8 2 x 2 recommended footprint


    2. MiniSO8 package information


      Figure 69. MiniSO8 package outline


      Table 9. MiniSO8 package mechanical data



      Ref.

      Dimensions

      Millimeters

      Inches

      Min.

      Typ.

      Max.

      Min.

      Typ.

      Max.

      A



      1.1



      0.043

      A1

      0


      0.15

      0


      0.0006

      A2

      0.75

      0.85

      0.95

      0.030

      0.033

      0.037

      SO8 package information



      Ref.

      Dimensions

      Millimeters

      Inches

      Min.

      Typ.

      Max.

      Min.

      Typ.

      Max.

      b

      0.22


      0.40

      0.009


      0.016

      c

      0.08


      0.23

      0.003


      0.009

      D

      2.80

      3.00

      3.20

      0.11

      0.118

      0.126

      E

      4.65

      4.90

      5.15

      0.183

      0.193

      0.203

      E1

      2.80

      3.00

      3.10

      0.11

      0.118

      0.122

      e


      0.65



      0.026


      L

      0.40

      0.60

      0.80

      0.016

      0.024

      0.031

      L1


      0.95



      0.037


      L2


      0.25



      0.010


      k



      ccc



      0.10



      0.004


    3. SO-8 package information


      Figure 70. SO8 package outline


      Table 10. SO-8 mechanical data



      Symbol

      Milimeters

      Inches(1)

      Min.

      Typ.

      Max.

      Min.

      Typ.

      Max.

      A



      1.75



      0.069

      A1

      0.10


      0.25

      0.004


      0.010

      A2

      1.25



      0.049



      b

      0.28


      0.48

      0.011


      0.019



      Symbol

      Milimeters

      Inches(1)

      Min.

      Typ.

      Max.

      Min.

      Typ.

      Max.

      c

      0.17


      0.23

      0.007


      0.010

      D

      4.80

      4.90

      5.00

      0.189

      0.193

      0.197

      E

      5.80

      6.00

      6.20

      0.228

      0.236

      0.244

      E1

      3.80

      3.90

      4.00

      0.150

      0.154

      0.157

      e


      1.27



      0.050


      h

      0.25


      0.50

      0.010


      0.020

      L

      0.40


      1.27

      0.016


      0.050

      L1


      1.04



      0.040


      k



      ccc



      0.10



      0.004

      1. Values in inches are converted from mm and rounded to 4 decimal digits.


    4. SOT23-5 package information


      Figure 71. SOT23-5 package outline


      Table 11. SOT23-5 mechanical data



      Ref.

      Dimensions

      Millimeters

      Inches

      Min.

      Typ.

      Max.

      Min.

      Typ.

      Max.

      A

      0.90

      1.20

      1.45

      0.035

      0.047

      0.057



      Ref.

      Dimensions

      Millimeters

      Inches

      Min.

      Typ.

      Max.

      Min.

      Typ.

      Max.

      A1



      0.15



      0.006

      A2

      0.90

      1.05

      1.30

      0.035

      0.041

      0.051

      B

      0.35

      0.40

      0.50

      0.014

      0.016

      0.020

      C

      0.09

      0.15

      0.20

      0.004

      0.006

      0.008

      D

      2.80

      2.90

      3.00

      0.110

      0.114

      0.118

      D1


      1.90



      0.075


      e


      0.95



      0.037


      E

      2.60

      2.80

      3.00

      0.102

      0.110

      0.118

      F

      1.50

      1.60

      1.75

      0.059

      0.063

      0.069

      L

      0.10

      0.35

      0.60

      0.004

      0.014

      0.024

      K

      0 degrees


      10 degrees

      0 degrees


      10 degrees

      Ordering information


  1. Ordering information


Table 12. Order code


Order code

Temperature range

Package

Packing

Marking

TSZ181ILT


-40 to 125 °C

SOT23-5


Tape and reel

K215

TSZ181IQ1T

DFN6 1.2x1.3

KB

TSZ182IQ2T

DFN8 2x2


K4G

TSZ182IST

MiniSO8

TSZ182IDT

SO8

TSZ182I

TSZ181IYLT (1)


Automotive grade

-40 to 125°C

SOT23-5

K216

TSZ182IYST (1)

MiniSO8

K420

TSZ182IYDT

SO8

TSZ182IY

1. Qualified and characterized according to AEC Q100 and Q003 or equivalent, advanced screening according to AEC Q001 & Q002 or equivalent.


Revision history



Table 13. Document revision history


Date

Revision

Changes

21-Nov-2016

1

Initial release

13-Jul-2017

2

Added SO-8 package information and updated automotive qualification status in Table 10 "Order codes".

06-Nov-2017

3

Added: new packages DFN6 1.2x1.3 and SOT23-5. Updated: Table 10 "Order codes".

14-Mar-2018

4

Updated footnote Table 12. Order code.

27-Aug-2018

5

Updated Figure 1. Pin connections for each package (top view).


Contents

  1. Package pin connections 2

  2. Absolute maximum ratings and operating conditions 3

  3. Electrical characteristics 4

  4. Electrical characteristic curves 9

  5. Application information 17

    1. Operation theory 17

      1. Time domain 17

      2. Frequency domain 18

    2. Operating voltages 18

    3. Input pin voltage ranges 18

    4. Rail-to-rail input/output 19

    5. Input offset voltage drift over temperature 19

    6. Capacitive load 19

    7. PCB layout recommendations 21

    8. Optimized application recommendation 21

    9. EMI rejection ration (EMIRR) 21

    10. 1/f noise 22

    11. Overload recovery 23

    12. Phase reversal protection 23

    13. Open loop gain close to the rail 24

    14. Application examples 24

      1. Measuring gas concentration using the NDIR principle (thermopile) 24

      2. Precision instrumentation amplifier 25

      3. Low-side current sensing 26

  6. Package information 28

    1. DFN6 1.2x1.3 package information 28

    2. DFN8 2 x 2 package information 30

    3. MiniSO8 package information 32

    4. SO-8 package information 33

    5. SOT23-5 package information 34

  7. Ordering information 36

Revision history 37

List of tables


List of tables

Table 1. Absolute maximum ratings (AMR) 3

Table 2. Operating conditions 3

Table 3. Electrical characteristics at V CC+ = 2.2 V with V CC- = 0 V, Vicm = V CC/2, T = 25 °C, and RL = 10 kΩ connected to V

CC/2 (unless otherwise specified) 4

Table 4. Electrical characteristics at VCC+ = 3.3 V with VCC- = 0 V, Vicm = VCC/2, T = 25 °C, and RL = 10 kΩ connected to VCC/2 (unless otherwise specified) 5

Table 5. Electrical characteristics at VCC+ = 5 V with VCC- = 0 V, Vicm = VCC/2, T = 25 °C, and RL = 10 kΩ connected to VCC/2 (unless otherwise specified) 6

Table 6. Riso impact on stability 21

Table 7. DFN6 1.2 x 1.3 mechanical data 30

Table 8. DFN8 2 x 2 mechanical data 31

Table 9. MiniSO8 package mechanical data 32

Table 10. SO-8 mechanical data 33

Table 11. SOT23-5 mechanical data 34

Table 12. Order code 36

Table 13. Document revision history 37


List of figures

Figure 1. Pin connections for each package (top view) 2

Figure 2. Supply current vs. supply voltage 9

Figure 3. Input offset voltage distribution at VCC = 5 V 9

Figure 4. Input offset voltage distribution at VCC = 3.3 V 9

Figure 5. Input offset voltage distribution at VCC = 2.2 V 9

Figure 6. Input offset voltage distribution at VCC = 5 V, T = 125 °C 9

Figure 7. Input offset voltage distribution at VCC = 5 V, T = -40 °C 9

Figure 8. Input offset voltage distribution at VCC = 2.2 V, T = 125 °C 10

Figure 9. Input offset voltage distribution at VCC = 2.2 V, T = -40 °C 10

Figure 10. Input offset voltage vs. supply voltage 10

Figure 11. Input offset voltage vs. input common-mode at VCC = 5.5 V 10

Figure 12. Input offset voltage vs. input common-mode at VCC = 3.3 V 10

Figure 13. Input offset voltage vs. input common-mode at VCC = 2.2 V 10

Figure 14. Input offset voltage vs. temperature 11

Figure 15. VOH vs. supply voltage 11

Figure 16. VOL vs. supply voltage 11

Figure 17. Output current vs. output voltage at VCC = 5.5 V 11

Figure 18. Output current vs. output voltage at VCC = 2.2 V 11

Figure 19. Input bias current vs. common-mode at VCC = 5 V 11

Figure 20. Input bias current vs. temperature at VCC = 5 V 12

Figure 21. Output rail linearity 12

Figure 22. Bode diagram at VCC = 5.5 V 12

Figure 23. Bode diagram at VCC = 2.2 V 12

Figure 24. Bode diagram at VCC = 3.3 V 12

Figure 25. Open loop gain vs. frequency 12

Figure 26. Positive slew rate vs. supply voltage 13

Figure 27. Negative slew rate vs. supply voltage 13

Figure 28. Noise 0.1 - 10 Hz vs. time 13

Figure 29. Noise vs. frequency 13

Figure 30. Noise vs. frequency and temperature 13

Figure 31. Output overshoot vs. load capacitance 13

Figure 32. Small signal VCC = 5 V 14

Figure 33. Small signal VCC = 2.2 V 14

Figure 34. Large signal VCC = 5 V 14

Figure 35. Large signal VCC = 2.2 V 14

Figure 36. Negative overvoltage recovery VCC = 2.2 V 14

Figure 37. Positive overvoltage recovery VCC = 2.2 V 14

Figure 38. Output impedance vs. frequency 15

Figure 39. Settling time positive step (-2 V to 0 V) 15

Figure 40. Settling time negative step (2 V to 0 V) 15

Figure 41. Settling time positive step (-0.8 V to 0 V) 15

Figure 42. Settling time negative step (0.8 V to 0 V) 15

Figure 43. Maximum output voltage vs. frequency 15

Figure 44. Crosstalk vs. frequency 16

Figure 45. PSRR vs. frequency 16

Figure 46. Block diagram in the time domain (step 1) 17

Figure 47. Block diagram in the time domain (step 2) 17

Figure 48. Vio cancellation principle 18

Figure 49. Block diagram in the frequency domain 18

Figure 50. Input current limitation 19

Figure 51. Stability criteria with a serial resistor at VCC = 5 V 20

Figure 52. Stability criteria with a serial resistor at VCC = 3.3 V 20

Figure 53. Stability criteria with a serial resistor at VCC = 2.2 V 20

Figure 54. Test configuration for Riso 21

Figure 55. EMIRR on IN+ pin 22

Figure 56. EMIRR on IN- pin 22

Figure 57. Noise vs frequency between 0.1 and 10 Hz exhibiting no 1/f noise 23

Figure 58. Negative overvoltage recovery VCC = 5 V 23

Figure 59. Positive overvoltage recovery VCC = 5 V 23

Figure 60. No phase reversal 24

Figure 61. Gain vs. output voltage, VCC = 5 V, RI = 10 kΩ to GND 24

Figure 62. Principle schematic 25

Figure 63. Precision instrumentation amplifier schematic 26

Figure 64. Low-side current sensing schematic 26

Figure 65. DFN6 1.2 x 1.3 package outline 29

Figure 66. DFN6 1.2 x 1.3 recommended footprint 30

Figure 67. DFN8 2 x 2 package outline 31

Figure 68. DFN8 2 x 2 recommended footprint 32

Figure 69. MiniSO8 package outline 32

Figure 70. SO8 package outline 33

Figure 71. SOT23-5 package outline 34


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