The MAX4230–MAX4234 single/dual/quad, high-output drive CMOS op amps feature 200mA of peak output cur- rent, rail-to-rail input, and output capability from a single 2.7V to 5.5V supply. These amplifiers exhibit a high slew rate of 10V/μs and a gain-bandwidth product (GBWP) of 10MHz. The MAX4230–MAX4234 can drive typical headset levels (32Ω), as well as bias an RF power amplifier (PA) in wireless handset applications.
The MAX4230 comes in a tiny 5-pin SC70 package and the MAX4231, single with shutdown, is offered in a 6-pin SC70 package and in 1.5mm x 1.0mm UCSP and thin μDFN packages. The dual op-amp MAX4233 is offered in the space-saving 10-bump chip-scale package (UCSP™), providing the smallest footprint area for a dual op amp with shutdown.
These op amps are designed to be part of the PA control circuitry, biasing RF PAs in wireless headsets. The MAX4231/ MAX4233 offer a SHDN feature that drives the output low. This ensures that the RF PA is fully disabled when needed, preventing unconverted signals to the RF antenna.
RF PA Biasing Controls in Handset Applications
Portable/Battery-Powered Audio Applications
Portable Headphone Speaker Drivers (32Ω)
Audio Hands-Free Car Phones (Kits)
Tablet/Notebook Computers
Digital-to-Analog Converter Buffers
Transformer/Line Drivers
Motor Drivers
Selector Guide appears at end of data sheet. Pin/Bump Configurations appear at end of data sheet.
Visit www.maximintegrated.com/products/patents for product patent marking information.
UCSP is a trademark of Maxim Integrated Products, Inc.
19-2164; Rev 21; 2/18
Optimized for Headsets and High-Current Outputs
200mA Output Drive Capability
100dB Voltage Gain (RL = 100kΩ)
85dB Power-Supply Rejection Ratio
No Phase Reversal for Overdriven Inputs
Unity-Gain Stable for Capacitive Loads to 780pF
Suitable for High-Bandwidth Applications
10MHz Gain-Bandwidth Product
High Slew Rate: 10V/μs
Extends the Battery Life of Portable Applications
1.1mA Supply Current per Amplifier
Low-Power Shutdown Mode Reduces Supply Current to < 1μA
Small Package Options
Tiny, 2.1mm x 2.0mm Space-Saving SC70 Package
AEC-Q100 Qualified, Refer to Ordering Information for the List of /V Parts
PART | TEMP RANGE | PIN- PACKAGE | TOP MARK |
MAX4230AXK+T | -40°C to +125°C | 5 SC70 | ACS |
MAX4230AXK/V+T | -40°C to +125°C | 5 SC70 | +AUU |
MAX4230AUK+T | -40°C to +125°C | 5 SOT23 | ABZZ |
MAX4231AXT+T | -40°C to +125°C | 6 SC70 | ABA |
MAX4231AUT+T | -40°C to +125°C | 6 SOT23 | ABNF |
MAX4231ART+T | -40°C to +125°C | 6 UCSP | AAM |
MAX4231AYT+T | -40°C to +125°C | 6 Thin µDFN (Ultra-Thin LGA) | +AH |
+Denotes a lead(Pb)-free/RoHS-compliant package. T = Tape and reel.
Ordering Information continued at end of data sheet.
ANTENNA 2.7V TO 5.5V PA DAC MAX4231 ILOAD = 30mA RISO CLOAD SHDN C R RF |
Supply Voltage (VDD to VSS) ................................................6V
All Other Pins ...................................(VSS - 0.3V) to (VDD + 0.3V)
Output Short-Circuit Duration to VDD or VSS (Note 1) ...............10s Continuous Power Dissipation (Multilayer, TA = +70°C) 5-Pin SC70 (derate 3.1mW/°C above +70°C) ..............247mW
5-Pin SOT23 (derate 3.9mW/°C above +70°C)............313mW
6-Pin SC70 (derate 3.1mW/°C above +70°C) ..............245mW
6-Pin SOT23 (derate 13.4mW/°C above +70°C)........1072mW 6-Pin Thin µDFN (derate 2.1mW/°C above +70°C)...170.2mW 6-Bump UCSP (derate 3.9mW/°C above +70°C) .....308.3mW 8-Pin SOT23 (derate 5.1mW/°C above +70°C).........408.2mW
μMAX is a registered trademark of Maxim Integrated Products, Inc.
Note 1: Package power dissipation should also be observed.
8-Pin µMAX® (derate 4.8mW/°C above +70°C) .......387.8mW 10-Pin µMAX (derate 8.8mW/°C above +70°C) .......707.3mW 10-Bump UCSP (derate 5.6mW/°C above +70°C) .....448.7mW 14-Pin SO (derate 11.9mW/°C above +70°C) ..........952.4mW 14-Pin TSSOP (derate 10mW/°C above +70°C) ......796.8mW Operating Temperature Range .........................-40°C to +125°C Junction Temperature ......................................................+150°C
Storage Temperature Range .............................-65°C to +150°C
Lead Temperature
(excluding 6 and 10 UCSP, soldering, 10s) ................+300°C Soldering Temperature (reflow) .......................................+260°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
(VDD = 2.7V, VSS = 0V, VCM = VDD/2, VOUT = (VDD/2), RL = ∞ connected to (VDD/2), VSHDN = VDD, TA = +25°C, unless otherwise
noted.) (Note 2)
PARAMETER | SYMBOL | CONDITIONS | MIN | TYP | MAX | UNITS | |
Operating Supply Voltage Range | VDD | Inferred from PSRR test | 2.7 | 5.5 | V | ||
Input Offset Voltage | VOS | 0.85 ±6 | mV | ||||
Input Bias Current (Note 4) | IB | VCM = VSS to VDD | 1 | pA | |||
Input Offset Current | IOS | VCM = VSS to VDD | 50 | pA | |||
Input Resistance | RIN | 1000 | MΩ | ||||
Common-Mode Input Voltage Range | VCM | Inferred from CMRR test | VSS | VDD | V | ||
Common-Mode Rejection Ratio | CMRR | VSS < VCM < VDD | 52 | 70 | dB | ||
Power-Supply Rejection Ratio | PSRR | VDD = 2.7V to 5.5V | 73 | 85 | dB | ||
Shutdown Output Impedance | ROUT | VSHDN = 0V (Note 3) | 10 | Ω | |||
Output Voltage in Shutdown | VOUT(SHDN) | VSHDN = 0V, RL = 200Ω (Note 3) | 68 | mV | |||
Large-Signal Voltage Gain | AVOL | VSS + 0.20V < VOUT < VDD - 0.20V | RL = 100kΩ | 100 | dB | ||
RL = 2kΩ | 85 | 98 | |||||
RL = 200Ω | 74 | 80 | |||||
Output Voltage Swing | VOUT | RL = 32Ω | VDD - VOH | 400 | 500 | mV | |
VOL - VSS | 360 | 500 | |||||
RL = 200Ω | VDD - VOH | 80 | 120 | ||||
VOL - VSS | 70 | 120 | |||||
RL = 2kΩ | VDD - VOH | 8 | 14 | ||||
VOL - VSS | 7 | 14 |
(VDD = 2.7V, VSS = 0V, VCM = VDD/2, VOUT = (VDD/2), RL = ∞ connected to (VDD/2), VSHDN = VDD, TA = +25°C, unless otherwise
noted.) (Note 2)
PARAMETER | SYMBOL | CONDITIONS | MIN TYP | MAX | UNITS | ||
Output Source/Sink Current | IOUT | VDD = 2.7V, VIN = ±100mV | 70 | mA | |||
VDD = 5V, VIN = ±100mV | 200 | ||||||
Output Voltage | IL = 10mA | VDD = 2.7V | VDD - VOH | 128 | 200 | mV | |
VOL - VSS | 112 | 175 | |||||
IL = 30mA | VDD = 5V | VDD - VOH | 240 | 320 | |||
VOL - VSS | 224 | 300 | |||||
Quiescent Supply Current (per Amplifier) | IDD | VDD = 5.5V, VCM = VDD/2 | 1.2 | 2.3 | mA | ||
VDD = 2.7V, VCM = VDD/2 | 1.1 | 2.0 | |||||
Shutdown Supply Current (per Amplifier) (Note 3) | IDD(SHDN) | VSHDN = 0V, RL = ∞ | VDD = 5.5V | 0.5 1 | µA | ||
VDD = 2.7V | 0.1 1 | ||||||
SHDN Logic Threshold (Note 3) | VIL | Shutdown mode | 0.8 | V | |||
VIH | Normal mode | VDD x 0.57 | |||||
SHDN Input Bias Current | VSS < VSHDN < VDD (Note 3) | 50 | pA |
(VDD = 2.7V, VSS = 0V, VCM = VDD/2, VOUT = (VDD/2), RL = ∞ connected to (VDD/2), VSHDN = VDD, TA = -40 to +125°C, unless other
wise noted.) (Note 2)
PARAMETER | SYMBOL | CONDITIONS | MIN TYP MAX | UNITS | |
Operating Supply Voltage Range | VDD | Inferred from PSRR test | 2.7 5.5 | V | |
Input Offset Voltage | VOS | ±8 | mV | ||
Offset-Voltage Tempco | ∆VOS/∆T | ±3 | µV/°C | ||
Input Bias Current (Note 4) | IB | TA = -40°C to +85°C | 17 550 | pA | |
TA = -40°C to +125°C | |||||
Common-Mode Input Voltage Range | VCM | Inferred from CMRR test | VSS VDD | V | |
Common-Mode Rejection Ratio | CMRR | VSS < VCM < VDD | 46 | dB | |
Power-Supply Rejection Ratio | PSRR | VDD = 2.7V to 5.5V | 70 | dB | |
Output Voltage in Shutdown | VOUT(SHDN) | VSHDN = 0V, RL = 200Ω (Note 3) | 150 | mV | |
Large-Signal Voltage Gain | AVOL | VSS + 0.20V < VDD - 0.20V | RL = 2kΩ | 76 | dB |
RL = 200Ω | 67 | ||||
Output Voltage Swing | VOUT | RL = 32Ω TA = +85°C | VDD - VOH | 650 | mV |
VOL - VSS | 650 | ||||
RL = 200Ω | VDD - VOH | 150 | |||
VOL - VSS | 150 | ||||
RL = 2kΩ | VDD - VOH | 20 | |||
VOL - VSS | 20 |
(VDD = 2.7V, VSS = 0V, VCM = VDD/2, VOUT = (VDD/2), RL = ∞ connected to (VDD/2), VSHDN = VDD, TA = -40 to +125°C, unless other
wise noted.) (Note 2)
PARAMETER | SYMBOL | CONDITIONS | MIN TYP MAX | UNITS | ||
Output Voltage | IL = 10mA | VDD = 2.7V | VDD - VOH | 250 | mV | |
VOL - VSS | 230 | |||||
IL = 30mA TA = -40°C to +85° | VDD = 5V | VDD - VOH | 400 | |||
VOL - VSS | 370 | |||||
Quiescent Supply Current (per Amplifier) | IDD | VDD = 5.5V, VCM = VDD/2 | 2.8 | mA | ||
VDD = 2.7V, VCM = VDD/2 | 2.5 | |||||
Shutdown Supply Current (per Amplifier) (Note 3) | IDD(SHDN) | VSHDN < 0V, RL = ∞ | VDD = 5.5V | 2.0 | µA | |
VDD = 2.7V | 2.0 | |||||
SHDN Logic Threshold (Note 3) | VIL | Shutdown mode | 0.8 | V | ||
VIH | Normal mode | VDD x 0.61 |
(VDD = 2.7V, VSS = 0V, VCM = VDD/2, VOUT = (VDD/2), RL = ∞ connected to (VDD/2), VSHDN = VDD, TA = +125°C, unless otherwise
noted.) (Note 2)
PARAMETER | SYMBOL | CONDITIONS | MIN TYP MAX | UNITS |
Gain-Bandwidth Product | GBWP | VCM = VDD/2 | 10 | MHz |
Full-Power Bandwidth | FPBW | VOUT = 2VP-P, VDD = 5V | 0.8 | MHz |
Slew Rate | SR | 10 | V/μs | |
Phase Margin | PM | 70 | Degrees | |
Gain Margin | GM | 15 | dB | |
Total Harmonic Distortion Plus Noise | THD+N | f = 10kHz, VOUT = 2VP-P, AVCL = 1V/V | 0.0005 | % |
Input Capacitance | CIN | 8 | pF | |
Voltage-Noise Density | en | f = 1kHz | 15 | nV/√Hz |
f = 10kHz | 12 | |||
Channel-to-Channel Isolation | f = 1kHz, RL = 100kΩ | 125 | dB | |
Capacitive-Load Stability | AVCL = 1V/V, no sustained oscillations | 780 | pF | |
Shutdown Time | tSHDN | (Note 3) | 1 | µs |
Enable Time from Shutdown | tENABLE | (Note 3) | 6 | µs |
Power-Up Time | tON | 5 | µs |
Note 2: All units 100% tested at +25°C. All temperature limits are guaranteed by design.
Note 3: SHDN logic parameters are for the MAX4231/MAX4233 only.
Note 4: Guaranteed by design.
(VDD = 2.7V, VSS = 0V, VCM = VDD/2, VOUT = VDD/2, RL = ∞, connected to VDD/2, VSHDN = VDD, TA = +25°C, unless otherwise noted.)
70
60
50
40
GAIN (dB)
30
20
10
0
-10
-20
-30
GAIN AND PHASE vs. FREQUENCY
PHASE (°)
MAX4230 toc01
AV = 1000V/V | |||||||||||||
120
90
60
30
0
-30
-60
-90
-120
-150
-180
70
60
50
40
GAIN (dB)
30
20
10
0
-10
-20
-30
GAIN AND PHASE vs. FREQUENCY (CL = 250pF)
MAX4230 toc02
AV = 1000V/V CL = 250pF
120
90
60
30
PHASE (°)
0
-30
-60
-90
-120
-150
-180
0.01k
0.1k 1k
10k 100k 1M 10M FREQUENCY (Hz)
100M
0.01k
0.1k 1k
10k 100k 1M 10M FREQUENCY (Hz)
100M
0
-10
-20
-30
PSRR (dB)
-40
-50
-60
-70
-80
-90
-100
POWER-SUPPLY REJECTION RATIO vs. FREQUENCY
MAX4230 toc03
AV = 1V/V
1000
OUTPUT IMPEDANCE (Ω)
100
10
1
0.1
0.01
OUTPUT IMPEDANCE vs. FREQUENCY
MAX4230 toc04
AV = 1V/V
0.01k
0.1k 1k
10k 100k 1M
10M
1k 10k
100k 1M
10M
2.0
1.8
SUPPLY CURRENT (mA)
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
FREQUENCY (Hz)
MAX4230 toc05
SUPPLY CURRENT vs. TEMPERATURE
110
SUPPLY CURRENT (nA)
100
90
80
70
60
FREQUENCY (Hz)
MAX4230 toc06
SUPPLY CURRENT vs. TEMPERATURE (SHDN = LOW)
SHDN = VSS
0
-40
-20
0 20 40 60 80 100 120
50
-40
-20 0
20 40 60 80 100 120
TEMPERATURE (°C)
TEMPERATURE (C)
(VDD = 2.7V, VSS = 0V, VCM = VDD/2, VOUT = VDD/2, RL = ∞, connected to VDD/2, VSHDN = VDD, TA = +25°C, unless otherwise noted.)
2.0
1.8
SUPPLY CURRENT (mA)
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
SUPPLY CURRENT PER AMPLIFIER vs. SUPPLY VOLTAGE
INPUT OFFSET VOLTAGE vs. TEMPERATURE
MAX4230 toc07
2
VDD = 2.7V
1
VOS (mV)
0 VDD = 5.0V
-1
-2
100
MAX4230 toc08
VDD - VOUT (mV)
80
60
40
20
0
OUTPUT SWING HIGH vs. TEMPERATURE
MAX4230/34 toc09
VDD = 5.0V RL = 200Ω
VDD = 2.7V RL = 200Ω
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
SUPPLY VOLTAGE (V)
-40
-20
0 20 40 60 80 100 120
TEMPERATURE (°C)
-40
-20
0 20 40 60 80 100 120
TEMPERATURE (°C)
140
120
VOUT - VSS (mV)
100
80
60
40
20
OUTPUT SWING LOW vs. TEMPERATURE
VDD = 5.0V RL = 200Ω
VDD = 2.7V RL = 200Ω
1.0
MAX4230/3 toc10
INPUT OFFSET VOLTAGE (mV)
0.5
0
-0.5
-1.0
-1.5
INPUT OFFSET VOLTAGE vs. COMMON-MODE VOLTAGE
MAX4230/3 toc11
1.2
SUPPLY CURRENT (mA)
1.0
0.8
0.6
0.4
SUPPLY CURRENT PER AMPLIFIER vs. COMMON-MODE VOLTAGE
0
-40
-20
0 20
40 60 80 100 120
MAX4230/3 toc12
-2.0
0 0.5 1.0 1.5 2.0 2.5
0.2
VDD = 2.7V |
0 0.5 1.0 1.5 2.0 2.5
1.4
TEMPERATURE (°C)
SUPPLY CURRENT PER AMPLIFIER vs. COMMON-MODE VOLTAGE
MAX4230/34 toc13
VDD = 5.0V | |||||||||
0.45
COMMON-MODE VOLTAGE (V)
TOTAL HARMONIC DISTORTION PLUS NOISE vs. FREQUENCY
VOUT = 2VP-P
COMMON-MODE VOLTAGE (V)
TOTAL HARMONIC DISTORTION PLUS NOISE vs. PEAK-TO-PEAK OUTPUT VOLTAGE
MAX4230/34 toc14
MAX4230/34 toc15
10
f = 10kHz
SUPPLY CURRENT (mA)
1.2
1.0
0.8
0.6
0.4
0.2
0.40
0.35
THD+N (%)
0.30
0.25
0.20
0.15
0.10
0.05
0
500kHz LOWPASS FILTER
RL = 32
RL = 10k
1
THD+N (%)
0.1
0.001
0.0001
VDD = 5V
RL = 25
RL = 2k RL = 250
RL = 100k
0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
10 100 1k 10k 100k
4.0 4.2
4.4
4.6
4.8
5.0
COMMON-MODE VOLTAGE (V)
FREQUENCY (Hz)
PEAK-TO-PEAK OUTPUT VOLTAGE (V)
(VDD = 2.7V, VSS = 0V, VCM = VDD/2, VOUT = VDD/2, RL = ∞, connected to VDD/2, VSHDN = VDD, TA = +25°C, unless otherwise noted.)
SMALL-SIGNAL TRANSIENT RESPONSE (NONINVERTING)
MAX4230/34 toc16
SMALL-SIGNAL TRANSIENT RESPONSE (INVERTING)
MAX4230/34 toc17
LARGE-SIGNAL TRANSIENT RESPONSE (NONINVERTING)
MAX4230/34 toc18
IN
50mV/div
OUT
IN
50mV/div
OUT
IN
1V/div OUT
MAX4230/34 toc21
400ns/div
400ns/div
400ns/div
IN
1V/div
OUT
LARGE-SIGNAL TRANSIENT RESPONSE (INVERTING)
MAX4230/34 toc19
OUTPUT CURRENT vs. OUTPUT VOLTAGE (SOURCING, VDD = 2.7V)
MAX4230/34 toc20
VDIFF = 100mV | |||||||||
80
70
OUTPUT CURRENT (mA)
60
50
40
30
20
10
0
0
-10
OUTPUT CURRENT (mA)
-20
-30
-40
-50
-60
-70
-80
OUTPUT CURRENT vs. OUTPUT VOLTAGE (SINKING, VDD = 2.7V)
VDIFF = 100mV | |||||||
400ns/div
1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0
0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6
250
OUTPUT CURRENT (mA)
200
150
100
50
OUTPUT CURRENT vs. OUTPUT VOLTAGE (SOURCING, VDD = 5.0V)
MAX4230/34 toc22
0
OUTPUT CURRENT (mA)
-50
-100
-150
-200
OUTPUT VOLTAGE (V)
OUTPUT CURRENT vs. OUTPUT VOLTAGE (SINKING, VDD = 5.0V)
MAX4230/34 toc23
200
INPUT VOLTAGE NOISE (nV/√Hz)
100
OUTPUT VOLTAGE (V)
MAX4230/34 toc24
INPUT VOLTAGE NOISE vs. FREQUENCY
VDIFF = 100mV | |||||
0
2.0
2.5
3.0
3.5 4.0 4.5 5.0
-250
VDIFF = 100mV | |||||
0
0.5
1.0
1.5 2.0 2.5 3.0
10
100 1k
10k 100k
OUTPUT VOLTAGE (V)
OUTPUT VOLTAGE (V)
FREQUENCY (Hz)
PIN | BUMP | NAME | FUNCTION | |||||
MAX4230 SOT23/ SC70 | MAX4231 SOT23/ SC70/Thin µDFN | MAX4232 SOT23/ µMAX | MAX4233 µMAX | MAX4234 TSSOP/SO | MAX4231 UCSP | MAX4233 UCSP | ||
1 | 1 | — | — | — | B1 | — | IN+ | Noninverting Input |
2 | 2 | 4 | 4 | 11 | A1 | B4 | VSS | Negative Supply Input. Connect to ground for single- supply operation. |
3 | 3 | — | — | — | B2 | — | IN- | Inverting Input |
4 | 4 | — | — | — | A2 | — | OUT | Amplifier Output |
5 | 6 | 8 | 10 | 4 | A3 | B1 | VDD | Positive Supply Input |
— | 5 | — | 5, 6 | — | B3 | C4, A4 | SHDN, SHDN1, SHDN2 | Shutdown Control. Tie to high for normal operation. |
— | — | 3 | 3 | 3 | — | C3 | IN1+ | Noninverting Input to Amplifier 1 |
— | — | 2 | 2 | 2 | — | C2 | IN1- | Inverting Input to Amplifier 1 |
— | — | 1 | 1 | 1 | — | C1 | OUT1 | Amplifier 1 Output |
— | — | 5 | 7 | 5 | — | A3 | IN2+ | Noninverting Input to Amplifier 2 |
— | — | 6 | 8 | 6 | — | A2 | IN2- | Inverting Input to Amplifier 2 |
— | — | 7 | 9 | 7 | — | A1 | OUT2 | Amplifier 2 Output |
— | — | — | — | 10, 12 | — | — | IN3+, N4+ | Noninverting Input to Amplifiers 3 |
— | — | — | — | 9, 13 | — | — | IN3-, IN4- | Inverting Input to Amplifiers 3 and |
— | — | — | — | 8, 14 | — | — | OUT3, OUT4 | Amplifiers 3 and 4 Outputs |
The MAX4230–MAX4234 CMOS operational amplifiers have parallel-connected n- and p-channel differential input stages that combine to accept a common-mode range extending to both supply rails. The n-channel stage is active for common-mode input voltages typically greater than (VSS + 1.2V), and the p-channel stage is active for common-mode input voltages typically less than (VDD - 1.2V).
Warning: Due to the high output current drive, this op amp can exceed the absolute maximum power- dissipation rating. As a general rule, as long as the peak current is less than or equal to 40mA, the maximum
package power dissipation is not exceeded for any of the package types offered. There are some exceptions to this rule, however. The absolute maximum power-dissipation rating of each package should always be verified using the following equations. The equation below gives an approximation of the package power dissipation:
PIC(DISS) VRMS IRMS COS
where:
VRMS = RMS voltage from VDD to VOUT when sourcing current and RMS voltage from VOUT to VSS when sinking current.
IRMS = RMS current flowing out of or into the op amp and
the load.
θ = phase difference between the voltage and the current. For resistive loads, COS θ = 1.
R C MAX4230 VIN = 2VP-P MAX4231 R 32Ω
|
RF LEFT CIN RIN AUDIO INPUT COUT HEADPHONE JACK TO 32Ω STEREO HEADSET VBIAS MAX4230 COUT CIN RIN RIGHT AUDIO INPUT RF |
Figure 1. MAX4230/MAX4231 Used in Single-Supply Operation
Circuit Example
Figure 2. Circuit Example: Adding a Coupling Capacitor Greatly
Reduces Power Dissipation of its Package
For example, the circuit in Figure 1 has a package power
dissipation of 196mW:
VRMS
VPEAK
2
RMS (VDD VDC ) VPEAK
2
3.6V 1.8V 1.0V 2.507VRMS
2
IRMS IDC IPEAK 1.8V 1.0V / 32
1.0V 0.707VRMS 2
IRMS IDC IPEAK 0A 1.0V / 32
2 2
22.1mA RMS
where:
2 32 2
78.4mARMS
Therefore:
PIC(DISS) = VRMS IRMS COS
VDC = the DC component of the output voltage. IDC = the DC component of the output current.
VPEAK = the highest positive excursion of the AC compo- nent of the output voltage.
IPEAK = the highest positive excursion of the AC compo- nent of the output current.
Therefore:
PIC(DISS) = VRMS IRMS COS
= 196mW
= 15.6mW
If the configuration in Figure 1 were used with all four of the MAX4234 amplifiers, the absolute maximum power dissipation rating of this package would be exceeded (see the Absolute Maximum Ratings section).
Two MAX4230/MAX4231s can be used as a single-supply, stereo headphone driver. The circuit shown in Figure 2 can deliver 60mW per channel with 1% distortion from a single 5V supply.
The input capacitor (CIN), in conjunction with RIN, forms a highpass filter that removes the DC bias from the incom- ing signal. The -3dB point of the highpass filter is given by
f3dB
1
2RINCIN
C1 R1 R2 0.1mF 16kΩ 82kΩ 0.5VP-P 32W 3V 3V 1/2 fS = 100Hz 2 8 MAX4232 1 R5 3 4 51kΩ R3 R4 10kΩ 10kΩ C2 R6 6 0.1µF 51kΩ 7 5 1/2 MAX4232 |
VCC = 3.0V RL = 100kΩ IN 1V/div OUT 1V/div 5s/div |
Figure 3. Dual MAX4230/MAX4231 Bridge Amplifier for 200mW at 3V
Figure 4. Rail-to-Rail Input/Output Range
Choose gain-setting resistors RIN and RF according to the amount of desired gain, keeping in mind the maximum output amplitude. The output coupling capacitor, COUT, blocks the DC component of the amplifier output, prevent- ing DC current flowing to the load. The output capacitor and the load impedance form a highpass filer with the
-3dB point determined by:
f3dB 1
2RINCOUT
For a 32Ω load, a 100μF aluminum electrolytic capacitor
gives a low-frequency pole at 50Hz.
The circuit shown in Figure 3 uses a dual MAX4230 to implement a 3V, 200mW amplifier suitable for use in size- constrained applications. This configuration eliminates the need for the large coupling capacitor required by the single op-amp speaker driver when single-supply opera- tion is necessary. Voltage gain is set to 10V/V; however, it can be changed by adjusting the 82kΩ resistor value.
The MAX4230–MAX4234 CMOS op amps have parallel connected n- and p-channel differential input stages that combine to accept a common-mode range extending to both supply rails. The n-channel stage is active for common-mode input voltages typically greater than (VSS
+ 1.2V), and the p-channel stage is active for common-
mode input voltages typically less than (VDD -1.2V).
The minimum output is within millivolts of ground for single-supply operation, where the load is referenced to ground (VSS). Figure 4 shows the input voltage range and the output voltage swing of a MAX4230 connected as a voltage follower. The maximum output voltage swing is load dependent; however, it is guaranteed to be within 500mV of the positive rail (VDD = 2.7V) even with maxi- mum load (32Ω to ground).
Observe the Absolute Maximum Ratings for power dis- sipation and output short-circuit duration (10s, max) because the output current can exceed 200mA (see the Typical Operating Characteristics.)
One consequence of the parallel-connected differential input stages for rail-to-rail operation is a relatively large input capacitance CIN (5pF typ). This introduces a pole at frequency (2πR′CIN)-1, where R′ is the parallel com- bination of the gain-setting resistors for the inverting or noninverting amplifier configuration (Figure 5). If the pole frequency is less than or comparable to the unity-gain bandwidth (10MHz), the phase margin is reduced, and the amplifier exhibits degraded AC performance through either ringing in the step response or sustained oscilla- tions. The pole frequency is 10MHz when R′ = 2kΩ. To maximize stability, R′ << 2kΩ is recommended.
2000 UNSTABLE 1500 STABLE 1000 500 VDD = 5.0V RL TO VDD/2 0 1 10 100 1k 10k 100k RESISTIVE LOAD (Ω) |
CAPACITIVE LOAD (pF)
INVERTING Cf Rf VIN R MAX4230 VOUT R’ = R || Rf RfCf = RCIN NONINVERTING VIN MAX4230 VOUT Rf Cf R R’ = R || Rf RfCf = RCIN |
20mV/div 20mV/div VDD = 3.0V, CL = 1500pF RL = 100kΩ, RISO = 0Ω 1µ/div |
Figure 6. Capacitive-Load Stability
Figure 5. Inverting and Noninverting Amplifiers with Feedback
Compensation
To improve step response when R′ > 2kΩ, connect small capacitor Cf between the inverting input and output. Choose Cf as follows:
Cf = 8(R/Rf) [pf]
where Rf is the feedback resistor and R is the gain-setting resistor (Figure 5).
The MAX4230–MAX4234 have a high tolerance for capacitive loads. They are stable with capacitive loads up to 780pF. Figure 6 is a graph of the stable operating region for various capacitive loads vs. resistive loads.Figures 7 and 8 show the transient response with excessive capaci- tive loads (1500pF), with and without the addition of an isolation resistor in series with the output. Figure 9 shows a typical noninverting capacitive-load-driving circuit in the unity-gain configuration.
Figure 7. Small-Signal Transient Response with Excessive Capacitive Load
20mV/div 20mV/div VDD = 3.0V, CL = 1500pF RL = 100kΩ, RISO = 39Ω 1µ/div |
Figure 8. Small-Signal Transient Response with Excessive Capacitive Load with Isolation Resistor
RISO CL |
SHDN 2V/div IDD 1mA/div OUT 2V/div 100µs/div |
Figure 9. Capacitive-Load-Driving Circuit Figure 11. Shutdown Enable/Disable Supply Current
1V/div 4µs/div |
VDD 2V/div IDD 1mA/div 40µs/div |
Figure 10. Shutdown Output Voltage Enable/Disable Figure 12. Power-Up/Down Supply Current
The resistor improves the circuit’s phase margin by isolat- ing the load capacitor from the op amp’s output.
The MAX4231/MAX4233 have a shutdown option. When the shutdown pin (SHDN) is pulled low, supply current drops to 0.5μA per amplifier (VDD = 2.7V), the amplifiers are disabled, and their outputs are driven to VSS. Since the outputs are actively driven to VSS in shutdown, any pullup resistor on the output causes a current drain from the supply. Pulling SHDN high enables the amplifier. In the dual MAX4233, the two amplifiers shut down indepen- dently. Figure 10 shows the MAX4231’s output voltage to a shutdown pulse. The MAX4231–MAX4234 typically settle within 5μs after power-up. Figures 11 and 12 show IDD to a shutdown plus and voltage power-up cycle.
PART | AMPS PER PACKAGE | SHUTDOWN MODE |
MAX4230 | Single | — |
MAX4231 | Single | Yes |
MAX4232 | Dual | — |
MAX4233 | Dual | Yes |
MAX4234 | Quad | — |
When exiting shutdown, there is a 6μs delay before the amplifier’s output becomes active (Figure 10).
8
5
VDD
6
TOP VIEW
+
1
IN+
2
VSS
3
IN-
VDD
4
5
MAX4230
OUT
IN+
VSS
IN-
+
6
3
7
2
MAX4232
1
MAX4231
MAX4231
2
3
VDD
5
6
SHDN
4
OUT
+
SHDN
OUT
4
OUT1 IN1- IN1+ VSS
1
+
4
5
SOT23/MAX
VDD OUT2 IN2- IN2+
SOT23/SC70
+
SC70/SOT23
3
IN-
2
VSS
1
IN+
1 2 3
Thin µDFN (Ultra-Thin LGA)
1 2 3 4
+
OUT1 1
IN1- 2
IN1+ 3
MAX4233
10 VDD A
9 OUT2
8 IN2-
VSS
OUT VDD
A OUT2
IN2-
IN2+
SHDN2
OUT1 1
IN1- 2
IN1+ 3
14 OUT4
13 IN4-
12 IN4+
VSS | 4 | 7 | IN2+ | MAX4231 B VDD | MAX4233 VSS | VDD | 4 | MAX4234 | 11 VSS | |
SHDN1 | 5 | 6 | SHDN2 | IN2+ | 5 | 10 IN3+ | ||||
MAX | B IN+ IN- SHDN C OUT1 | IN1- IN1+ SHDN1 | IN2- OUT2 | 6 7 | 9 IN3- 8 OUT3 |
UCSP
UCSP
TSSOP/SO
The MAX4230–MAX4234 can operate from a single 2.7V to 5.5V supply, or from dual ±1.35V to ±2.5V supplies. or single-supply operation, bypass the power supply with a 0.1μF ceramic capacitor. For dual-supply operation, bypass each supply to ground. Good layout improves performance by decreasing the amount of stray capacitance at the op amps’ inputs and outputs. Decrease stray capacitance by placing external components close to the op amps’ pins, minimizing trace and lead lengths.
PART | TEMP RANGE | PIN- PACKAGE | TOP MARK |
MAX4232AKA+T | -40°C to +125°C | 8 SOT23 | AAKW |
MAX4232AKA/V+T | -40°C to +125°C | 8 SOT23 | AEQW |
MAX4232AUA+T | -40°C to +125°C | 8 μMAX | — |
MAX4233AUB+T | -40°C to +125°C | 10 μMAX | — |
MAX4233ABC+T | -40°C to +125°C | 10 UCSP | ABF |
MAX4234AUD | -40°C to +125°C | 14 TSSOP | — |
MAX4234AUD/V+T | -40°C to +125°C | 14 TSSOP | — |
MAX4234ASD | -40°C to +125°C | 14 SO | — |
+Denotes a lead-free(Pb)/RoHS-compliant package. T = Tape and reel.
/V denotes an automotive-qualified part.
*EP = Exposed pad.
For the latest package outline information and land patterns (footprints), go to www.maximintegrated.com/packages. Note that a “+”, “#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status.
PACKAGE TYPE | PACKAGE CODE | DOCUMENT NO. | LAND PATTERN NO. |
5 SC70 | X5+1 | ||
6 SC70 | X6SN+1 | ||
5 SOT23 | U5+1 | ||
6 SOT23 | U6SN+1 | ||
8 μMAX | U8+1 | ||
8 SOT23 | K8+5 | ||
10 μMAX | U10+2 | ||
10 UCSP | B12+4 | — | |
6 UCSP | R61A1+1 | — | |
6 Thin μDFN (Ultra-Thin LGA) | Y61A1+1 | ||
14 TSSOP | U14+1 | ||
14 SO | S14+1 |
REVISION NUMBER | REVISION DATE | DESCRIPTION | PAGES CHANGED |
7 | 7/08 | Added 6-pin μDFN package for the MAX4231 | 1, 2, 8, 13 |
8 | 10/08 | Corrected top mark for MAX4321, 6 SOT23 package; changed MAX4320 and 4321 to lead-free packages | 1 |
9 | 10/08 | Added shutdown pin limits | 3, 4 |
10 | 12/08 | Added automotive part number | 13 |
11 | 9/09 | Corrected top mark designation and pin configuration, and added UCSP package | 1, 2, 8, 13 |
12 | 1/10 | Updated Absolute Maximum Ratings section | 2 |
13 | 1/11 | Added 10 μMAX to Package Information section | 14 |
14 | 10/11 | Updated Electrical Characteristics table with specs for bias current at various temperatures | 1–4 |
15 | 3/12 | Updated thermal data in the Absolute Maximum Ratings | 2 |
16 | 6/12 | Added automotive part number for MAX4230 | 1 |
17 | 12/13 | Updated tENABLE specification in the AC Electrical Characteristics | 6 |
18 | 10/14 | Corrected µDFN references and added ultra-thin LGA reference to Ordering Information, Pin Configurations, and Package Information | 1, 13, 14 |
19 | 1/15 | Updated General Description, Applications, and Benefits and Features sections | 1 |
20 | 11/16 | Updated TOC22 in Typical Operating Characteristics section | 7 |
21 | 2/18 | Updated Benefits and Features section and Ordering Information table | 1, 13 |
Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent licenses are implied. Maxim Integrated reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and max limits) shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance.
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MAX4232AKA+T MAX4230AUK+T MAX4230AXK+T MAX4231AUT+T MAX4231AXT+T MAX4231AYT+ MAX4231AYT+T MAX4232AKA+TC2F MAX4232AUA+ MAX4232AUA+T MAX4233ABC+T MAX4233ABC+TG47 MAX4233AUB+ MAX4233AUB+T MAX4234ASD+ MAX4234ASD+T MAX4234AUD+ MAX4234AUD+T MAX4230AUK-T MAX4230AXK-T MAX4231AUT-T MAX4231AXT-T MAX4231ART+T