TSB571, TSB572


Datasheet


Low-power, 2.5 MHz, RR IO, 36 V BiCMOS operational amplifier



TSB571


SOT23-5


TSB572


SO8 MiniSO8 DFN8 (3x3 mm)

Features


Related products

TSB611

For below 100 µA solution

Description

The TSB571 and TSB572 operational amplifiers offer an extended voltage operating range from 4 V to 36 V and rail-to-rail input/output.

The TSB571 and TSB572 give a very good speed/power consumption ratio with a

2.5 MHz gain bandwidth product and a consumption of 380 µA typically only at 36 V supply voltage.

Stability and robustness of these devices make them an ideal solution for a wide voltage range of applications.


DS11248 - Rev 6 - July 2019

For further information contact your local STMicroelectronics sales office.

www.st.com


  1. Package pin connections


    Figure 1. Pin connections (top view)


    OUT VCC- IN+

    VCC+


    IN-


    SOT23-5


    Table 1. Pin description (SOT23-5)


    Pin n°

    Pin name

    Description

    1

    OUT

    Output channel

    2

    VCC-

    Negative supply voltage

    3

    IN1+

    Non-inverting input channel

    4

    IN-

    Inverting input channel

    5

    VCC+

    Positive supply voltage


    Figure 2. Pin connections for each package (top view)



    Out1


    VCC+

    Out1


    VCC+

    In1-


    Out2

    In1-


    Out2

    In1+


    In2-

    In1+


    In2-

    VCC-


    SO8

    In2+

    VCC-


    MiniSO8

    In2+





    Out1

    1


    8

    VCC+

    In1-

    2


    7

    Out2






    In1+

    3


    6

    In2-






    VCC-

    4


    5

    In2+








    DFN8 (3 x 3) (1)




    1. Exposed pad can be left floating or connected to ground.


      Table 2. Pin description (miniSO8/SO8/DFN8)


      Pin

      Pin name

      Description

      1

      OUT1

      Output channel 1

      2

      IN1-

      Inverting input channel 1

      3

      IN1+

      Non-inverting input channel 1

      4

      VCC-

      Negative supply voltage

      5

      IN2+

      Non-inverting input channel 2

      6

      IN2-

      Inverting input channel 2

      7

      OUT2

      Output channel 2

      8

      VCC+

      Positive supply voltage

      Absolute maximum ratings and operating conditions


  2. Absolute maximum ratings and operating conditions


    Table 3. Absolute maximum ratings


    Symbol

    Parameter


    Value

    Unit

    VCC

    Supply voltage (1)

    40


    V

    Vid

    Differential input voltage (2)

    ±1

    Vin

    Input voltage (3)

    (VCC -) - 0.2 to (VCC +) + 0.2

    Iin

    Input current (4)

    10

    mA

    Tstg

    Storage temperature

    -65 to 150


    °C

    Tj

    Maximum junction temperature

    150


    Rthja


    Thermal resistance junction to ambient (5) (6)

    SOT23-5

    250


    °C/W

    MiniSO8

    190

    DFN8 3x3

    40

    SO-8

    125


    ESD

    Human body model (HBM) (7)

    4

    kV

    Machine model (MM) (8)

    100

    V

    CDM: charged device model (9)

    1.5

    kV


    Latch-up immunity

    100

    mA

    1. All voltage values, except the differential voltage are with respect to network ground terminal.

    2. Differential voltages are the non-inverting input terminal with respect to the inverting input terminal.

    3. VCC-Vin must not exceed 40 V, Vin must not exceed 40 V.

    4. Input current must be limited by a resistor in-series with the inputs.

    5. Rth are typical values.

    6. Short-circuits can cause excessive heating and destructive dissipation.

    7. According to JEDEC standard JESD22-A114F.

    8. According to JEDEC standard JESD22-A115A.

    9. According to ANSI/ESD STM5.3.1.


      Table 4. Operating conditions


      Symbol

      Parameter

      Value

      Unit

      VCC

      Supply voltage

      4 to 36


      V

      Vicm

      Common mode input voltage range

      (VCC -) - 0.1 to (VCC +) + 0.1

      Toper

      Operating free-air temperature range

      -40 to 125

      °C


  3. Electrical characteristics


    Table 5. Electrical characteristics at Vcc = 4 V, Vicm = Vcc/2, Tamb = 25 °C, and RL connected to Vcc/2 (unless otherwise specified)


    Symbol

    Parameter

    Conditions

    Min.

    Typ.

    Max.

    Unit

    DC performance


    Vio


    Input offset voltage


    -1.5


    1.5


    mV

    -40 °C < T < 125 °C

    -2.1


    2.1

    ΔVio/ΔT

    Input offset voltage drift

    -40 °C < T < 125 °C


    1.5

    6

    μV/°C


    Iio


    Input offset current



    2

    15


    nA

    -40 °C < T < 125 °C



    35


    Iib


    Input bias current



    8

    30

    -40 °C < T < 125 °C



    70

    CIN

    Input capacitor



    2


    pF

    RIN

    Input impedance



    1



    CMR


    Common mode rejection ratio 20 log (ΔVicm/ΔVio)

    Vicm = (VCC-) to (VCC+) - 1.5 V, Vout = VCC/2

    90

    114



    dB

    -40 °C < T < 125 °C

    80



    Vicm = (VCC-) to (VCC+), Vout = VCC/2

    75

    97


    -40 °C < T < 125 °C

    70




    Avd


    Large signal voltage gain

    RL= 10 kΩ, Vout = 0.5 to 3.5 V

    90

    100


    -40 °C < T < 125 °C

    85




    VOH

    High level output voltage (drop voltage from (VCC+))

    RL = 10 kΩ


    19

    60


    mV

    -40 °C < T < 125 °C



    80


    VOL


    Low level output voltage

    RL = 10 kΩ


    12

    50

    -40 °C < T < 125 °C



    70


    Iout


    Isink

    Vout = VCC

    20

    38



    mA

    -40 °C < T < 125 °C

    5




    Isource

    Vout = 0 V

    10

    32


    -40 °C < T < 125 °C

    5




    ICC


    Supply current (per channel)

    No load, Vout = VCC/2


    340

    430

    μA

    -40 °C < T < 125 °C



    500


    AC performance


    GBP


    Gain bandwidth product

    RL = 10 kΩ, CL = 100 pF

    1.5

    2.2



    MHz

    -40 °C < T < 125 °C

    1.2



    ϕm

    Phase margin

    RL = 10 kΩ, CL = 100 pF


    45


    degrees

    Gm

    Gain margin

    RL = 10 kΩ, CL = 100 pF


    5


    dB


    Symbol

    Parameter

    Conditions

    Min.

    Typ.

    Max.

    Unit


    SR


    Negative slew rate

    Vin = 3.5 to 0.5 V, Av = 1, 10 % to 90 %, RL = 10 kΩ, CL = 100 pF


    0.50


    0.78



    V/μs

    -40 °C < T < 125 °C

    0.37




    Positive slew rate

    Vin = 0.5 to 3.5 V, Av = 1, 10 % to 90 %, RL = 10 kΩ, CL = 100 pF


    0.50


    0.89


    -40 °C < T < 125 °C

    0.37




    en


    Equivalent input noise voltage

    f = 1 kHz


    20


    nV/√Hz

    f = 0.1 Hz to 10 Hz


    0.7


    μVpp

    THD+N

    Total harmonic distortion + noise

    f = 1 kHz, Vin = 3.8 Vpp, RL = 10 kΩ, CL = 100 pF


    0.001


    %


    Table 6. Electrical characteristics at Vcc = 12 V, Vicm = Vcc/2, Tamb = 25 °C, and RL connected to Vcc/2 (unless otherwise specified)


    Symbol

    Parameter

    Conditions

    Min.

    Typ.

    Max.

    Unit

    DC performance


    Vio


    Input offset voltage


    -1.5


    1.5


    mV

    -40 °C < T < 125 °C

    -2.1


    2.1

    ΔVio/ΔT

    Input offset voltage drift

    -40 °C < T < 125 °C


    1.5

    6

    μV/°C


    Iio


    Input offset current



    2

    15


    nA

    -40 °C < T < 125 °C



    35


    Iib


    Input bias current



    8

    30

    -40 °C < T < 125 °C



    70

    CIN

    Input capacitor



    2


    pF

    RIN

    Input impedance



    1



    CMR


    Common mode rejection ratio 20 log (ΔVicm/ΔVio)

    Vicm = (VCC-) to (VCC+) - 1.5 V, Vout = VCC/2

    100

    123



    dB

    -40 °C < T < 125 °C

    90



    Vicm = (VCC-) to (VCC+), Vout = VCC/2

    85

    106


    -40 °C < T < 125 °C

    80




    SVR

    Supply voltage rejection ratio 20 log (ΔVCC/ΔVio)

    VCC = 4 to 12 V

    90

    99


    -40 °C < T < 125 °C

    80




    Avd


    Large signal voltage gain

    RL= 10 kΩ, Vout = 0.5 to 11.5 V

    95

    106


    -40 °C < T < 125 °C

    90




    VOH

    High level output voltage (drop voltage from VCC+)

    RL = 10 kΩ


    38

    100


    mV

    -40 °C < T < 125 °C



    150


    VOL


    Low level output voltage

    RL = 10 kΩ


    16

    70

    -40 °C < T < 125 °C



    90


    Iout


    Isink

    Vout = VCC

    20

    42



    mA

    -40 °C < T < 125 °C

    8




    Isource

    Vout = 0 V

    15

    35


    -40 °C < T < 125 °C

    7




    Symbol

    Parameter

    Conditions

    Min.

    Typ.

    Max.

    Unit


    ICC


    Supply current (per channel)

    No load, Vout = VCC/2


    360

    450


    μA

    -40 °C < T < 125 °C



    530

    AC performance


    GBP


    Gain bandwidth product

    RL = 10 kΩ, CL = 100 pF

    1.6

    2.4



    MHz

    -40 °C < T < 125 °C

    1.3



    ϕm

    Phase margin

    RL = 10 kΩ, CL = 100 pF


    50


    degrees

    Gm

    Gain margin

    RL = 10 kΩ, CL = 100 pF


    6


    dB


    SR


    Negative slew rate

    Vin = 10.5 to 1.5 V, Av = 1, 10 % to 90 %, RL = 10 kΩ, CL = 100 pF


    0.53


    0.82



    V/μs

    -40 °C < T < 125 °C

    0.40




    Positive slew rate

    Vin = 1.5 to 10.5 V, Av = 1, 10 % to 90 %, RL = 10 kΩ, CL = 100 pF


    0.55


    0.92


    -40 °C < T < 125 °C

    0.40




    en


    Equivalent input noise voltage

    f = 1 kHz


    20


    nV/√Hz

    f = 0.1 Hz to 10 Hz


    0.7


    μVpp

    THD+N

    Total harmonic distortion + noise

    f = 1 kHz, Vin = 7 Vpp, RL = 10 kΩ, CL = 100 pF


    0.0005


    %


    Table 7. Electrical characteristics at Vcc = 36 V, Vicm = Vcc/2, Tamb = 25 °C, and RL connected to Vcc/2 (unless otherwise specified)


    Symbol

    Parameter

    Conditions

    Min.

    Typ.

    Max.

    Unit

    DC performance


    Vio


    Input offset voltage


    -1.5


    1.5


    mV

    -40 °C < T < 125 °C

    -2.1


    2.1

    ΔVio/ΔT

    Input offset voltage drift

    -40 °C < T < 125 °C


    1.5

    6

    μV/°C

    ΔVio

    Long-term input offset voltage drift (1)

    T = 25 °C


    1.5


    µV/√month


    Iio


    Input offset current



    2

    15


    nA

    -40 °C < T < 125 °C



    35


    Iib


    Input bias current



    8

    30

    -40 °C < T < 125 °C



    70

    CIN

    Input capacitor



    2


    pF

    RIN

    Input impedance



    1



    CMR


    Common mode rejection ratio 20 log (ΔVicm/ΔVio)

    Vicm = (VCC-) to (VCC+) - 1.5 V, Vout = VCC/2

    105

    129



    dB

    -40 °C < T < 125 °C

    95



    Vicm = (VCC-) to (VCC+), Vout = VCC/2

    95

    115


    -40 °C < T < 125 °C

    90




    SVR

    Supply voltage rejection ratio 20 log (ΔVCC/ΔVio)

    VCC = 4 to 36 V

    90

    104


    -40 °C < T < 125 °C

    85




    Avd


    Large signal voltage gain

    RL= 10 kΩ, Vout = 0.5 to 35.5 V

    95

    114


    -40 °C < T < 125 °C

    90




    Symbol

    Parameter

    Conditions

    Min.

    Typ.

    Max.

    Unit


    VOH

    High level output voltage (drop voltage from VCC+)

    RL = 10 kΩ


    78

    150


    mV

    -40 °C < T < 125 °C



    200


    VOL


    Low level output voltage

    RL = 10 kΩ


    30

    90

    -40 °C < T < 125 °C



    120


    Iout


    Isink

    Vout = VCC

    25

    65



    mA

    -40 °C < T < 125 °C

    10




    Isource

    Vout = 0 V

    20

    50


    -40 °C < T < 125 °C

    10




    ICC


    Supply current (per channel)

    No load, Vout = VCC/2


    380

    470


    μA

    -40 °C < T < 125 °C



    550

    AC performance


    GBP


    Gain bandwidth product

    RL = 10 kΩ, CL = 100 pF

    1.7

    2.5



    MHz

    -40 °C < T < 125 °C

    1.4



    ϕm

    Phase margin

    RL = 10 kΩ, CL = 100 pF


    50


    degrees

    Gm

    Gain margin

    RL = 10 kΩ, CL = 100 pF


    8


    dB


    SR


    Negative slew rate

    Vin = 22.5 to 13.5 V, Av = 1, 10 % to 90 %, RL = 10 kΩ, CL = 100 pF


    0.57


    0.88



    V/μs

    -40 °C < T < 125 °C

    0.44




    Positive slew rate

    Vin = 13.5 to 22.5 V, Av = 1, 10 % to 90 %, RL = 10 kΩ, CL = 100 pF


    0.60


    1.00


    -40 °C < T < 125 °C

    0.44




    en


    Equivalent input noise voltage

    f = 1 kHz


    20


    nV/√Hz

    f = 0.1 Hz to 10 Hz


    0.7


    μVpp

    THD+N

    Total harmonic distortion + noise

    f = 1 kHz, Vin = 7 Vpp, RL = 10 kΩ, CL = 100 pF


    0.001


    %

    1. Typical value is based on the Vio drift observed after 1000h at 125 °C extrapolated to 25 °C using Arrhenius law and assuming an activation energy of 0.7 eV. The operational amplifier is aged in follower mode configuration (see Section 4.5 Section 4.5).

    Population (%)

    Population (%)

    Supply Current (mA)

    Input offset voltage (mV)

    Population (%)

    Vcc=4V Vicm=2V T=25°C

    Figure 3. Supply current vs. supply voltage


    0.5

    Vicm = Vcc/2

    0.4

    T = 125 °C

    0.3

    T = 25°C

    0.2

    T = -40°C

    0.1


    0.0

    0

    5 10 15 20 25 30 35

    Supply Voltage (V)

    Figure 4. Input offset voltage distribution at VCC = 4 V


    35


    30


    25


    20


    15


    10


    5


    0

    -1.5 -1.2 -0.9 -0.6 -0.3 0.0 0.3 0.6 0.9 1.2 1.5

    Input offset voltage (mV)

    Figure 5. Input offset voltage distribution at VCC = 12 V


    35

    Vcc=12V

    30 Vicm=6V T=25°C

    25


    20


    15


    10


    5


    0

    -1.5 -1.2 -0.9 -0.6 -0.3 0.0 0.3 0.6 0.9 1.2 1.5

    Input offset voltage (mV)

    Figure 7. Input offset voltage vs. temperature at VCC = 36 V

    2.5

    2.0

    1.5

    1.0

    0.5

    0.0

    -0.5

    -1.0

    -1.5

    -2.0

    -2.5

    Figure 8. Input offset voltage temperature variation distribution at VCC = 36 V



    Figure 6. Input offset voltage distribution at VCC = 36 V


    35

    Vcc=36V

    30 Vicm=18V T=25°C

    25


    20


    15


    10


    5


    0

    -1.5 -1.2 -0.9 -0.6 -0.3 0.0 0.3 0.6 0.9 1.2 1.5

    Input offset voltage (mV)





    Vio limit





















































































    Vcc=36V

    Vicm=18V





















































































    -40 -20 0 20 40 60 80 100 120


    Temperature (°C)

    Output Current (mA)

    Input bias current (nA)

    Input bias current (nA)

    Input Offset Voltage (mV)

    Vicm=Vcc/2

    T=25°C

    T=-40°

    Figure 9. Input offset voltage vs. supply voltage


    -0.2


    -0.3


    -0.4


    -0.5

    -0.6

    C

    T=125°C

    -0.7


    -0.8

    4 8 12 16 20 24 28 32 36

    Supply voltage (V)

    Figure 10. Input offset voltage vs. common-mode voltage at VCC = 4 V

    Figure 11. Input offset voltage vs. common-mode voltage at VCC = 36 V

    Figure 12. Input bias current vs. temperature at VICM = VCC/2


    0

    Vicm=Vcc/2


    -2


    -4

    -6

    Vcc=4V

    Vcc=36V

    Vcc=12V

    -8


    -10

    Sink Vid=-1V

    T=125°C

    T=25°C

    T=-40°C

    Source Vid=1V

    Vcc=4V

    Figure 13. Input bias current vs. common-mode voltage at VCC = 36 V


    60

    Vcc=36V

    40 T=-40°C

    T=25°C

    20

    T=125°C


    0


    -20


    -40


    -60

    0 5 10 15 20 25 30 35

    Input Common Mode Voltage (V)















































































    -40 -20 0 20 40 60 80 100 120

    Temperature (°C)


    Figure 14. Output current vs. output voltage at VCC = 4 V


    50

    40

    30

    20

    10

    0

    -10

    -20

    -30

    -40

    -50

    0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0

    Output Voltage (V)

    Slew rate (V/µs)

    Output voltage drop (from Vcc+) (mV)

    Voltage (V)

    Output Current (mA)

    Output voltage (mV)

    Voltage (V)

    T=-40°C

    T=25°C

    T=125°C

    Vid=0.1V

    Rl=10kΩ to Vcc/2

    Figure 15. Output current vs. output voltage at VCC = 36 V

    70

    56

    42

    28

    14

    0

    -14

    -28

    -42

    -56

    -70

    0 5 10 15 20 25 30 35

    Output Voltage (V)

    Figure 17. Output voltage (Vol) vs. supply voltage


    40

    35

    30


    25


    20


    15


    10


    5


    0

    T=-40°C T=25°C T=125°C

    Vid=-0.1V

    Rl=10kΩ to Vcc/2

    4 8 12 16 20 24 28 32 36

    Power supply voltage (V)

    Figure 18. Negative slew rate at VCC = 36 V

    1.2

    1.0

    0.8

    0.6

    0.4

    0.2

    0.0

    -0.2

    -0.4

    -0.6

    -0.8

    -1.0

    -1.2

    T=-40°C

    Vcc=36V

    Vicm=Vcc/2 Rl=10kΩ Cl=100pF

    T=25°C

    T=125°C

    0.0 0.5 1.0 1.5

    2.0

    Time (µs)

    2.5 3.0 3.5 4.0

    1.2

    1.0

    0.8

    0.6

    0.4

    0.2

    0.0

    -0.2

    -0.4

    -0.6

    -0.8

    -1.0

    -1.2

    T=-40°C

    T=25°C

    T=125°C

    Vcc=36V

    Vicm=Vcc/2 Rl=10kΩ Cl=100pF

    0.0 0.5 1.0 1.5

    2.0

    Time (µs)

    2.5 3.0 3.5 4.0

    1.4

    1.2

    1.0

    0.8

    0.6

    0.4

    0.2

    0.0

    -0.2

    -0.4

    -0.6

    -0.8

    -1.0

    -1.2

    -1.4

    4.0

    Vicm=Vcc/2

    T=125°C T=25°C T=-40°C Vload=Vcc/2

    Rl=10kΩ Cl=100pF

    8.0 12.0 16.0 20.0 24.0 28.0 32.0 36.0

    Supply Voltage (V)


    Sink Vid=-1V



    Vcc=36V






































    T=125°C


    T=25°C


    T=-40°C































    Source

    Vid=1V









    Figure 16. Output voltage (Voh) vs. supply voltage


    110

    100

    90

    80

    70

    60

    50

    40

    30

    20

    10

    0

    4 8 12 16 20 24 28 32 36

    Power supply voltage (V)


    Figure 19. Positive slew rate at VCC = 36 V

    Figure 20. Slew rate vs. supply voltage

    Phase (°)

    Gain (dB)

    Overshoot (%)

    Phase (°)

    Phase margin(°)

    Gain (dB)

    60

    0

    T=-40°C T=25°C

    40 T=125°C -60

    20

    Phase

    -120

    Gain

    0

    -180

    -40 Rl=10kΩ

    Cl=100pF

    Gain=100

    1k 10k

    100k

    Frequency (Hz)

    1M

    -360 10M

    60

    0

    T=-40°C T=25°C

    40 T=125°C -60


    Phase

    20 -120

    Gain

    0

    -180

    -40 Rl=10kΩ

    Cl=100pF

    Gain=100

    1k 10k

    100k

    Frequency (Hz)

    1M

    -360 10M

    V

    cc=4V

    Vcc=36V

    Vicm=Vcc/2 Rl=10kΩ T=25°C

    30

    20

    10

    200 300 400 500 700 1000

    Capacitive load (pF)

    Vcc=36V

    Vicm=Vcc/2 Rl=10kΩ

    Vin=100mVpp Gain=1 T=25°C

    60


    40


    20

    Sustained Oscillations

    10

    100

    1000

    10000

    Capacitive load (pF)



    Figure 21. Bode diagram at VCC = 4 V

    Figure 22. Bode diagram at VCC = 36 V


    -20 Vcc=4V

    Vicm=2V

    -240

    -20 Vcc=36V

    Vicm=18V

    -240


    -300


    -60

    -300


    -60


    Figure 23. Phase margin vs. output current at VCC = 4 V

    Figure 24. Phase margin vs. output current at VCC = 36 V

    100


    100

    90

    90

    80

    80

    70

    70

    60

    60

    50

    50

    40

    40

    30

    30

    20

    20

    10

    10

    0

    -1.0 -0.8 -0.6 -0.4 -0.2 0.0 0.2 0.4 0.6 0.8 1.0

    0

    -1.0 -0.8 -0.6 -0.4 -0.2 0.0 0.2 0.4 0.6 0.8 1.0


    Figure 25. Phase margin vs. capacitive load


    50

    Figure 26. Overshoot vs. capacitive load at VCC = 36 V


    100


    40

    80


    0

    100

    0

    Input and Output voltages (V)

    Equivalent Input Noise Voltage (nV/Hz)

    THD + N (%)

    35.70

    35.75

    35.80

    35.85

    35.90

    35.95

    36.00

    0.00

    0.05

    0.10

    0.15

    0.20

    0.25

    Output voltage (V)

    Input voltage nosie (nV)

    Output Voltage (V)

    Vcc=4V

    Rl=10kΩ Cl=100pF

    Follower Configuration T=25°C

    Vicm=2V

    0.07

    0.00

    -0.07

    2.5

    5.0

    Time (µs)

    7.5

    10.0

    20


    15


    10


    5

    Vcc=+/-18V Vicm=0V Gain=4.7 Rl=10kΩ Cl=100pF

    0


    -5


    -10


    -15


    -20

    Time (µs)

    Vicm=Vcc/2 T=25°C

    Figure 29. Amplifier behavior close to the rails at VCC = 36 V


    36.00

    35.95

    35.90

    35.85

    35.80

    35.75

    35.70

    0.25

    0.20

    0.15

    0.10

    0.05

    0.00


    Input voltage (V)

    Frequency (Hz)

    Figure 31. Noise vs. time at VCC = 36 V

    400


    300


    200


    100


    0


    -100


    -200


    -300


    -400

    0 1 2 3 4 5 6 7 8 9 10

    Time (s)

    Vicm=Vcc/2 Gain=1 Rl=10kΩ

    Cl=100pF BW=80kHz T=25°C

    1E-3

    Vcc=4V

    with Vin=3.8Vpp

    Vcc=12V

    with Vin=7Vpp

    Vcc=36V

    with Vin=7Vpp

    1E-4

    10

    100

    1000

    10000

    Frequency (Hz)



    Figure 27. Small step response vs. time at VCC = 4 V

    0.15

    Figure 28. Output desaturation vs. time


    -0.15

    0.0

    0

    200

    400

    600

    800

    1000





























































































    T=-40°C

    T=25°C











    T=125°C









    Vcc=36V

    Follower configuration





















    Figure 30. Noise vs. frequency at VCC = 36 V

    100

    @Vcc=36V

    @Vcc=12V

    80 @Vcc=4V


    60


    40


    20


    0

    10

    100

    1000

    10000



    Figure 32. THD+N vs. frequency


    0.01

    Vcc=36V

    Vicm=Vcc/2 Vload=Vcc/


    2































































































































    PSRR (dB)

    Channel Separation refered to input (dB)

    THD + N (%)

    1E-3

    Vicm=Vcc/2 Gain=1 f=1kHz BW=22kHz

    Rl=10kΩ Cl=100pF T=25°C

    4V

    12V

    36V

    1E-4

    0.01 0.1 1 10

    Output Voltage (Vpp)

    -80

    PSRR -

    -100

    -120

    10

    100

    1k

    Frequency (Hz)

    10k

    100k



    Figure 33. THD+N vs. output voltage

    0.1

    Figure 34. PSRR vs. frequency at VCC = 36 V

    -20



    -40


    0.01

    -60

    PSRR +



    Figure 35. Channel separation vs. frequency at VCC= 36 V


    160


    140


    120

    Vcc=36V

    Vicm=18V Gain=11 Vin = 1Vpp


    100


    80


    60


    40


    20


    0

    100

    1k

    10k

    Frequency (Hz)

    100k

    1M

    Application information


  4. Application information


    1. Operating voltages


      The TSB571 and TSB572 can operate from 4 V to 36 V. The parameters are fully specified for 4 V, 12 V, and 36 V power supplies. However, the parameters are stable in the full VCC range. Additionally, the main specifications are guaranteed in extended temperature ranges from -40 to 125 °C.

    2. Input pin voltage ranges


      The TSB571 and TSB572 have an internal ESD diode protection on the inputs. These diodes are connected between the inputs and each supply rail to protect the input transistors from electrical discharge.

      If the input pin voltage exceeds the power supply by 0.2 V, the ESD diodes become conductive and excessive current can flow through them. Without limitation this over current can damage the device.

      In this case, it is important to limit the current to 10 mA, by adding resistance on the input pin, as shown in Figure 37. Input current limitation.


      Figure 36. Input current limitation



      16 V


      R - +

      Vin + -


      Vout



    3. Rail-to-rail input


      The TSB571 and TSB572 have rail-to-rail inputs. The input common mode range is extended from (VCC -) - 0.1 V to (VCC+) + 0.1 V at T = 25 °C.

    4. Input offset voltage drift over temperature


      The maximum input voltage drift variation over temperature is defined as the offset variation related to the offset value measured at 25 °C. The operational amplifier is one of the main circuits of the signal conditioning chain, and the amplifier input offset is a major contributor to the chain accuracy. The signal chain accuracy at 25 °C can be compensated during production at application level. The maximum input voltage drift over temperature enables the system designer to anticipate the effect of temperature variations.

      The maximum input voltage drift over temperature is computed using Equation 1.

      Equation 1

      ∆Vio = ma x VioTVio 25 °C

      ∆T


      where T = -40 °C and 125 °C.

      T 25 °C

      The TSB571 and TSB572 datasheet maximum value is guaranteed by measurements on a representative sample size ensuring a Cpk (process capability index) greater than 1.3.

    5. Long term input offset voltage drift


      To evaluate product reliability, two types of stress acceleration are used:

      Long term input offset voltage drift



    6. Capacitive load


      Driving large capacitive loads can cause stability problems. Increasing the load capacitance produces gain peaking in the frequency response, with overshoot and ringing in the step response. It is usually considered that with a gain peaking higher than 2.3 dB an op amp might become unstable.

      Generally, unity gain configuration is the worst situation for stability and the ability to drive large capacitive loads.

      Figure 38. Stability criteria with a serial resistor at different supply voltages shows the serial resistor that must be added to the output, to make a system stable. Figure 39. Test configuration for Riso shows the test configuration using an isolation resistor, Riso.


      Figure 37. Stability criteria with a serial resistor at different supply voltages



      100


      Serial Riso (Ω)

      10


      Stable

      Vcc=36V

      Vicm=18V follower configuration T=25°C



      1


      0.1

      Unstable


      @Vcc=4V

      @Vcc=12V

      @Vcc=36V

      102 103 104 105 106

      Capacitive load (pF)


      Figure 38. Test configuration for Riso



      -

      VIN +

      VCC+


      VCC-


      Riso


      Cload


      VOUT 10 kΩ


    7. PCB layout recommendations


      Particular attention must be paid to the layout of the PCB tracks connected to the amplifier, load, and power supply. The power and ground traces are critical as they must provide adequate energy and grounding for all circuits. The best practice is to use short and wide PCB traces to minimize voltage drops and parasitic inductance.

      In addition, to minimizing parasitic impedance over the entire surface, a multi-via technique that connects the bottom and top layer ground planes together in many locations is often used.

      The copper traces that connect the output pins to the load and supply pins should be as wide as possible to minimize trace resistance.

    8. Optimized application recommendation


      It is recommended to place a 22 nF capacitor as close as possible to the supply pin. A good decoupling will help to reduce electromagnetic interference impact.

      Package information


  1. Package information


    In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com. ECOPACK is an ST trademark.

    1. SOT23-5 package information


      Figure 39. SOT23-5 package outline

      SOT23-5 package information



      Table 8. SOT23-5 package mechanical data



      Ref.

      Dimensions

      Millimeters

      Inches

      Min.

      Typ.

      Max.

      Min.

      Typ.

      Max.

      A

      0.90

      1.20

      1.45

      0.035

      0.047

      0.057

      A1



      0.15



      0.006

      A2

      0.90

      1.05

      1.30

      0.035

      0.041

      0.051

      B

      0.35

      0.40

      0.50

      0.014

      0.016

      0.020

      C

      0.09

      0.15

      0.20

      0.004

      0.006

      0.020

      D

      2.80

      2.90

      3.00

      0.110

      0.114

      0.118

      D1


      1.90



      0.075


      e


      0.95



      0.037


      E

      2.60

      2.80

      3.00

      0.102

      0.110

      0.118

      F

      1.50

      1.60

      1.75

      0.059

      0.063

      0.069

      L

      0.10

      0.35

      0.60

      0.004

      0.014

      0.024

      K


      10°


      10°

      MiniSO8 package information



    2. MiniSO8 package information


      Figure 40. MiniSO8 package outline


      Table 9. MiniSO8 package mechanical data



      Ref.

      Dimensions

      Millimeters

      Inches

      Min.

      Typ.

      Max.

      Min.

      Typ.

      Max.

      A



      1.1



      0.043

      A1

      0


      0.15

      0


      0.0006

      A2

      0.75

      0.85

      0.95

      0.030

      0.033

      0.037

      b

      0.22


      0.40

      0.009


      0.016

      c

      0.08


      0.23

      0.003


      0.009

      D

      2.80

      3.00

      3.20

      0.11

      0.118

      0.126

      E

      4.65

      4.90

      5.15

      0.183

      0.193

      0.203

      E1

      2.80

      3.00

      3.10

      0.11

      0.118

      0.122

      e


      0.65



      0.026


      L

      0.40

      0.60

      0.80

      0.016

      0.024

      0.031

      L1


      0.95



      0.037


      L2


      0.25



      0.010


      k



      ccc



      0.10



      0.004


    3. DFN8 3x3 package information


      Figure 41. DFN8 3x3 package outline and mechanical data



      BOTTOM VIEW


      DETAIL A


      SIDE VIEW


      TOP VIEW



      Table 10. DFN8 3x3 mechanical data



      Symbol

      mm

      Min.

      Typ.

      Max.

      A

      0.70

      0.75

      0.80

      A1

      0.0


      0.05

      A3

      0.20 Ref.

      b

      0.25

      0.30

      0.35

      D

      2.95

      3.00

      3.05

      D2

      2.25

      2.35

      2.45

      e

      0.65 BSC

      E

      2.95

      3.00

      3.05

      E2

      1.45

      1.55

      1.65

      L

      0.35

      0.45

      0.55

      K

      2.75 Ref.

      N

      8


      Figure 42. DFN8 3x3 footprint data






      SO-8 package information



    4. SO-8 package information


      Figure 43. SO-8 package outline



      0016023_So-807_fig2_Rev10



      Table 11. SO-8 mechanical data



      Dim.

      mm

      Min.

      Typ.

      Max.

      A



      1.75

      A1

      0.10


      0.25

      A2

      1.25



      b

      0.31


      0.51

      b1

      0.28


      0.48

      c

      0.10


      0.25

      c1

      0.10


      0.23

      D

      4.80

      4.90

      5.00

      E

      5.80

      6.00

      6.20

      E1

      3.80

      3.90

      4.00

      e


      1.27


      h

      0.25


      0.50

      L

      0.40


      1.27

      L1


      1.04


      L2


      0.25


      k


      ccc



      0.10

      Ordering information


  2. Ordering information


Table 12. Order codes


Order code

Temperature range

Package

Packing

Marking

TSB571ILT


-40 °C to +125 °C


SOT23-5


Tape and reel

K31

TSB572IYLT (1)

K32

TSB572IQ2T


-40 °C to 125 °C


DFN8 3x3


Tape and reel

K31

TSB572IYQ2T (1)

K32

TSB572IST


MiniSO8

K31

TSB572IYST (1)

K32

TSB572IDT

SO8 package

TSB572I

1. Automotive qualification according to AEC-Q100.


Revision history


Table 13. Document revision history


Date

Version

Changes

12-Oct-2015

1

Initial release


17-Dec-2015


2

Section 2: "Absolute maximum ratings and operating conditions": updated ESD, MM value. Section 6: "Ordering information": removed footnote (1) from order code TSB572IQ2T


26-Jun-2017


3

In Table1: "Absolute maximum ratings":

  • Updated Latch-up immunity Parameter Value

  • updated footnote (3)

10-Nov-2017

4

Added: new SO-8 Package information and new order code TSB572IDT Section 6 Ordering information

26-Mar-2018

5

Updated: Section 5.2 DFN8 3x3 package information

22-Jul-2019

6

Added the root part number TSB571 and updated the whole document accordingly.

Contents


Contents

  1. Package pin connections 2

  2. Absolute maximum ratings and operating conditions 4

  3. Electrical characteristics 5

  4. Application information 15

    1. Operating voltages 15

    2. Input pin voltage ranges 15

    3. Rail-to-rail input 15

    4. Input offset voltage drift over temperature 15

    5. Long term input offset voltage drift 15

    6. Capacitive load 16

    7. PCB layout recommendations 17

    8. Optimized application recommendation 17

  5. Package information 18

    1. SOT23-5 package information 18

    2. MiniSO8 package information 20

    3. DFN8 3x3 package information 20

    4. SO-8 package outline 23

  6. Ordering information 24

Revision history 25

List of tables


List of tables

Table 1. Pin description (SOT23-5) 2

Table 2. Pin description (miniSO8/SO8/DFN8) 3

Table 3. Absolute maximum ratings 4

Table 4. Operating conditions 4

Table 5. Electrical characteristics at Vcc = 4 V, Vicm = Vcc/2, Tamb = 25 °C, and RL connected to Vcc/2 (unless otherwise specified) 5

Table 6. Electrical characteristics at Vcc = 12 V, Vicm = Vcc/2, Tamb = 25 °C, and RL connected to Vcc/2 (unless otherwise specified) 6

Table 7. Electrical characteristics at Vcc = 36 V, Vicm = Vcc/2, Tamb = 25 °C, and RL connected to Vcc/2 (unless otherwise specified) 7

Table 8. SOT23-5 package mechanical data 19

Table 9. MiniSO8 package mechanical data 20

Table 10. DFN8 3x3 mechanical data 21

Table 11. SO-8 mechanical data 23

Table 12. Order codes 24

Table 13. Document revision history 25

List of figures


List of figures

Figure 1. Pin connections (top view) 2

Figure 2. Pin connections for each package (top view) 2

Figure 3. Supply current vs. supply voltage 9

Figure 4. Input offset voltage distribution at VCC = 4 V 9

Figure 5. Input offset voltage distribution at VCC = 12 V 9

Figure 6. Input offset voltage distribution at VCC = 36 V 9

Figure 7. Input offset voltage vs. temperature at VCC = 36 V 9

Figure 8. Input offset voltage temperature variation distribution at VCC = 36 V 9

Figure 9. Input offset voltage vs. supply voltage 10

Figure 10. Input offset voltage vs. common-mode voltage at VCC = 4 V 10

Figure 11. Input offset voltage vs. common-mode voltage at VCC = 36 V 10

Figure 12. Input bias current vs. temperature at VICM = VCC/2 10

Figure 13. Input bias current vs. common-mode voltage at VCC = 36 V 10

Figure 14. Output current vs. output voltage at VCC = 4 V 10

Figure 15. Output current vs. output voltage at VCC = 36 V 11

Figure 16. Output voltage (Voh) vs. supply voltage 11

Figure 17. Output voltage (Vol) vs. supply voltage 11

Figure 18. Negative slew rate at VCC = 36 V 11

Figure 19. Positive slew rate at VCC = 36 V 11

Figure 20. Slew rate vs. supply voltage 11

Figure 21. Bode diagram at VCC = 4 V 12

Figure 22. Bode diagram at VCC = 36 V 12

Figure 23. Phase margin vs. output current at VCC = 4 V 12

Figure 24. Phase margin vs. output current at VCC = 36 V 12

Figure 25. Phase margin vs. capacitive load 12

Figure 26. Overshoot vs. capacitive load at VCC = 36 V 12

Figure 27. Small step response vs. time at VCC = 4 V 13

Figure 28. Output desaturation vs. time 13

Figure 29. Amplifier behavior close to the rails at VCC = 36 V 13

Figure 30. Noise vs. frequency at VCC = 36 V 13

Figure 31. Noise vs. time at VCC = 36 V 13

Figure 32. THD+N vs. frequency 13

Figure 33. THD+N vs. output voltage 14

Figure 34. PSRR vs. frequency at VCC = 36 V 14

Figure 35. Channel separation vs. frequency at VCC= 36 V 14

Figure 36. Input current limitation 15

Figure 37. Stability criteria with a serial resistor at different supply voltages 17

Figure 38. Test configuration for Riso 17

Figure 39. SOT23-5 package outline 18

Figure 40. MiniSO8 package outline 20

Figure 41. DFN8 3x3 package outline and mechanical data 21

Figure 42. DFN8 3x3 footprint data 22

Figure 43. SO-8 package outline 23


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