MC33272A, MC33274A, NCV33272A, NCV33274A


Single Supply, High Slew Rate,

Low Input Offset Voltage Operational Amplifiers

The MC33272/74 series of monolithic operational amplifiers are


http://onsemi.com


MARKING

quality fabricated with innovative Bipolar design concepts. This dual and quad operational amplifier series incorporates Bipolar inputs along with a patented Zip−R−Trim element for input offset voltage reduction. The MC33272/74 series of operational amplifiers exhibits low input offset voltage and high gain bandwidth product. Dual−doublet frequency compensation is used to increase the slew rate while maintaining low input noise characteristics. Its all NPN output stage exhibits no deadband crossover distortion, large output voltage swing, and an excellent phase and gain margin. It also provides a low open loop high frequency output impedance with symmetrical source and sink AC frequency performance.

Features

DUAL


PDIP8 P SUFFIX

8 CASE 626

1


SOIC8

8 D SUFFIX

1 CASE 751

x = A for MC33272AD/DR2

= N for NCV33272ADR2

DIAGRAMS

8

MC33272AP

AWL YYWWG

1






33272

ALYWx







8


1


1 1


TSSOP14

14 DTB SUFFIX

CASE 948G

1

3274

274A

14 14

MC33

NCV3


ALYW■

ALYW■


1 1

A = Assembly Location WL, L = Wafer Lot

YY, Y = Year

WW, W = Work Week

G or ■ = PbFree Package (Note: Microdot may be in either location)


ORDERING INFORMATION

See detailed ordering and shipping information in the package dimensions section on page 11 of this data sheet.


Semiconductor Components Industries, LLC, 2013

1 Publication Order Number:


PIN CONNECTIONS


DUAL CASE 626/751

QUAD

CASE 646/751A/948G

Output 1 1

2 -

Inputs 1 +

3


VEE 4

8 VCC

7 Output 2

+

- 6 Inputs 2

5


Output 1 1

2

-

Inputs 1 -

3

+ 1 4 +


Output 4


13

12

14

Inputs 4

(Top View)

VCC 4

5 +

2

Inputs 2 -

6


Output 2 7

VEE

10

11

+

9

-

3

Inputs 3


8

Output 3


(Top View)


MAXIMUM RATINGS


Rating

Symbol

Value

Unit

Supply Voltage

VCC to VEE

+36

V

Input Differential Voltage Range

VIDR

Note 1

V

Input Voltage Range

VIR

Note 1

V

Output Short Circuit Duration (Note 2)

tSC

Indefinite

sec

Maximum Junction Temperature

TJ

+150

C

Storage Temperature

Tstg

60 to +150

C

ESD Protection at Any Pin

Human Body Model

Machine Model

Vesd


2000

200

V

Maximum Power Dissipation

PD

Note 2

mW

Operating Temperature Range MC33272A, MC33274A NCV33272A, NCV33274A

TA

40 to +85

40 to +125

C

Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability.

  1. Either or both input voltages should not exceed VCC or VEE.

  2. Power dissipation must be considered to ensure maximum junction temperature (TJ) is not exceeded (see Figure 2).


DC ELECTRICAL CHARACTERISTICS (VCC = +15 V, VEE = 15 V, TA = 25C, unless otherwise noted.)

Characteristics

Figure

Symbol

Min

Typ

Max

Unit

Input Offset Voltage (RS = 10 Q, VCM = 0 V, VO = 0 V) (VCC = +15 V, VEE = 15 V)

TA = +25C

TA = 40 to +85C

TA = 40 to +125C (NCV33272A) TA = 40 to +125C (NCV33274A)

(VCC = 5.0 V, VEE = 0) TA = +25C

3

|VIO|




mV



0.1

1.0




1.8




2.5




3.5




2.0


Average Temperature Coefficient of Input Offset Voltage

RS = 10 Q, VCM = 0 V, VO = 0 V, TA = 40 to +125C

3

�VIO/�T



2.0


µV/C

Input Bias Current (VCM = 0 V, VO = 0 V) TA = +25C

TA = Tlow to Thigh

4, 5

IIB



300


650

800

nA

Input Offset Current (VCM = 0 V, VO = 0 V) TA = +25C

TA = Tlow to Thigh


|IIO|



3.0


65

80

nA

Common Mode Input Voltage Range (�VIO = 5.0 mV, VO = 0 V) TA = +25C

6

VICR


VEE to (VCC 1.8)

V

Large Signal Voltage Gain (VO = 0 V to 10 V, RL = 2.0 kQ) TA = +25C

TA = Tlow to Thigh

7

AVOL


90

86


100


dB

Output Voltage Swing (VID = 1.0 V) (VCC = +15 V, VEE = 15 V)

RL = 2.0 kQ RL = 2.0 kQ RL = 10 kQ RL = 10 kQ

(VCC = 5.0 V, VEE = 0 V)

RL = 2.0 kQ RL = 2.0 kQ

8, 9, 12


10, 11


VO + VO VO + VO

VOL VOH


13.4

13.4


3.7


13.9

13.9

14

14.7



13.5

14.1

0.2

5.0

V

Common Mode Rejection (Vin = +13.2 V to 15 V)

13

CMR

80

100

dB

Power Supply Rejection

VCC/VEE = +15 V/ 15 V, +5.0 V/ 15 V, +15 V/ 5.0 V

14, 15

PSR


80


105


dB

Output Short Circuit Current (VID = 1.0 V, Output to Ground) Source

16

ISC


+25


+37


mA

Sink



25

37


Power Supply Current Per Amplifier (VO = 0 V) (VCC = +15 V, VEE = 15 V)

TA = +25C

TA = Tlow to Thigh (VCC = 5.0 V, VEE = 0 V)

TA = +25C

17

ICC




mA



2.15

2.75

3.0




2.75


3. MC33272A, MC33274A Tlow = 40C Thigh = +85C NCV33272A, NCV33274A Tlow = 40C Thigh = +125C


AC ELECTRICAL CHARACTERISTICS (VCC = +15 V, VEE = 15 V, TA = 25C, unless otherwise noted.)

Characteristics Figure Symbol Min Typ Max Unit

Slew Rate

(Vin = 10 V to +10 V, RL = 2.0 kQ, CL = 100 pF, AV = +1.0 V)

18, 33 SR


8.0 10

V/µs

Gain Bandwidth Product (f = 100 kHz) 19 GBW 17 24 MHz

AC Voltage Gain (RL = 2.0 kQ, VO = 0 V, f = 20 kHz) 20, 21, 22 AVO 65 dB

Unity Gain Bandwidth (Open Loop) BW 5.5 MHz

Gain Margin (RL = 2.0 kQ, CL = 0 pF) 23, 24, 26 Am 12 dB

Phase Margin (RL = 2.0 kQ, CL = 0 pF) 23, 25, 26 m 55 Deg

Channel Separation (f = 20 Hz to 20 kHz) 27 CS − −120 dB Power Bandwidth (VO = 20 Vpp, RL = 2.0 kQ, THD 1.0%) BWP 160 kHz

Total Harmonic Distortion

(RL = 2.0 kQ, f = 20 Hz to 20 kHz, VO = 3.0 Vrms, AV = +1.0)

28 THD

%

0.003

Open Loop Output Impedance (VO = 0 V, f = 6.0 MHz) 29 |ZO| 35 Q

Differential Input Resistance (VCM = 0 V) Rin 16 MQ

Differential Input Capacitance (VCM = 0 V) Cin 3.0 pF Equivalent Input Noise Voltage (RS = 100 Q, f = 1.0 kHz) 30 en 18 nV/ Hz Equivalent Input Noise Current (f = 1.0 kHz) 31 in 0.5 pA/ Hz


VCC



-

Vin


Sections

B C D

+

Vin

+

VO


+


VEE


Figure 1. Equivalent Circuit Schematic

(Each Amplifier)


PD (MAX), MAXIMUM POWER DISSIPATION (mW)














MC33272P & MC33274P
























MC33274D













MC33272D

























2400 5.0


2000


1600


1200


800


400


3.0


VIO, INPUT OFFSET VOLTAGE (mV)

1.0


-1.0


-3.0

VCC = +15 V VEE = -15 V VCM = 0 V

1

3

1

2

2

3

1. VIO > 0 @ 25C

2. VIO = 0 @ 25C

3. VIO < 0 @ 25C


0

-60 -40 -20


0 20 40 60 80 100 120 140 160 180

TA, AMBIENT TEMPERATURE (C)

-5.0

-55 -25 0 25 50 75 100 125

TA, AMBIENT TEMPERATURE (C)

Figure 2. Maximum Power Dissipation versus Temperature

Figure 3. Input Offset Voltage versus Temperature for Typical Units












































VCC = +15 V VEE = -15 V TA = 25C





















400

I IB, INPUT BIAS CURRENT (nA)

350


300


250


200


150

100


50


0

600


I IB, INPUT BIAS CURRENT (nA)

500


400


300


200


100


0


VCC = +15 V VEE = -15 V VCM = 0 V

-16 -12 -8.0 -4.0 0 4.0 8.0 12 16

VCM, COMMON MODE VOLTAGE (V)

Figure 4. Input Bias Current versus Common Mode Voltage

-55 -25 0 25 50 75 100 125

TA, AMBIENT TEMPERATURE (C)

Figure 5. Input Bias Current versus Temperature


VICR, INPUT COMMON MODE VOLTAGE RANGE (V)

VCC VCC -0.5

VCC -1.0

VCC -1.5

VCC -2.0

180


AVOL, OPEN LOOP VOLTAGE GAIN (X 1.0 kV/V)

160


140





VCC


































VCC = +15 V

VEE

+1.0

VCC = +5.0 V to +18 V VEE = -5.0 V to -18 V

120

VEE = -15 V RL = 2.0 kQ

VEE +0.5

VEE

VEE

�VIO = 5.0 mV VO = 0 V


100

f = 10 Hz

�VO = -10 V to +10 V

-55 -25 0 25 50 75 100 125

TA, AMBIENT TEMPERATURE (C)

Figure 6. Input Common Mode Voltage Range versus Temperature

-55 -25 0 25 50 75 100 125

TA, AMBIENT TEMPERATURE (C)

Figure 7. Open Loop Voltage Gain versus Temperature


40


VO, OUTPUT VOLTAGE (Vpp )

TA = 25C

30


20


10


0


RL = 10 kQ

RL = 2.0 kQ

VCC VCC -1.0

Vsat , OUTPUT SATURATION VOLTAGE (V)

VCC -2.0


VEE +2.0


VEE +1.0


VEE


S


TA = 125C


TA = 125C


ink

TA = 25C


Source

TA = -55C TA = 25C


TA = -55C


VCC = +5.0 V to +18 V VEE = -5.0 V to -18 V

0 5.0 10 15 20

VCC, VEE SUPPLY VOLTAGE (V)

Figure 8. Split Supply Output Voltage Swing versus Supply Voltage

0 5.0 10 15 20

IL, LOAD CURRENT (mA)

Figure 9. Split Supply Output Saturation Voltage versus Load Current



Vsat , OUTPUT SATURATION VOLTAGE (V)

VCC


VCC


-4.0


TA = 125C


TA = 55C


VCC VCC = +5.0 V to +18 V


15


Vsat , OUTPUT SATURATION VOLTAGE (V)

14.6


T = 25C


TA = 125C

VCC -8.0


VCC -12

RL to Gnd

VEE = Gnd

14.2

A


TA = 55C


+0.2


+0.1


0


Gnd


TA = 125C TA = +25C TA = -55C

8.0


4.0


0

TA = 25C TA = -55C

TA = 125C VCC = +15 V RL to VCC VEE = Gnd

RFdbk = 100 kQ

100 1.0 k 10 k 100 k 1.0 M

10 100 1.0 k

10 k

100 k

RL , LOAD RESISTANCE TO GROUND (kQ)

Figure 10. Single Supply Output Saturation Voltage versus Load Resistance to Ground

RL, LOAD RESISTANCE TO VCC (Q)

Figure 11. Single Supply Output Saturation Voltage versus Load Resistance to VCC



CMR, COMMON MODE REJECTION (dB)





















































































































































VCC = +15 V VEE = -15 V RL = 2.0 kQ AV = +1.0 THD = 1.0%

TA = 25C






















































































































28 120


VO, OUTPUT VOLTAGE (Vpp )

24 100

20

80

16

60

12


TA = 125C


- A


TA = -55C


VCC = +15 V VEE = -15 V VCM = 0 V

�VCM = 1.5 V

40

8

4 20

0 0

�VCM


CMR = 20Log

DM

+


�VCM

�VO

�VO


X ADM

1.0 k 10 k

100 k

f, FREQUENCY (Hz)

1.0 M 1 0M

10 100 1.0 k 10 k 100 k 1.0 M

f, FREQUENCY (Hz)

Figure 12. Output Voltage versus Frequency Figure 13. Common Mode Rejection

versus Frequency


+PSR, POWER SUPPLY REJECTION (dB)

120


100


80


60


40


20


TA = 125


C

-

ADM

+


VCC


VEE


�VO


�VO/ADM


VCC = +15 V VEE = -15 V

�VCC = 1.5 V


TA = -55C

120


-PSR, POWER SUPPLY REJECTION (dB)

100


80


60


40


20


-

ADM

+


VCC


VEE


�VO


�VO/ADM


TA = -55C


TA = 125C


�VCC = 1.5 V VCC = +15 V VEE = -15 V

+PSR = 20Log

0

�VCC

-PSR = 20Log

0

�VEE

10 100 1.0 k 10 k 100 k 1 .0 M

f, FREQUENCY (Hz)

Figure 14. Positive Power Supply Rejection versus Frequency

10 100 1.0 k 10 k 100 k 1.0 M

f, FREQUENCY (Hz)

Figure 15. Negative Power Supply Rejection versus Frequency



|I SC |, OUTPUT SHORT CIRCUIT CURRENT (mA)

60


50


Sink

40

Source

30


20


10


VCC = +15 V VEE = -15 V VID = 1.0 V RL < 100 Q


Sink Source


11


I CC , SUPPLY CURRENT (mA)

10


9.0


8.0


7.0


6.0


5.0


4.0


TA = +125C


TA = +25C

TA = -55C


0

-55 -25 0 25 50 75 100 125

TA, AMBIENT TEMPERATURE (C)

Figure 16. Output Short Circuit Current versus Temperature


3.0


0 2.0 4.0 6.0 8.0 10 12 14 16 18 20

VCC, |VEE| , SUPPLY VOLTAGE (V)

Figure 17. Supply Current versus Supply Voltage


1.15


SR, SLEW RATE (NORMALIZED)

1.1


1.05


1.0


0.95


0.9


�Vin


-

+

2.0 kQ


VO 100 pF

50


GBW, GAIN BANDWIDTH PRODUCT (MHz)






VCC = +15 V VEE = -15 V

f = 100 kHz

RL = 2.0 kQ CL = 0 pF






























































40


30

VCC = +15 V 20

VEE = -15 V

�Vin = 20 V

10


0.85

-55 -25 0 25 50 75 100 125

TA, AMBIENT TEMPERATURE (C)

Figure 18. Normalized Slew Rate versus Temperature

0

-55 -25 0 25 50 75 100 125

TA, AMBIENT TEMPERATURE (C)

Figure 19. Gain Bandwidth Product versus Temperature


25

20

AV, VOLTAGE GAIN (dB)

15

10

5.0

0

-5.0

-10

-15

-20

-25


Phase


VCC = +15 V VEE = -15 V RL = 2.0 kQ TA = 25C


Gain

80

 EXCESS PHASE (DEGREES)

AV, VOLTAGE GAIN (dB)

100

120

140

160

180

200

220

240

260

280

25

20

15

10

5.0

0

-5.0

-10

-15

-20

-25


TA = 25C 1A

CL = 0 pF


2A

1B

1A - Phase VCC = 18 V, VEE = -18 V

2A - Phase VCC = 1.5 V, VEE = -1.5 V 2B

1B - Gain VCC = 18 V, VEE = -18 V

2B - Gain VCC = 1.5 V, VEE = -1.5 V

80

100

 PHASE (DEGREES)

120

140

160

180

200

220

240

100 k 1.0 M 10 M 100 M

f, FREQUENCY (Hz)

Figure 20. Voltage Gain and Phase versus Frequency

100 k 1.0 M 10 M 100 M

f, FREQUENCY (Hz)

Figure 21. Gain and Phase versus Frequency


A VOL , OPEN LOOP VOLTAGE GAIN (dB)

20


10


0


-10


-20


-30


2A

1A

VCC = +15 V VEE = -15 V

1B

Vout = 0 V TA = 25C

1A - Phase (RL = 2.0 kQ)

2A - Phase (RL = 2.0 kQ, CL = 300 pF)

1B - Gain (RL = 2.0 kQ)

2B - Gain (RL = 2.0 kQ, CL = 300 pF)

100

120

140

160

180

200

220

2B

240

260

280

12


EXCESS PHASE (DEGREES)

A m , OPEN LOOP GAIN MARGIN (dB)

10


8.0


6.0


4.0


2.0


0

0


Gain Margin

m, PHASE MARGIN (DEGREES)

10

VCC = +15 V

VEE = -15 V 20

VO = 0 V

- 30

Vin VO

+

2.0 kQ CL 40



Phase Margin

50

3.0 4.0 6.0 8.0 10 20 30

f, FREQUENCY (MHz)

Figure 22. Open Loop Voltage Gain and Phase versus Frequency

1.0 10 100 1000

CL, OUTPUT LOAD CAPACITANCE (pF)

Figure 23. Open Loop Gain Margin and Phase Margin versus Output Load Capacitance


A m , OPEN LOOP GAIN MARGIN (dB)

12


10


8.0


6.0


4.0


2.0


0


CL = 10 pF


CL = 100 pF CL = 300 pF

CL = 500 pF

60


m, PHASE MARGIN (DEGREES)

50


40


30


20

VCC = +15 V 10

VEE = -15 V

0


CL = 10 pF


CL = 100 pF CL = 300 pF


CL = 500 pF


VCC = +15 V VEE = -15 V

-55 -25 0 25 50 75 100 125

TA, AMBIENT TEMPERATURE (C)

Figure 24. Open Loop Gain Margin versus Temperature

-55 -25 0 25 50 75 100 125

TA, AMBIENT TEMPERATURE (C)

Figure 25. Phase Margin versus Temperature


15


Am , GAIN MARGIN (dB)

12


9.0


6.0


3.0


VCC = +15 V VEE = -15 V RT = R1+R2 VO = 0 V

TA = 25C

-

60

m, PHASE MARGIN (DEGREES)

Gain Margin

Phase Margin

50


40


30


20

160


CS, CHANNEL SEPERATION (dB)

150


140


130


120


Driver Channel VCC = +15 V VEE = -15 V RL = 2.0 kQ

�VOD = 20 Vpp TA = 25C

0 R1 VO Vin +

R2

10 110


0 100

1.0 10 100 1.0 k 10 k

RT, DIFFERENTIAL SOURCE RESISTANCE (Q)

Figure 26. Phase Margin and Gain Margin versus Differential Source Resistance

100 1.0 k 10 k 100 k 1.0 M

f, FREQUENCY (Hz)

Figure 27. Channel Separation versus Frequency



THD, TOTAL HARMONIC DISTORTION (%)

1.0


0.1


0.01


0.001


AV = +1000


AV = +100


AV = +10


AV = +1.0


VO = 2.0 Vpp TA = 25C


50

|Z O |, OUTPUT IMPEDANCE ( Ω)

VCC = +15 V VEE = -15 V

40 VO = 0 V

TA = 25C

30


AV = 1000

20

AV = 100

10


VCC = +15 V VEE = -15 V

0


AV = 10 AV = 1.0

10 100 1.0 k 10 k 100 k

f, FREQUENCY (Hz)

Figure 28. Total Harmonic Distortion versus Frequency

10 k 100 k 1.0 M 10 M

f, FREQUENCY (Hz)

Figure 29. Output Impedance versus Frequency


e n , INPUT REFERRED NOISE VOLTAGE ( nV/ Hz )

i n , INPUT REFERRED NOISE CURRENT (pA/ Hz )

50 2.0

+ 1.8


Input Noise Current Circuit

40 - VO

1.6

1.4

+

RS VO

-

30


20


VCC = +15 V

10 VEE = -15 V

TA = 25C

0


Input Noise Voltage

Test Circuit

1.2

1.0

0.8

0.6

0.4

0.2

0


VCC = +15 V VEE = -15 V TA = 25C


(RS = 10 kQ)

10 100 1.0 k 10 k 100 k

f, FREQUENCY (Hz)

Figure 30. Input Referred Noise Voltage versus Frequency

10 100 1.0 k 10 k 100 k

f, FREQUENCY (Hz)

Figure 31. Input Referred Noise Current versus Frequency


60

VCC = +15 V

PERCENT OVERSHOOT (%)

50 VEE = -15 V RL = 2.0 kQ TA = 25C

40


30


20


10


0

10 100 1000

CL, LOAD CAPACITANCE (pF)

Figure 32. Percent Overshoot versus Load Capacitance



VCC = +15 V VEE = -15 V AV = +1.0 RL = 2.0 kQ TA = 25C

VCC = +15 V VEE = -15 V AV = +1.0 RL = 2.0 kQ CL = 100 pF TA = 25C

VO, OUTPUT VOLTAGE (5.0 V/DIV)

VO, OUTPUT VOLTAGE (5.0 V/DIV)

CL = 100 pF


CL =


t, TIME (2.0 µs/DIV)

Figure 33. Noninverting Amplifier Slew Rate for the MC33274

t, TIME (2.0 ns/DIV)

Figure 34. Noninverting Amplifier Overshoot for the MC33274



VCC = +15 V VEE = -15 V AV = +1.0 RL = 2.0 kQ CL = 300 pF TA = 25C

VO, OUTPUT VOLTAGE (50 mV/DIV)

VO, OUTPUT VOLTAGE (5.0 V/DIV)

VCC = +15 V

VEE = -15 V

AV = +1.0

RL = 2.0 kQ

CL = 300 pF

TA = 25C


t, TIME (2.0 µs/DIV) t, TIME (1.0 µs/DIV)

Figure 35. Small Signal Transient Response for MC33274

Figure 36. Large Signal Transient Response for MC33274


ORDERING INFORMATION

Device

Package

Shipping

MC33272AD

SOIC8


98 Units / Rail

MC33272ADG

SOIC8

(PbFree)

MC33272ADR2

SOIC8


2500 / Tape & Reel

MC33272ADR2G

SOIC8

(PbFree)

MC33272AP

PDIP8


50 Units / Rail

MC33272APG

PDIP8

(PbFree)

NCV33272ADR2*

SOIC8


2500 / Tape & Reel

NCV33272ADR2G*

SOIC8

(PbFree)

MC33274AD

SOIC14


55 Units / Rail

MC33274ADG

SOIC14

(PbFree)

MC33274ADR2

SOIC14


2500 / Tape & Reel

MC33274ADR2G

SOIC14

(PbFree)

MC33274ADTBR2G

TSSOP14

(PbFree)

MC33274AP

PDIP14


25 Units / Rail

MC33274APG

PDIP14

(PbFree)

NCV33274AD*

SOIC14


55 Units / Rail

NCV33274ADG*

SOIC14

(PbFree)

NCV33274ADR2*

SOIC14


2500 / Tape & Reel

NCV33274ADR2G*

SOIC14

(PbFree)

NCV33274ADTBR2G*

TSSOP14

(PbFree)

†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D.

*NCV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AECQ100 Qualified and PPAP Capable.



NOTE 8


D A


8

5


E1

1

4


b2 B

TOP VIEW


PDIP8 P SUFFIX

CASE 62605 ISSUE N


E

H


c

END VIEW

WITH LEADS CONSTRAINED

NOTE 5


NOTES:

  1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994.

  2. CONTROLLING DIMENSION: INCHES.

  3. DIMENSIONS A, A1 AND L ARE MEASURED WITH THE PACK- AGE SEATED IN JEDEC SEATING PLANE GAUGE GS3.

  4. DIMENSIONS D, D1 AND E1 DO NOT INCLUDE MOLD FLASH

    OR PROTRUSIONS. MOLD FLASH OR PROTRUSIONS ARE NOT TO EXCEED 0.10 INCH.

  5. DIMENSION E IS MEASURED AT A POINT 0.015 BELOW DATUM PLANE H WITH THE LEADS CONSTRAINED PERPENDICULAR TO DATUM C.

  6. DIMENSION E3 IS MEASURED AT THE LEAD TIPS WITH THE LEADS UNCONSTRAINED.

  7. DATUM PLANE H IS COINCIDENT WITH THE BOTTOM OF THE LEADS, WHERE THE LEADS EXIT THE BODY.


    DIM

    INCHES

    MILLIMETERS

    MIN

    MAX

    MIN

    MAX

    A

    −−−−

    0.210

    −−−

    5.33

    A1

    0.015

    −−−−

    0.38

    −−−

    A2

    0.115

    0.195

    2.92

    4.95

    b

    0.014

    0.022

    0.35

    0.56

    b2

    0.060 TYP

    1.52 TYP

    C

    0.008

    0.014

    0.20

    0.36

    D

    0.355

    0.400

    9.02

    10.16

    D1

    0.005

    −−−−

    0.13

    −−−

    E

    0.300

    0.325

    7.62

    8.26

    E1

    0.240

    0.280

    6.10

    7.11

    e

    0.100 BSC

    2.54 BSC

    eB

    −−−−

    0.430

    −−−

    10.92

    L

    0.115

    0.150

    2.92

    3.81

    M

    −−−−

    10

    −−−

    10

  8. PACKAGE CONTOUR IS OPTIONAL (ROUNDED OR SQUARE CORNERS).

e/2 A2

A

L


NOTE 3


SEATING

A1 PLANE

C M

D1

e eB


SIDE VIEW

8X b

END VIEW


0.010 M

C

A M

B M

NOTE 6



PDIP14 CASE 64606 ISSUE R


D A

14 8

H


E1


1 7


NOTES:

  1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994.

  2. CONTROLLING DIMENSION: INCHES.

    E

  3. DIMENSIONS A, A1 AND L ARE MEASURED WITH THE PACK- AGE SEATED IN JEDEC SEATING PLANE GAUGE GS3.

  4. DIMENSIONS D, D1 AND E1 DO NOT INCLUDE MOLD FLASH

    OR PROTRUSIONS. MOLD FLASH OR PROTRUSIONS ARE NOT TO EXCEED 0.10 INCH.

  5. DIMENSION E IS MEASURED AT A POINT 0.015 BELOW DATUM PLANE H WITH THE LEADS CONSTRAINED PERPENDICULAR TO DATUM C.

  6. DIMENSION E3 IS MEASURED AT THE LEAD TIPS WITH THE

    c LEADS UNCONSTRAINED.

    NOTE 8

    b2

    TOP VIEW

    B


    A2

    A

    NOTE 3

    L

    END VIEW

    WITH LEADS CONSTRAINED

    NOTE 5

  7. DATUM PLANE H IS COINCIDENT WITH THE BOTTOM OF THE LEADS, WHERE THE LEADS EXIT THE BODY.

  8. PACKAGE CONTOUR IS OPTIONAL (ROUNDED OR SQUARE CORNERS).



DIM

INCHES

MILLIMETERS

MIN

MAX

MIN

MAX

A

−−−−

0.210

−−−

5.33

A1

0.015

−−−−

0.38

−−−

A2

0.115

0.195

2.92

4.95

b

0.014

0.022

0.35

0.56

b2

0.060 TYP

1.52 TYP

C

0.008

0.014

0.20

0.36

D

0.735

0.775

18.67

19.69

D1

0.005

−−−−

0.13

−−−

E

0.300

0.325

7.62

8.26

E1

0.240

0.280

6.10

7.11

e

0.100 BSC

2.54 BSC

eB

−−−−

0.430

−−−

10.92

L

0.115

0.150

2.92

3.81

M

−−−−

10

−−−

10

SEATING

A1 PLANE

C M

D1

e eB


SIDE VIEW

14X b

END VIEW


0.010 M

C

A M

B M

NOTE 6



X

A



5


8

B S

1


4

Y


G


C


DIM

MILLIMETERS

INCHES

MIN

MAX

MIN

MAX

A

4.80

5.00

0.189

0.197

B

3.80

4.00

0.150

0.157

C

1.35

1.75

0.053

0.069

D

0.33

0.51

0.013

0.020

G

1.27 BSC

0.050 BSC

H

0.10

0.25

0.004

0.010

J

0.19

0.25

0.007

0.010

K

0.40°

1.27°

0.016°

0.050°

M

0

8

0

8

N

0.25

0.50

0.010

0.020

S

5.80

6.20

0.228

0.244

SEATING


SOIC8 NB CASE 75107 ISSUE AK



0.25 (0.010) M

Y M



K


N X 45°


NOTES:

  1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982.

  2. CONTROLLING DIMENSION: MILLIMETER.

  3. DIMENSION A AND B DO NOT INCLUDE MOLD PROTRUSION.

  4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE.

  5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION.

  6. 75101 THRU 75106 ARE OBSOLETE. NEW STANDARD IS 75107.

Z

PLANE


0.10 (0.004)

H D M J



0.25 (0.010)

M

Z

Y

S

X

S


SOLDERING FOOTPRINT*



1.52 0.060


7.0

0.275

4.0

0.155


0.6 0.024

1.270

( )

0.050


SCALE 6:1


mm inches

*For additional information on our PbFree strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.



SOIC14 CASE 751A03 ISSUE K


D A

B

14 8


H E


NOTES:

  1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994.

  2. CONTROLLING DIMENSION: MILLIMETERS.

  3. DIMENSION b DOES NOT INCLUDE DAMBAR

    A3 PROTRUSION. ALLOWABLE PROTRUSION SHALL BE 0.13 TOTAL IN EXCESS OF AT

    MAXIMUM MATERIAL CONDITION.

  4. DIMENSIONS D AND E DO NOT INCLUDE MOLD PROTRUSIONS.


DIM

MILLIMETERS

INCHES

MIN

MAX

MIN

MAX

A

1.35

1.75

0.054

0.068

A1

0.10

0.25

0.004

0.010

A3

0.19

0.25

0.008

0.010

b

0.35

0.49

0.014

0.019

D

8.55

8.75

0.337

0.344

E

3.80

4.00

0.150

0.157

e

1.27 BSC

0.050 BSC

H

5.80

6.20

0.228

0.244

h

0.25

0.50

0.010

0.019

L

0.40

1.25

0.016

0.049

M

0 °

7 °

0 °

7 °

L 5. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE.

1 7


0.25 M

B M

13X b


0.25 M

C

A S

B S


A

DETAIL A


h

X 45 °


DETAIL A



e A1


M

C

SEATING PLANE


SOLDERING FOOTPRINT*

6.50


1


14X

1.18


1.27

PITCH


14X

0.58


DIMENSIONS: MILLIMETERS

*For additional information on our PbFree strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.



0.15 (0.006)

U S


T

L

PIN 1 IDENT.


0.15 (0.006)

U S


14X K REF


14



1


V

2X L/2

A


TSSOP14 CASE 948G ISSUE B


U S


0.25 (0.010)

V S

T

0.10 (0.004) M

N

8

M

B

U

N

7

F DETAIL E

K K1


NOTES:

  1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982.

  2. CONTROLLING DIMENSION: MILLIMETER.

  3. DIMENSION A DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE.

  4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE.

  5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION.

  6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY.


    DIM

    MILLIMETERS

    INCHES

    MIN

    MAX

    MIN

    MAX

    A

    4.90

    5.10

    0.193

    0.200

    B

    4.30

    4.50

    0.169

    0.177

    C

    −−−

    1.20

    −−−

    0.047

    D

    0.05

    0.15

    0.002

    0.006

    F

    0.50

    0.75

    0.020

    0.030

    G

    0.65 BSC

    0.026 BSC

    H

    0.50

    0.60

    0.020

    0.024

    J

    0.09

    0.20

    0.004

    0.008

    J1

    0.09

    0.16

    0.004

    0.006

    K

    0.19

    0.30

    0.007

    0.012

    K1

    0.19

    0.25

    0.007

    0.010

    L

    6.40 BSC

    0.252 BSC

    M

    0 °

    8 °

    0 °

    8 °

  7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE W.


T

J J1


C


SECTION NN


W


0.10 (0.004)

T

D

G

SEATING PLANE

H DETAIL E

SOLDERING FOOTPRINT

7.06


1


0.65

PITCH


14X

0.36


14X

1.26


are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC owns the rights to a number of patents, trademarks,

ON Semiconductor and

DIMENSIONS: MILLIMETERS


copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/PatentMarking.pdf. SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.


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