TS921


Rail-to-rail high output current single operational amplifier


Datasheet production data


N DIP8

(plastic package)


D SO-8

(plastic micropackage)


P TSSOP8

(thin shrink small outline package)


Pin connections (top view)

Features


Table 1. Device summary


Order code

Temperature range


Package


Packing


Marking

TS921IN

-40 °C, +125 °C

DIP8

Tube

TS921IN

TS921ID/IDT


SO-8

Tube or tape and reel


921I

TS921IPT


TSSOP8

(thin shrink outline package)

Tape and reel


September 2012 Doc ID 5560 Rev 4 1/16

This is information on a product in full production. www.st.com


  1. Description


    The TS921 device is a rail-to-rail single BiCMOS operational amplifier optimized and fully specified for 3 V and 5 V operation.

    Its high output current allows low load impedances to be driven.

    The TS921 device exhibits very low noise, low distortion and low offset. It has a high output current capability which makes this device an excellent choice for high quality, low voltage or battery operated audio systems.

    The device is stable for capacitive loads up to 500 pF.


  2. Absolute maximum ratings

    Table 2. Key parameters and their absolute maximum ratings

    Symbol

    Parameter

    Condition

    Value

    Unit

    VCC

    Supply voltage(1)


    14

    V

    Vid

    Differential input voltage(2)


    ±1

    V

    Vi

    Input voltage


    VDD - 0.3 to VCC + 0.3

    V

    Tstg

    Storage temperature


    -65 to +150

    °C

    Tj

    Maximum junction temperature


    150

    °C


    Rthja


    Thermal resistance junction-to-ambient

    SO-8 TSSOP8 DIP8

    125

    120

    85


    °C/W


    Rthjc


    Thermal resistance junction-to-case

    SO-8 TSSOP8 DIP8

    40

    37

    41


    °C/W


    ESD


    Electrostatic discharge

    HBM

    Human body model(3)

    1.5

    kV

    MM

    Machine model(4)

    100

    V

    CDM

    Charged device model

    1.5

    kV


    Output short-circuit duration


    See(5)



    Latch-up immunity


    200

    mA



    Soldering temperature

    10 sec.,

    standard package

    250

    °C

    10 sec.,

    lead-free package

    260


    1. All voltage values, except differential voltage are with respect to network ground terminal.

    2. Differential voltages are the non-inverting input terminal with respect to the inverting input terminal. If Vid > ±1 V, the maximum input current must not exceed ±1 mA. In this case (Vid > ±1 V) an input serie resistor must be added to limit input current.

    3. Human body model, 100 pF discharged through a 1.5 kΩ resistor into pin of device.

    4. Machine model ESD, a 200 pF cap is charged to the specified voltage, then discharged directly into the IC with no external series resistor (internal resistor < 5 Ω), into pin to pin of device.

    5. There is no short-circuit protection inside the device: short-circuits from the output to VCC can cause excessive heating. The maximum output current is approximately 80 mA, independent of the magnitude of VCC. Destructive dissipation can result from simultaneous short-circuits on all amplifiers.


    Table 3. Operating conditions

    Symbol

    Parameter

    Value

    Unit

    VCC

    Supply voltage

    2.7 to 12

    V

    Vicm

    Common mode input voltage range

    VDD - 0.2 to VCC + 0.2

    V

    Toper

    Operating free air temperature range

    -40 to +125

    °C


    Doc ID 5560 Rev 4 3/16


  3. Electrical characteristics


    Table 4. Electrical characteristics for VCC = 3 V, VDD = 0 V, Vicm = VCC/2, RL connected to VCC/2, Tamb = 25 °C (unless otherwise specified)

    Symbol

    Parameter

    Conditions

    Min.

    Typ.

    Max.

    Unit

    Vio

    Input offset voltage


    at Tmin. Tamb Tmax



    3

    5

    mV

    ΔVio

    Input offset voltage drift



    2


    V/°C

    Iio

    Input offset current

    Vout = 1.5 V


    1

    30

    nA

    Iib

    Input bias current

    Vout = 1.5 V


    15

    100

    nA

    VOH

    High level output voltage

    RL = 600 Ω

    RL = 32 Ω

    2.87


    2.63


    V

    VOL

    Low level output voltage

    RL = 600 Ω

    RL = 32 Ω



    180

    100

    mV

    Avd

    Large signal voltage gain

    Vout = 2 Vpk-pk RL = 600 Ω RL = 32 Ω



    35

    16



    V/mV

    GBP

    Gain bandwidth product

    RL = 600 Ω


    4


    MHz

    ICC

    Supply current

    No load, Vout = VCC/2


    1

    1.5

    mA

    CMR

    Common mode rejection ratio


    60

    80


    dB

    SVR

    Supply voltage rejection ratio

    VCC = 2.7 to 3.3 V

    60

    80


    dB

    Io

    Output short-circuit current


    50

    80


    mA

    SR

    Slew rate


    0.7

    1.3


    V/s

    Pm

    Phase margin at unit gain

    RL = 600 Ω CL =100 pF


    68


    Degrees

    GM

    Gain margin

    RL = 600 Ω CL =100 pF


    12


    dB

    en

    Equivalent input noise voltage

    f = 1 kHz


    9


    ---n---V-----

    Hz

    THD

    Total harmonic distortion

    Vout = 2 Vpk-pk, f = 1 kHz, Av = 1, RL = 600 Ω


    0.005


    %


    4/16 Doc ID 5560 Rev 4


    Table 5. Electrical characteristics for VCC = 5 V, VDD = 0 V, Vicm = VCC/2, RL connected to VCC/2, Tamb = 25 °C (unless otherwise specified)

    Symbol

    Parameter

    Conditions

    Min.

    Typ.

    Max.

    Unit

    Vio

    Input offset voltage


    at Tmin. Tamb Tmax



    3

    5

    mV

    ΔVio

    Input offset voltage drift



    2


    V/°C

    Iio

    Input offset current

    Vout = 1.5 V


    1

    30

    nA

    Iib

    Input bias current

    Vout = 1.5 V


    15

    100

    nA

    VOH

    High level output voltage


    RL = 600 Ω

    RL = 32 Ω

    4.85


    4.4



    V

    VOL

    Low level output voltage

    RL = 600 Ω

    RL = 32 Ω



    300

    120


    mV

    Avd

    Large signal voltage gain

    Vout = 2 Vpk-pk RL = 600 Ω RL = 32 Ω



    35

    16



    V/mV

    GBP

    Gain bandwidth product

    RL = 600 Ω


    4


    MHz

    ICC

    Supply current

    No load, Vout = VCC/2


    1

    1.5

    mA

    CMR

    Common mode rejection ratio


    60

    80


    dB

    SVR

    Supply voltage rejection ratio

    VCC = 4.5 to 5.5 V

    60

    80


    dB

    Io

    Output short-circuit current


    50

    80


    mA

    SR

    Slew rate


    0.7

    1.3


    V/s

    Pm

    Phase margin at unit gain

    RL = 600 Ω CL =100 pF


    68


    Degrees

    GM

    Gain margin

    RL = 600 Ω CL =100 pF


    12


    dB

    en


    Equivalent input noise voltage


    f = 1 kHz



    9


    ---n---V-----

    Hz

    THD

    Total harmonic distortion

    Vout = 2 Vpk-pk, f = 1 kHz, Av = 1, RL = 600 Ω


    0.005


    %


    Doc ID 5560 Rev 4 5/16


    60

    20

    L

    Gain L

    120

    40

    Phase

    180

    60

    100


    80


    60


    40


    20


    0


    -20


    -40


    -60


    -80

    Sink

    Output short-circuit current (mA)

    Gain (dB)

    Phase (deg.)

    Figure 1. Output short-circuit vs. output voltage (VCC = 5 V, VDD = 0 V)

    Figure 2. Voltage gain and phase vs.

    frequency (RL = 10 kΩ CL = 100 pF)


    -20 -60

    1E+02 1E+03 1E+04 1E+05 1E+06 1E+07 1E+08

    Frequency (Hz)

    0

    0

    Output voltage (V)

    3

    2

    1

    0

    -100


    -120

    Source

    Figure 3. Output short-circuit vs. output voltage (VCC = 3 V, VDD = 0 V)

    Figure 4. Equivalent input noise voltage vs. frequency (VCC = ±1.5 V, RL = 100 Ω)


    Output short-circuit current (mA)

    Equivalent input noise (nV/sqrt(Hz)

    100 30


    80

    25

    60 Sink

    40 20

    20


    0 15


    -20

    -40 10


    -60


    -80

    Source 5

    -100

    0 0,5 1 1,5 2 2,5 3

    Output voltage (V)


    0

    0.01 0.1 1 10 100

    Frequency (kHz)


    Figure 5. Output supply current vs. supply voltage

    Figure 6. THD + noise vs. frequency (RL = 2 kΩ Vo = 10 Vpp, VCC = ±6 V, Av = 1)



    0.02



    THD + noise (%)

    0.015



    0.01



    0.005



    0

    0.01 0.1 1 10 100

    Frequency (kHz)


    6/16 Doc ID 5560 Rev 4


    Figure 7. THD + noise vs. frequency

    THD + noise (%)

    THD + noise (%)

    (RL = 32 Ω Vo = 4 Vpp, VCC = ±2.5 V, Av = 1)

    Figure 8. THD + noise vs. output voltage (RL = 600 Ω f = 1 kHz,

    VCC = 0/3 V, Av = -1)


    0.04






    10








    0.032


















    1







    0.024













    0.016

















    0.1








    0.008













    0






    0.01







    0.01

    0.1

    1

    10

    100


    0

    0.2

    0.4

    0.6

    0.8

    1



    Frequency (kHz)











    Figure 9. THD + noise vs. frequency

    THD + noise (%)

    THD + noise (%)

    (RL = 32 Ω Vo = 2 Vpp, VCC = ±1.5 V, Av = 10)

    Figure 10. THD + noise vs. output voltage (RL = 32 Ω f = 1 kHz,

    VCC = ±1.5 V, Av = -1)







    10








    0.7














    0.6


















    1








    0.5














    0.4


















    0.1








    0.3














    0.2


















    0.01








    0.1














    0













    0.01

    0.1

    1

    10

    100

    0.001










    Frequency (kHz)




    0

    0.2

    0.4

    0.6

    0.8

    1

    1.2


    Figure 11. THD + noise vs. output voltage (RL = 2 kΩ, f = 1 kHz,

    60

    30


    20

    120

    40

    180

    50

    0,100

    1,000

    10,000

    THD + noise (%)

    Gain (dB)

    Phase (deg.)

    VCC = ±1.5 V, Av = -1)

    Figure 12. Open loop gain and phase

    vs. frequency (CL = 500 pF)












































































































































































































    0,001

    1E+2

    1E+3

    1E+4

    1E+5

    Frequency (Hz)

    1E+7

    1E+8


    1E+6

    0

    0

    10

    1,2

    1

    0,8

    0,6

    0,4

    0,2

    0

    0,010

    Doc ID 5560 Rev 4 7/16


  4. Macromodel


    1. Important note concerning this macromodel

      Please consider following remarks before using this macromodel:

      • All models are a trade-off between accuracy and complexity (i.e. simulation time).

      • Macromodels are not a substitute to breadboarding; rather, they confirm the validity of a design approach and help to select surrounding component values.

      • A macromodel emulates the NOMINAL performance of a TYPICAL device within SPECIFIED OPERATING CONDITIONS (i.e. temperature, supply voltage, etc.). Thus the macromodel is often not as exhaustive as the datasheet, its goal is to illustrate the main parameters of the product.

      • Data issued from macromodels used outside of its specified conditions

        (VCC, temperature, etc.) or even worse: outside of the device operating conditions (VCC, Vicm, etc.) are not reliable in any way.

        In Section 4.3, the electrical characteristics resulting from the use of these macromodels are presented.


    2. Electrical characteristics from macromodelization

      Table 6. Electrical characteristics resulting from macromodel simulation at VCC = 3 V, VDD = 0 V, RL, CL connected to VCC/2, Tamb = 25 °C (unless otherwise specified)

      Symbol

      Conditions

      Value

      Unit

      Vio


      0

      mV

      Avd

      RL = 10 kΩ

      200

      V/mV

      ICC

      No load, per operator

      1.2

      mA

      Vicm


      -0.2 to 3.2

      V

      VOH

      RL = 10 kΩ

      2.95

      V

      VOL

      RL = 10 kΩ

      25

      mV

      Isink

      VO = 3 V

      80

      mA

      Isource

      VO = 0 V

      80

      mA

      GBP

      RL = 600 kΩ

      4

      MHz

      SR

      RL = 10 kΩ, CL = 100 pF

      1.3

      V/s

      m

      RL = 600 kΩ

      68

      Degrees


      8/16 Doc ID 5560 Rev 4


    3. Macromodel code

      ** Standard Linear Ics Macromodels, 1996.

      ** CONNECTIONS:

      • 1 INVERTING INPUT

      • 2 NON-INVERTING INPUT

      • 3 OUTPUT

      • 4 POSITIVE POWER SUPPLY

      • 5 NEGATIVE POWER SUPPLY

        .SUBCKT TS921 1 3 2 4 5 (analog)

        ********************************************************* .MODEL MDTH D IS=1E-8 KF=2.664234E-16 CJO=10F

      • INPUT STAGE

        CIP 2 5 1.000000E-12

        CIN 1 5 1.000000E-12

        EIP 10 5 2 5 1

        EIN 16 5 1 5 1

        RIP 10 11 8.125000E+00

        RIN 15 16 8.125000E+00

        RIS 11 15 2.238465E+02

        DIP 11 12 MDTH 400E-12

        DIN 15 14 MDTH 400E-12

        VOFP 12 13 DC 153.5u

        VOFN 13 14 DC 0

        IPOL 13 5 3.200000E-05

        CPS 11 15 1e-9

        DINN 17 13 MDTH 400E-12

        VIN 17 5 -0.100000e+00

        DINR 15 18 MDTH 400E-12

        VIP 4 18 0.400000E+00

        FCP 4 5 VOFP 1.865000E+02

        FCN 5 4 VOFN 1.865000E+02

        FIBP 2 5 VOFP 6.250000E-03

        FIBN 5 1 VOFN 6.250000E-03

        * GM1 STAGE *************** FGM1P 119 5 VOFP 1.1

        FGM1N 119 5 VOFN 1.1

        RAP 119 4 2.6E+06

        RAN 119 5 2.6E+06

        * GM2 STAGE ***************


        G2P

        19

        5

        119 5 1.92E-02

        G2N

        19

        5

        119 4 1.92E-02

        R2P

        19

        4

        1E+07

        R2N

        19

        5

        1E+07

        ************************** VINT1 500 0 5


        Doc ID 5560 Rev 4 9/16


        GCONVP 500 501 119 4 19.38!send ds VP, I(VP)=(V119-V4)/2/Ut VP 501 0 0

        GCONVN 500 502 119 5 19.38!send ds VN, I(VN)=(V119-V5)/2/Ut VN 502 0 0

        ********* orientation isink isource ******* VINT2 503 0 5

        FCOPY 503 504 VOUT 1


        DCOPYP

        504

        505 MDTH 400E-9

        VCOPYP

        505

        0 0

        DCOPYN

        506

        504 MDTH 400E-9

        VCOPYN 0 506 0



        ***************************



        F2PP 19 5 poly(2) VCOPYP VP

        V4)/2/Ut

        0 0 0 0

        0.5!multiply I(vout)*I(VP)=Iout*(V119-

        F2PN 19 5 poly(2) VCOPYP VN

        V5)/2/Ut

        0 0 0 0

        0.5 !multiply I(vout)*I(VN)=Iout*(V119-

        F2NP 19 5 poly(2) VCOPYN VP 0 0 0 0 1.75 !multiply I(vout)*I(VP)=Iout*(V119- V4)/2/Ut

        F2NN 19 5 poly(2) VCOPYN VN 0 0 0 0 1.75 !multiply I(vout)*I(VN)=Iout*(V119- V5)/2/Ut

      • COMPENSATION ************ CC 19 119 25p

      * OUTPUT***********


      DOPM

      19

      22 MDTH 400E-12

      DONM

      21

      19 MDTH 400E-12

      HOPM

      22

      28 VOUT 6.250000E+02

      VIPM

      28

      4 5.000000E+01

      HONM

      21

      27 VOUT 6.250000E+02

      VINM

      5

      27 5.000000E+01

      VOUT

      3

      23 0

      ROUT

      23

      19 6

      COUT

      3

      5 1.300000E-10

      DOP

      19

      25 MDTH 400E-12

      VOP 4 25 1.052

      DON 24 19 MDTH 400E-12

      VON 24 5 1.052

      .ENDS


      10/16 Doc ID 5560 Rev 4


  5. Package information


    In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK

    specifications, grade definitions and product status are available at: www.st.com. ECOPACK is an ST trademark.



    Doc ID 5560 Rev 4 11/16


    Figure 13. DIP8 package outline


    Table 7. DIP8 package mechanical data


    Symbol

    Dimensions

    mm

    inch

    Min.

    Typ.

    Max.

    Min.

    Typ.

    Max.

    A


    3.3



    0.130


    a1

    0.7



    0.028



    B

    1.39


    1.65

    0.055


    0.065

    B1

    0.91


    1.04

    0.036


    0.041

    b


    0.5



    0.020


    b1

    0.38


    0.5

    0.015


    0.020

    D



    9.8



    0.386

    E


    8.8



    0.346


    e


    2.54



    0.100


    e3


    7.62



    0.300


    e4


    7.62



    0.300


    F



    7.1



    0.280

    I



    4.8



    0.189

    L


    3.3



    0.130


    Z

    0.44


    1.6

    0.017


    0.063


    12/16 Doc ID 5560 Rev 4


    Figure 14. SO-8 package outline


    00160 23/C


    Table 8. SO-8 package mechanical data


    Symbol

    Dimensions

    mm

    inch

    Min.

    Typ.

    Max.

    Min.

    Typ.

    Max.

    A

    1.35


    1.75

    0.053


    0.069

    A1

    0.10


    0.25

    0.04


    0.010

    A2

    1.10


    1.65

    0.043


    0.065

    B

    0.33


    0.51

    0.013


    0.020

    C

    0.19


    0.25

    0.007


    0.010

    D

    4.80


    5.00

    0.189


    0.197

    E

    3.80


    4.00

    0.150


    0.157

    e


    1.27



    0.050


    H

    5.80


    6.20

    0.228


    0.244

    h

    0.25


    0.50

    0.010


    0.020

    L

    0.40


    1.27

    0.016


    0.050

    k

    8° (max.)

    ddd



    0.1



    0.04


    Doc ID 5560 Rev 4 13/16


    Figure 15. TSSOP8 package outline


    0079397/D

    Table 9. TSSOP8 package mechanical data


    Symbol

    Dimensions

    mm

    inch

    Min.

    Typ.

    Max.

    Min.

    Typ.

    Max.

    A



    1.2



    0.047

    A1

    0.05


    0.15

    0.002


    0.006

    A2

    0.80

    1.00

    1.05

    0.031

    0.039

    0.041

    b

    0.19


    0.30

    0.007


    0.012

    c

    0.09


    0.20

    0.004


    0.008

    D

    2.90

    3.00

    3.10

    0.114

    0.118

    0.122

    E

    6.20

    6.40

    6.60

    0.244

    0.252

    0.260

    E1

    4.30

    4.40

    4.50

    0.169

    0.173

    0.177

    e


    0.65



    0.0256


    K



    L

    0.45

    0.60

    0.75

    0.018

    0.024

    0.030

    L1


    1



    0.039



    14/16 Doc ID 5560 Rev 4


  6. Revision history


Table 10. Document revision history

Date

Revision

Changes

Feb. 2001

1

Initial release - Product in full production.

Dec. 2004

2

Modifications on AMR table page 2 (explanation of Vid and Vi limits, ESD, MM and CDM values added, Rthja added)


Nov. 2005


3

The following changes were made in this revision: PPAP references inserted in the datasheet see Table 1.

Data in tables Electrical characteristics on page 4 reformatted for easier use.

Thermal Resistance Junction to Case added in Table 2 on page 3.


19-Sep-2012


4

Updated Figure on page 1(replaced VCC- by VDD).

Updated (renamed) Table 1, removed TS921IYD/IYDT devices from

Table 1.

Moved Description to page 2.

Updated Figure 1 to Figure 4, Figure 6 to Figure 12 (added conditions to titles).

Updated ECOPACK text and reformatted Section 5 (added Table 7 to

Table 9, reversed order of figures and tables).

Minor corrections throughout document.


Doc ID 5560 Rev 4 15/16


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16/16 Doc ID 5560 Rev 4

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