30 V, Low Noise, Rail-to-Rail Input/Output, Low Power Operational Amplifiers

Data Sheet

ADA4084-1/ADA4084-2/ADA4084-4


FEATURES

Rail-to-rail input/output

PIN CONNECTION DIAGRAM

ADA4084-2

Low power: 0.625 mA typical per amplifier at ±15 V Gain bandwidth product: 15.9 MHz at AV = 100 typical Unity-gain crossover: 9.9 MHz typical

−3 dB closed-loop bandwidth: 13.9 MHz typical at ±15 V Low offset voltage: 100 µV maximum (SOIC)

OUT A 1

–IN A 2

+IN A 3

V– 4


08237-001

NOTES

8 V+

7 OUT B

6 –IN B

5 +IN B

Unity-gain stable

High slew rate: 4.6 V/µs typical

Low noise: 3.9 nV/√Hz typical at 1 kHz

Long-term offset voltage drift (10,000 hours): 3 µV typical Temperature hysteresis: 4 µV typical

APPLICATIONS

Battery-powered instrumentation High-side and low-side sensing Power supply control and protection Telecommunications

Digital-to-analog converter (DAC) output amplifiers Analog-to-digital converter (ADC) input buffers

GENERAL DESCRIPTION

The ADA4084-1 (single), ADA4084-2 (dual), and ADA4084-4 (quad) are single-supply, 10 MHz bandwidth amplifiers featuring rail-to-rail inputs and outputs. They are guaranteed to operate from +3 V to +30 V (or ±1.5 V to ±15 V).

These amplifiers are well suited for single-supply applications requiring both ac and precision dc performance. The combination of wide bandwidth, low noise, and precision makes the ADA4084-1/ADA4084-2/ADA4084-4 useful in a wide variety of applications, including filters and instrumentation.

Other applications for these amplifiers include portable telecom- munications equipment, power supply control and protection, and use as amplifiers or buffers for transducers with wide output ranges. Sensors requiring a rail-to-rail input amplifier include Hall effect, piezoelectric, and resistive transducers.

The ability to swing rail to rail at both the input and output enables designers to build multistage filters in single-supply systems and to maintain high signal-to-noise ratios.

The ADA4084-1/ADA4084-2/ADA4084-4 are specified over the industrial temperature range of −40°C to +125°C.

  1. FOR THE LFCSP PACKAGE,

    THE EXPOSED PAD MUST BE CONNECTED TO V–.

    Figure 1. ADA4084-2, 8-Lead LFCSP (CP); for Additional Packages and Models, See the Pin Configurations and Function Descriptions Section


    The single ADA4084-1 is available in the 5-lead SOT-23 and 8-lead SOIC; the dual ADA4084-2 is available in the 8-lead SOIC, 8-lead MSOP, and 8-lead LFCSP surface-mount

    packages; and the ADA4084-4 is offered in the 14-lead TSSOP and 16-lead LFCSP.

    The ADA4084-1/ADA4084-2/ADA4084-4 are members of a growing series of high voltage, low noise op amps offered by Analog Devices, Inc. (see Table 1).

    Table 1. Low Noise Op Amps

    Single

    Dual

    Quad

    Voltage Noise

    AD8597

    AD8599


    1.1 nV/Hz

    ADA4004-1

    ADA4004-2

    ADA4004-4

    1.8 nV/Hz

    AD8675

    AD8676


    2.8 nV/Hz rail-to-rail output

    AD8671

    AD8672

    AD8674

    2.8 nV/Hz

    OP27, OP37



    3.2 nV/Hz

    ADA4084-1

    ADA4084-2

    ADA4084-4

    3.9 nV/Hz rail-to-rail input/output



    Rev. I Document Feedback

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    TABLE OF CONTENTS

    Features 1

    Applications 1

    Pin Connection Diagram 1

    General Description 1

    Revision History 2

    Specifications 4

    Electrical Characteristics 4

    Absolute Maximum Ratings 7

    Thermal Resistance 7

    ESD Caution 7

    Pin Configurations and Function Descriptions 8

    Typical Performance Characteristics 11

    ±1.5 V Characteristics 11

    ±5 V Characteristics 17

    ±15 V Characteristics 23

    Applications Information 29

    Functional Description 29

    Start-Up Characteristics 30

    Input Protection 30

    Output Phase Reversal 30

    Designing Low Noise Circuits in Single-Supply Applications .. 31 Comparator Operation 31

    Long-Term Drift 32

    Temperature Hysteresis 32

    Outline Dimensions 33

    Ordering Guide 36


    REVISION HISTORY

    5/2017—Rev. H to Rev. I

    Changed CP-8-12 to CP-8-11 ...................................... Throughout

    Changed CP-16-26 to CP-16-17 .................................. Throughout Changes to Features Section 1

    Added Long-Term Drift Section, Temperature Hysteresis Section, Figure 112, Figure 113, and Figure 114; Renumbered

    Sequentially 32

    Updated Outline Dimensions 34

    Changes to Ordering Guide 36


    8/2015—Rev. G to Rev. H

    Added 5-Lead SOT-23 .......................................................Universal

    Changes to Pin Connection Diagram Section, Figure 1, and General Description Section 1

    Deleted Figure 3; Renumbered Sequentially 1

    Changes to Large Signal Voltage Gain Parameter, Table 2 4

    Changes to Large Signal Voltage Gain Parameter, Table 3 5

    Changes to Large Signal Voltage Gain Parameter, Table 4 6

    Changes to Table 6 7

    Moved Figure 3 8

    Added Pin Configurations and Function Descriptions Section, Figure 4, Figure 5, Table 7, Table 8, and Table 9; Renumbered

    Sequentially 8

    Added Figure 6, Figure 7, Figure 8, Table 10, and Table 11 9

    Moved Figure 9 10

    Added Table 12 10

    Added Figure 11 and Figure 15 11

    Added Figure 42 and Figure 46 17

    Added Figure 73 and Figure 77 23

    Updated Outline Dimensions 32

    Changes to Ordering Guide 35


    6/2015—Rev. F to Rev. G

    Changes to Figure 96 and Figure 97 24

    1/2015—Rev. E to Rev. F

    Moved Revision History 3

    Changes to Table 5 7

    Changes to Ordering Guide 29

    7/2014—Rev. D to Rev. E

    Added ADA4084-1.............................................................Universal

    Added Figure 1; Renumbered Sequentially 1

    Changes to Output Voltage High Parameter, Table 2 3

    Changes to Current Noise Density Parameter, Table 3 4

    Changes to Current Noise Density Parameter, Table 4 5

    Changes to Figure 8 Caption, and Figure 9 to Figure 11 7

    Changes to Figure 13 8

    Changes to Figure 21 9

    Added Figure 31; Renumbered Sequentially 11

    Changes to Figure 30 Caption, and Figure 32 to Figure 34 11

    Changes to Figure 36 Caption to Figure 39 Caption 12

    Changes to Figure 50 14

    Added Figure 60 16

    Changes to Figure 59 Caption, Figure 62, and Figure 63 16

    Changes to Figure 65 Caption to Figure 68 Caption 17

    Changes to Figure 79 19

    Added Figure 89 21

    Changes to Figure 88 Caption, Figure 91 Caption, and

    Figure 92 Caption 21

    Changes to Ordering Guide 28

    11/2013—Rev. C to Rev. D

    Added 14-Lead TSSOP and 16-Lead LFCSP Packages.......Universal Added ADA4084-4.....................................................................Universal

    Change to Features Section and Applications Section 1

    Added Figure 2 and Figure 3; Renumbered Sequentially 1

    Changes to Table 2 3

    Changes to Table 3 4

    Changes to Table 4 5

    Changes to Table 5 and Table 6 6

    Changes to Typical Performance Characteristics Section 7

    Updated Outline Dimensions 27

    Changes to Ordering Guide 28


    4/2013—Rev. B to Rev. C

    Changes to Figure 48 Caption 15

    Updated Outline Dimensions 25


    6/2012—Rev. A to Rev. B

    Added LFCSP Package....................................................... Universal

    Changes to Figure 1 1

    Changes to Output Voltage High Parameter, Table 4 5

    Added Figure 5 and Figure 7, Renumbered Sequentially 7

    Added Figure 30 and Figure 32 12

    Added Figure 55 and Figure 57 17

    Added Startup Characteristics Section 23

    Moved Figure 78 23

    Changes to Output Phase Reversal Section and Comparator Operation Section 24

    Updated Outline Dimensions 25

    Changes to Ordering Guide 26

    2/2012—Rev. 0 to Rev. A

    Changes to Data Sheet Title 1

    Changes to Voltage Range in General Description 1

    Changes to Supply Current/Amplifier Parameter, Table 2 3

    Changes to Common-Mode Rejection Ratio Parameter, Table 3.. 4 Changes to Common-Mode Rejection Ratio Parameter, Table 4.. 5 Changes to Figure 2 6

    Changes to Figure 24 10

    Changes to Figure 32 12

    Changes to Figure 47 14

    Changes to Figure 55 16

    Changes to Figure 62 17

    Changes to Figure 73 20

    10/2011—Revision 0: Initial Version

    SPECIFICATIONS

    ELECTRICAL CHARACTERISTICS

    VSY = 3 V, VCM = 1.5 V, TA = 25°C, unless otherwise noted.

    Table 2.

    Parameter

    Symbol

    Test Conditions/Comments

    Min

    Typ

    Max

    Unit

    INPUT CHARACTERISTICS

    Offset Voltage


    Offset Voltage Drift Offset Voltage Matching

    Input Bias Current Input Offset Current Input Voltage Range

    Common-Mode Rejection Ratio

    Large Signal Voltage Gain Input Impedance

    Differential Common Mode


    VOS


    SOIC package



    20


    100


    µV


    −40°C ≤ TA ≤ +125°C



    200

    µV


    SOT-23, MSOP, TSSOP packages


    50

    130

    µV


    −40°C ≤ TA ≤ +125°C



    250

    µV


    ADA4084-2 LFCSP package


    80

    200

    µV


    −40°C ≤ TA ≤ +125°C



    300

    µV

    Δt/ΔT

    −40°C ≤ TA ≤ +125°C


    0.5

    1.75

    µV/°C


    TA = 25°C



    150

    µV


    ADA4084-4 LFCSP package



    200

    µV

    IB



    140

    250

    nA


    −40°C ≤ TA ≤ +125°C



    400

    nA

    IOS



    5

    25

    nA


    −40°C ≤ TA ≤ +125°C



    50

    nA



    0


    3

    V

    CMRR

    VCM = 0 V to 3 V

    64

    88


    dB


    −40°C ≤ TA ≤ +125°C

    60



    dB

    AVO

    RL = 2 kΩ, 0.5 V ≤ VOUT ≤ 2.5 V

    100

    104


    dB


    −40°C ≤ TA ≤ +125°C

    97



    dB




    100||1.1


    kΩ||pF




    80||2.9


    MΩ||pF

    OUTPUT CHARACTERISTICS







    Output Voltage High

    VOH

    RL = 10 kΩ to VCM

    2.90

    2.95


    V



    −40°C ≤ TA ≤ +125°C

    2.80



    V



    RL = 2 kΩ to VCM

    2.85

    2.9


    V



    −40°C ≤ TA ≤ +125°C

    2.70



    V

    Output Voltage Low

    VOL

    RL = 10 kΩ to VCM


    10

    20

    mV



    −40°C ≤ TA ≤ +125°C



    40

    mV



    RL = 2 kΩ to VCM


    20

    30

    mV



    −40°C ≤ TA ≤ +125°C



    50

    mV

    Short-Circuit Current

    ISC



    −17/+10


    mA

    Closed-Loop Output Impedance

    ZOUT

    f = 1 kHz, AV = 1


    0.1


    POWER SUPPLY

    Power Supply Rejection Ratio


    Supply Current per Amplifier

    PSRR ISY


    VSY = ±1.25 V to ±1.75 V

    −40°C ≤ TA ≤ +125°C IOUT = 0 mA

    −40°C ≤ TA ≤ +125°C


    100

    90


    110


    0.565


    0.650

    0.950


    dB dB mA

    mA

    DYNAMIC PERFORMANCE







    Slew Rate

    SR

    RL = 2 kΩ

    2.0

    2.6


    V/µs

    Gain Bandwidth Product

    GBP

    VIN = 5 mV p-p, RL = 10 kΩ, AV = 100


    15.4


    MHz

    Unity-Gain Crossover

    UGC

    VIN = 5 mV p-p, RL = 10 kΩ, AV = 1


    8.08


    MHz

    Phase Margin

    ΦM



    86


    Degrees

    −3 dB Closed-Loop Bandwidth

    −3 dB

    AV = 1, VIN = 5 mV p-p


    12.3


    MHz

    Settling Time

    tS

    AV = 10, VIN = 2 V p-p, 0.1%


    4


    µs

    Total Harmonic Distortion Plus Noise

    THD + N

    VIN = 300 mV rms, RL = 2 kΩ, f = 1 kHz


    0.009


    %

    NOISE PERFORMANCE





    Voltage Noise

    en p-p

    0.1 Hz to 10 Hz

    0.14

    µV p-p

    Voltage Noise Density

    en

    f = 1 kHz

    3.9

    nV/√Hz

    Current Noise Density

    in

    f = 1 kHz

    0.55

    pA/√Hz

    VSY = ±5.0 V, VCM = 0 V, TA = 25°C, unless otherwise noted.

    Table 3.

    Parameter

    Symbol

    Test Conditions/Comments

    Min

    Typ

    Max

    Unit

    INPUT CHARACTERISTICS

    Offset Voltage


    Offset Voltage Drift Offset Voltage Matching

    Input Bias Current Input Offset Current Input Voltage Range

    Common-Mode Rejection Ratio


    Large Signal Voltage Gain Input Impedance

    Differential Common Mode


    VOS


    SOIC package



    30


    100


    µV


    −40°C ≤ TA ≤ +125°C



    200

    µV


    SOT-23, MSOP, TSSOP packages


    60

    130

    µV


    −40°C ≤ TA ≤ +125°C



    250

    µV


    ADA4084-2 LFCSP package


    90

    200

    µV


    −40°C ≤ TA ≤ +125°C



    300

    µV

    ΔVOS/ΔT

    −40°C ≤ TA ≤ +125°C


    0.5

    1.75

    µV/°C


    TA = 25°C



    150

    µV


    ADA4084-4 LFCSP package



    200

    µV

    IB



    140

    250

    nA


    −40°C ≤ TA ≤ +125°C



    400

    nA

    IOS



    5

    25

    nA


    −40°C ≤ TA ≤ +125°C



    50

    nA



    −5


    +5

    V

    CMRR

    VCM = ±4 V, −40°C ≤ TA ≤ +125°C

    106

    124


    dB


    VCM = ±5 V

    76



    dB


    VCM = ±5 V, −40°C ≤ TA ≤ +125°C

    70



    dB

    AVO

    RL = 2 kΩ, −4 V ≤ VOUT ≤ 4 V

    108

    112


    dB


    −40°C ≤ TA ≤ +125°C

    103



    dB




    100||1.1


    kΩ||pF




    200||2.5


    MΩ||pF

    OUTPUT CHARACTERISTICS







    Output Voltage High

    VOH

    RL = 10 kΩ to VCM

    4.9

    4.95


    V



    −40°C ≤ TA ≤ +125°C

    4.8



    V



    RL = 2 kΩ to VCM

    4.8

    4.85


    V



    −40°C ≤ TA ≤ +125°C

    4.7



    V

    Output Voltage Low

    VOL

    RL = 10 kΩ to VCM


    −4.95

    −4.9

    V



    −40°C ≤ TA ≤ +125°C



    −4.8

    V



    RL = 2 kΩ to VCM


    −4.95

    −4.8

    V



    −40°C ≤ TA ≤ +125°C



    −4.7

    V

    Short-Circuit Current

    ISC



    −24/+17


    mA

    Closed-Loop Output Impedance

    ZOUT

    f = 1 kHz, AV = 1


    0.1


    POWER SUPPLY

    Power Supply Rejection Ratio


    Supply Current per Amplifier

    PSRR ISY


    VSY = ±2 V to ±18 V

    −40°C ≤ TA ≤ +125°C IOUT = 0 mA

    −40°C ≤ TA ≤ +125°C


    110

    105


    120


    0.595


    0.700

    1.00


    dB dB mA

    mA

    DYNAMIC PERFORMANCE







    Slew Rate

    SR

    RL = 2 kΩ to VCM

    2.4

    3.7


    V/µs

    Gain Bandwidth Product

    GBP

    VIN = 5 mV p-p, RL = 10 kΩ, AV = 100


    15.9


    MHz

    Unity-Gain Crossover

    UGC

    VIN = 5 mV p-p, RL = 10 kΩ, AV = 1


    9.6


    MHz

    Phase Margin

    ΦM



    85


    Degrees

    −3 dB Closed-Loop Bandwidth

    −3 dB

    AV = 1, VIN = 5 mV p-p


    13.9


    MHz

    Settling Time

    tS

    AV = 10, VIN = 8 V p-p, 0.1%


    4


    µs

    Total Harmonic Distortion Plus Noise

    THD + N

    VIN = 2 V rms, RL = 2 kΩ, f = 1 kHz


    0.003


    %

    NOISE PERFORMANCE





    Voltage Noise

    en p-p

    0.1 Hz to 10 Hz

    0.14

    µV p-p

    Voltage Noise Density

    en

    f = 1 kHz

    3.9

    nV/√Hz

    Current Noise Density

    in

    f = 1 kHz

    0.55

    pA/√Hz


    VSY = ±15.0 V, VCM = 0 V, TA = 25°C, unless otherwise noted.

    Table 4.

    Parameter

    Symbol

    Test Conditions/Comments

    Min

    Typ

    Max

    Unit

    INPUT CHARACTERISTICS

    Offset Voltage


    Offset Voltage Drift Offset Voltage Matching

    Input Bias Current Input Offset Current Input Voltage Range

    Common-Mode Rejection Ratio


    Large Signal Voltage Gain Input Impedance

    Differential Common Mode


    VOS


    SOIC package



    40


    100


    µV


    −40°C ≤ TA ≤ +125°C



    200

    µV


    SOT-23, MSOP, TSSOP packages


    70

    130

    µV


    −40°C ≤ TA ≤ +125°C



    250

    µV


    ADA4084-2 LFCSP package


    100

    200

    µV


    −40°C ≤ TA ≤ +125°C



    300

    µV

    ΔVOS/ΔT



    0.5

    1.75

    µV/°C


    TA = 25°C



    150

    µV


    ADA4084-4 LFCSP package



    200

    µV

    IB



    140

    250

    nA


    −40°C ≤ TA ≤ +125°C



    400

    nA

    IOS



    5

    25

    nA


    −40°C ≤ TA ≤ +125°C



    50

    nA



    −15


    +15

    V

    CMRR

    VCM = ±14 V, −40°C ≤ TA ≤ +125°C

    106

    124


    dB


    VCM = ±15 V

    85



    dB


    VCM = ±15 V, −40°C ≤ TA ≤ +125°C

    80



    dB

    AVO

    RL = 2 kΩ, −13.5 V ≤ VOUT ≤ +13.5 V

    110

    117


    dB


    −40°C ≤ TA ≤ +125°C

    105



    dB




    100||1.1


    kΩ||pF




    200||2.5


    MΩ||pF

    OUTPUT CHARACTERISTICS







    Output Voltage High

    VOH

    RL = 10 kΩ to VCM

    14.85

    14.9


    V



    −40°C ≤ TA ≤ +125°C

    14.8



    V



    RL = 2 kΩ to VCM

    14.5

    14.6


    V



    −40°C ≤ TA ≤ +125°C

    14.0



    V

    Output Voltage Low

    VOL

    RL = 10 kΩ to VCM


    −14.95

    −14.9

    V



    −40°C ≤ TA ≤ +125°C



    −14.8

    V



    RL = 2 kΩ to VCM


    −14.9

    −14.8

    V



    −40°C ≤ TA ≤ +125°C



    −14.7

    V

    Short-Circuit Current

    ISC



    ±30


    mA

    Closed-Loop Output Impedance

    ZOUT

    f = 1 kHz, AV = +1


    0.1


    POWER SUPPLY

    Power Supply Rejection Ratio


    Supply Current per Amplifier

    PSRR ISY


    VSY = ±2 V to ±18 V

    −40°C ≤ TA ≤ +125°C IOUT = 0 mA

    −40°C ≤ TA ≤ +125°C


    110

    105


    120


    0.625


    0.750

    1.050


    dB dB mA

    mA

    DYNAMIC PERFORMANCE







    Slew Rate

    SR

    RL = 2 kΩ

    2.4

    4.6


    V/µs

    Gain Bandwidth Product

    GBP

    VIN = 5 mV p-p, RL = 10 kΩ, AV = 100


    15.9


    MHz

    Unity-Gain Crossover

    UGC

    VIN = 5 mV p-p, RL = 10 kΩ, AV = 1


    9.9


    MHz

    Phase Margin

    ΦM



    86


    Degrees

    −3 dB Closed-Loop Bandwidth

    −3 dB

    AV = 1, VIN = 5 mV p-p


    13.9


    MHz

    Settling Time

    tS

    AV = 10, VIN = 10 V p-p, 0.1%


    4


    µs

    Total Harmonic Distortion Plus Noise

    THD + N

    VIN = 5 V rms, RL = 2 kΩ, f = 1 kHz


    0.003


    %

    NOISE PERFORMANCE





    Voltage Noise

    en p-p

    0.1 Hz to 10 Hz

    0.1

    µV p-p

    Voltage Noise Density

    en

    f = 1 kHz

    3.9

    nV/√Hz

    Current Noise Density

    in

    f = 1 kHz

    0.55

    pA/√Hz


    ABSOLUTE MAXIMUM RATINGS

    Table 5.

    Parameter

    Rating

    Supply Voltage Input Voltage

    Differential Input Voltage1

    Output Short-Circuit Duration to GND Storage Temperature Range Operating Temperature Range Junction Temperature Range

    Lead Temperature (Soldering 60 sec) ESD

    Human Body Model2 Machine Model3

    Field-Induced Charged-Device Model (FICDM)4

    ±18 V

    V− ≤ VIN ≤ V+

    ±0.6 V

    Indefinite

    −65°C to +150°C

    −40°C to +125°C

    −65°C to +150°C 300°C


    4.5 kV 200 V

    1.25 kV

    1 For input differential voltages greater than 0.6 V, limit the input current to less than 5 mA to prevent degradation or destruction of the input devices.

    2 Applicable standard: MIL-STD-883, Method 3015.7.

    3 Applicable standard: JESD22-A115-A (ESD machine model standard of JEDEC).

    4 Applicable standard: JESD22-C101-C (ESD FICDM standard of JEDEC).

    Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability.


    THERMAL RESISTANCE

    θJA is specified for the device soldered on a 4-layer JEDEC standard printed circuit board (PCB) with zero airflow.

    Table 6. Thermal Resistance

    Package Type

    θJA

    θJC

    Unit

    5-Lead SOT-23 (RJ-5)

    219.4

    155.6

    °C/W

    8-Lead SOIC_N (R-8)

    121

    43

    °C/W

    8-Lead MSOP (RM-8)

    142

    45

    °C/W

    8-Lead LFCSP (CP-8-11)1, 3

    84

    40

    °C/W

    14-Lead TSSOP (RU-14)

    112

    43

    °C/W

    16-Lead LFCSP (CP-16-17)2, 3

    55

    30

    °C/W

    1 Values are based on 4-layer (2S2P) JEDEC standard PCB, with four thermal vias. Exposed pad soldered to PCB.

    2 Values are based on 4-layer (2S2P) JEDEC standard PCB, with nine thermal vias. Exposed pad soldered to PCB.

    3 θJC measured on top of package.


    ESD CAUTION



    VCC


    R4 R3


    R6

    Q24


    Q23



    D2 Q1


    D1

    Q2

    D100


    MIRROR



    Q4 D101 Q3


    FOLDED CASCADE


    VOUT



    D5 D4


    Q13


    R5


    VBIAS C1


    Q18

    R7 C2


    Q19


    R1 R2


    Q21


    D20


    VEE


    08237-002

    Figure 2. Simplified Schematic


    7

    8


    ADA4084-1

    TOP VIEW

    (Not to Scale)

    1

    08237-101

    PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS


    NIC

    2

    –IN

    4

    3

    +IN V–


    NIC V+ OUT NIC

    5

    6

    NOTES

    1. NIC = NOT INTERNALLY CONNECTED.

Figure 3. ADA4084-1, 8-Lead SOIC (R)

Table 7. 8-Lead SOIC, ADA4084-1 Pin Function Descriptions

Pin No.

Mnemonic

Description

1

NIC

Not Internally Connected

2

−IN

Negative Input

3

+IN

Positive Input

4

V−

Negative Supply

5

NIC

Not Internally Connected

6

OUT

Output

7

V+

Positive Supply

8

NIC

Not Internally Connected

ADA4084-1


OUT 1 5 V+


V– 2


08237-301

+IN 3 4 –IN


Figure 4. ADA4084-1, 5-Lead SOT-23 (RJ)

Table 8. 5-Lead SOT-23, ADA4084-1 Pin Function Descriptions

Pin No.

Mnemonic

Description

1

OUT

Output

2

V−

Negative Supply

3

+IN

Positive Input

4

−IN

Negative Input

5

V+

Positive Supply


OUT A 1

–IN A 2

+IN A 3

V– 4

8 V+


ADA4084-2

TOP VIEW

(Not to Scale)

7 OUT B

6 –IN B

5 +IN B


08237-104

NOTES

  1. FOR THE LFCSP PACKAGE, THE EXPOSED PAD MUST BE CONNECTED TO V–.

Figure 5. ADA4084-2, 8-Lead LFCSP (CP)

Table 9. 8-Lead LFCSP, ADA4084-2 Pin Function Descriptions

Pin No.

Mnemonic

Description

1

OUT A

Output, Channel A

2

−IN A

Negative Input, Channel A

3

+IN A

Positive Input, Channel A

4

V−

Negative Supply

5

+IN B

Positive Input, Channel B

6

−IN B

Negative Input, Channel B

7

OUT B

Output, Channel B

8

V+

Positive Supply


EPAD

Exposed Pad. For the LFCSP package, the exposed pad must be connected to V−.



OUT A 1

–IN A 2

+IN A 3

V– 4


ADA4084-2

TOP VIEW

(Not to Scale)


8 V+

7 OUT B

6 –IN B

5 +IN B


OUT A 1

–IN A 2

+IN A 3

V– 4

ADA4084-2

8


7


6


5


TOP VIEW

(Not to Scale)


V+ OUT B

–IN B

08237-303

+IN B

08237-302

Figure 6. ADA4084-2, 8-Lead MSOP (RM)

Figure 7. ADA4084-2, 8-Lead SOIC (R)


Table 10. 8-Lead MSOP, 8-Lead SOIC, ADA4084-2 Pin Function Descriptions

Pin No.

Mnemonic

Description

1

OUT A

Output, Channel A

2

−IN A

Negative Input, Channel A

3

+IN A

Positive Input, Channel A

4

V−

Negative Supply

5

+IN B

Positive Input, Channel B

6

−IN B

Negative Input, Channel B

7

OUT B

Output, Channel B

8

V+

Positive Supply B


OUT A 1

–IN A 2

+IN A 3

V+ 4

+IN B 5


ADA4084-4

TOP VIEW

(Not to Scale)


14 OUT D

13 –IN D

12 +IN D

11 V–

10 +IN C

–IN B 6

OUT B 7

9 –IN C

08237-102

8 OUT C


Figure 8. ADA4084-4, 14-Lead TSSOP (RU)


Table 11. 14-Lead TSSOP, ADA4804-4 Pin Function Descriptions

Pin No.

Mnemonic

Description

1

OUT A

Output, Channel A

2

−IN A

Negative Input, Channel A

3

+IN A

Positive Input, Channel A

4

V+

Positive Supply

5

+IN B

Positive Input, Channel B

6

−IN B

Negative Input, Channel B

7

OUT B

Output, Channel B

8

OUT C

Output, Channel C

9

−IN C

Negative Input, Channel C

10

+IN C

Positive Input, Channel C

11

V−

Negative Supply

12

+IN D

Positive Input, Channel D

13

−IN D

Negative Input, Channel D

14

OUT D

Output, Channel D


16 NIC 15 OUT A 14 OUT D

13 NIC

–IN A 1

+IN A 2

V+ 3

+IN B 4


ADA4084-4

TOP VIEW

12 –IN D

11 +IN D

10 V–

9 +IN C


–IN B 5

OUT B 6

OUT C 7

–IN C 8

08237-103

NOTES

  1. NIC = NOT INTERNALLY CONNECTED.

  2. FOR THE LFCSP PACKAGE, THE EXPOSED PAD MUST BE CONNECTED TO V–.

Figure 9. ADA4084-4, 16-Lead LFCSP (CP)

Table 12. 16-Lead LFCSP, ADA4084-4 Pin Function Descriptions

Pin No.

Mnemonic

Description

1

−IN A

Negative Input Channel A

2

+IN A

Positive Input, Channel A

3

V+

Positive Supply

4

+IN B

Positive Input, Channel B

5

−IN B

Negative Input, Channel B

6

OUT B

Output, Channel B

7

OUT C

Output, Channel C

8

−IN C

Negative Input, Channel C

9

+IN C

Positive Input, Channel C

10

V−

Negative Supply

11

+IN D

Positive Input, Channel D

12

−IN D

Negative Input, Channel D

13

NIC

Not Internally Connected

14

OUT D

Output, Channel D

15

OUT A

Output, Channel A

16

NIC

Not Internally Connected


TYPICAL PERFORMANCE CHARACTERISTICS

TA = 25°C, unless otherwise noted.

±1.5 V CHARACTERISTICS

120

VSY = ±1.5V

TA = 25°C


200


VSY = ±1.5V TA = 25°C

NUMBER OF AMPLIFIERS

100


80

RL = ∞


NUMBER OF AMPLIFIERS

150

RL = ∞


60 100


40

50

20


0

–100


–75


–50


–25


0 25

VOS (µV)


50 75


100

0

08237-081

–200 –150 –100 –50 0 50 100

VOS (µV)

08237-003

Figure 10. Input Offset Voltage (VOS) Distribution, SOIC Figure 13. Input Offset Voltage (VOS) Distribution, LFCSP


100


90


80

60

VSY = ±1.5V TA = 25°C RL = ∞

50


NUMBER OF AMPLIFIERS

NUMBER OF AMPLIFIERS

70

40

60


50 30


40

30 20


20

10 VSY = ±1.5V

10 RL = ∞

–40°C ≤ TA ≤ +125°C

08237-306

08237-005

0 0

–100 –75 –50 –25 0 25 50 75 100

VOS (µV)

0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8

TCVOS (µV/°C)

2.0

Figure 11. Input Offset Voltage (VOS) Distribution, SOT-23 Figure 14. TCVOS Distribution, SOIC, MSOP, and TSSOP


50

VSY = ±1.5V

45 TA = 25°C RL = ∞

40

20

VSY = ±1.5V

18 RL = ∞

–40°C ≤ TA ≤ +125°C

16


NUMBER OF AMPLIFIERS

NUMBER OF AMPLIFIERS

35 14


30 12


25 10


20 8


15 6


10 4


5 2


0

–100


–75


–50 –25


0 25 50

VOS (µV)


75 100


0

08237-309

0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0

TCVOS (µV/°C)

08237-004

Figure 12. Input Offset Voltage (VOS) Distribution, MSOP and TSSOP Figure 15. TCVOS Distribution, SOT-23


30

VSY = ±1.5V RL = ∞

NUMBER OF AMPLIFIERS

25 –40°C ≤ TA ≤ +125°C


20


15


10


5


0

0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0

TCVOS (µV/°C)

Figure 16. TCVOS Distribution, LFCSP

50


INPUT BIAS CURRENT (nA)

VSY = ±1.5V VCM = 0V RL = ∞






IB+


















IB










–100


–150


–200


08237-213

–250

–50 –25 0 25 50 75 100 125 150

TEMPERATURE (°C)


Figure 19. Input Bias Current vs. Temperature


08237-082

500


400


INPUT OFFSET VOLTAGE (µV)

300

600


400


VSY = ±1.5V



VSY = ±1.5V TA = 25°C RL = ∞

200


100


0


–100


–200


–300


–400


–500

–1.50 –1.00 –0.50 0


0.50


1.00


1.50


200


INPUT BIAS CURRENT (nA)

0


–200


–400


08237-006

–600


TA = +85°C


TA = +125°C


TA = +25°C


TA = –40°C

COMMON-MODE VOLTAGE (V)

–1.5 –1.0

–0.5

0

VCM (V)

0.5

1.0

1.5

08237-008

Figure 17. Input Offset Voltage vs. Common-Mode Voltage Figure 20. Input Bias Current vs. VCM for Various Temperatures


VSY = ±1.5V

































































100


75


INPUT OFFSET VOLTAGE (µV)

50


25


0


–25


–50


–75


–100

–50 –25 0 25 50 75 100 125 150

TEMPERATURE (°C)


Figure 18. Input Offset Voltage vs. Temperature


1000


VDO (mV)

VSY = ±1.5V TA = 25°C



























































































































































































































































































































































































(V+) – VOH





























































































































































100


10


08237-108

08237-009

1

0.001 0.01 0.1 1 10

SOURCE CURRENT (mA)


Figure 21. Dropout Voltage (VDO) vs. Source Current



1000


VDO (mV)

100


10

1000


100


ZOUT (Ω)

10


1


0.10


VSY = ±1.5V TA = 25°C


AV = +100


AV = +10


AV = +1



VSY = ±1.5V TA = 25°C































































































































































































































































































































































































VOL – (V–)
















































































































































1

0.001 0.01 0.1 1 10

SINK CURRENT (mA)

0.01

10


100 1k 10k 100k 1M

FREQUENCY (Hz)


10M


08237-013

100M

08237-010

Figure 22. Dropout Voltage (VDO) vs. Sink Current Figure 25. Output Impedance (ZOUT) vs. Frequency


120


VSY


= ±1.5V

270

140


VSY


= ±1.5V


100

TA = 25°C RL = 10kΩ

225

120

TA = 25°C


80 180 100


GAIN (dB)

PHASE (Degrees)

PSRR (dB)

60 135 80


40 90 60


20 45 40


0 0 20


PSRR+


PSRR–


–20 –45 0


–40

0.1


1 10 100 1k 10k FREQUENCY (kHz)


–90 100k

–20

10


100 1k 10k 100k 1M

FREQUENCY (Hz)


10M


08237-014

100M

08237-011

Figure 23. Open-Loop Gain and Phase vs. Frequency Figure 26. PSRR vs. Frequency



60


50


40


GAIN (dB)

30


20


10


0


–10

140























VSY = ±1.5V TA = 25°C









































































































































































120


100


CMRR (dB)

80


60


40


20
























VSY = ±1.5V TA = 25°C





























AV = +100

























































AV = +10

























































AV = +1

























































–20

10


100 1k 10k 100k 1M

FREQUENCY (Hz)


10M


100M

0

10 100 1k 10k 100k 1M

FREQUENCY (Hz)


10M


08237-221

100M

08237-012

Figure 24. Closed-Loop Gain vs. Frequency Figure 27. CMRR vs. Frequency


VOLTAGE NOISE DENSITY (nV/√Hz)


































































































































































































































VSY = ±1.5V TA = 25°C

1.0


VOLTAGE (V)

0.5

4


0


–0.5



–1.0


–1.5

VSY = ±1.5V TA = 25°C RL = 2kΩ CL = 100pF

08237-016

0 2 4 6 8 10 12 14 16 18

TIME (µs)

Figure 28. Large Signal Transient Response


1

08237-019

1 10 100 1k 10k 100k FREQUENCY (Hz)

Figure 31. Voltage Noise Density vs. Frequency


80 60


60

50

40

VOLTAGE (mV)

OVERSHOOT (%)

40

20


0 30


VSY = ±1.5V

VIN = 100mV p-p RL = 2kΩ

TA = 25°C OS+


–20


–40


–60


–80

0


VSY = ±1.5V TA = 25°C RL = 2kΩ CL = 100pF

2 4 6 8 10 12 14 16 18


20


10


0

1 10


OS–


100


08237-020

1000

TIME (µs)

Figure 29. Small Signal Transient Response

LOAD CAPACITANCE (pF)

Figure 32. Overshoot vs. Load Capacitance


08237-017



INPUT



OUTPUT


VSY = ±1.5V TA = 25°C

2 0.08 80


60

0 0.06

VOLTAGE NOISE (nV)

40

–2 0.04

VOLTAGE (V)

VOLTAGE (V)

20


–4 0.02 0



–6 0


–8 –0.02

–20


–40


–60


VSY


= ±1.5V


–10

–1 0


1 2 3


4 5 6 7 8

TIME (µs)


–0.04

9


–80

TA = 25°C

08237-021

0 1 2 3 4 5 6 7 8 9 10

TIME (Seconds)

08237-018

Figure 30. Settling Time Figure 33. Voltage Noise, 0.1 Hz to 10 Hz


0


–20


CHANNEL SEPARATION (dB)

–40


VSY = ±1.5V TA = 25°C VIN = 1V p-p


10V p-p


VCC


+

VEE


2kΩ


2kΩ


10kΩ VCC


+

VEE


1kΩ

0.1


VSY = ±1.5V TA = 25°C

VIN = 300mV rms

80kHz FILTER


–60

CH A

CH B, CH C, CH D

0.01


–80

RL = 2kΩ


–100


–120


THD + N (%)

0.001


RL = 10kΩ


08237-022

–140


–160

100 1k 10k 100k FREQUENCY (Hz)

Figure 34. Channel Separation vs. Frequency

0.0001

08237-231

10 100 1k 10k 100k FREQUENCY (Hz)

Figure 37. THD + N vs. Frequency, 80 kHz Filter



1

V = ±1.5V

2.0


VSY = ±1.5V TA = 25°C

THD + N (%)

0.1


0.01

SY

TA = 25°C RL = 10kΩ VIN AT 1kHz

1.5


1.0


VOLTAGE (V)

0.5


0


–0.5


OUTPUT


INPUT

–1.0

0.001

–1.5



0.0001

0.001 0.01


0.1 1

–2.0

0


100 200 300 400 500 600 700 800 900

TIME (µs)


1000

08237-025

AMPLITUDE (VRMS)

Figure 35. THD + N vs. Amplitude


08237-125

Figure 38. No Phase Reversal


0.01

0.5


0


VOLTAGE (V)

–0.5


–1.0


–1.5


08237-126

–2.0


INPUT


OUTPUT

4


3


VOLTAGE (V)

2


1


0


VSY = ±1.5V TA = 25°C

08237-233

–1

THD + N (%)

VSY = ±1.5V TA = 25°C

VIN = 300mV rms

500kHz FILTER
















































RL = 2kΩ

































































































































RL = 10kΩ


































0.001

0.01 0.1

1 10 100

FREQUENCY (kHz)

–2 0

2 4 6

8 10 12

TIME (µs)

14 16 18

Figure 36. THD + N vs. Frequency, 500 kHz Filter Figure 39. Positive 50% Overload Recovery


0.5 3


0 2

INPUT


VOLTAGE (V)

VOLTAGE (V)

–0.5 1


–1.0


OUTPUT


0


–1.5


–2.0

–2 0 2 4


6 8 10 12

TIME (µs)

–1


VSY = ±1.5V TA = 25°C

08237-234

–2

14 16 18

Figure 40. Negative 50% Overload Recovery

±5 V CHARACTERISTICS

120

VSY = ±5V

TA = 25°C


250

100

RL = ∞


200


VSY = ±5V TA = 25°C RL = ∞

NUMBER OF AMPLIFIERS

NUMBER OF AMPLIFIERS

80

150


60


100

40


50

20


0

–100


–75


–50


–25


0 25

VOS (µV)


50 75 100

0

08237-080

–200 –150 –100 –50 0 50 100

VOS (µV)

08237-026

Figure 41. Input Offset Voltage (VOS) Distribution, SOIC Figure 44. Input Offset Voltage (VOS) Distribution, LFCSP


VSY = ±5V TA = 25°C RL = ∞

120


100

50

VSY = ±5V

45 RL = ∞

–40°C ≤ TA ≤ +125°C

40


NUMBER OF AMPLIFIERS

NUMBER OF AMPLIFIERS

35

80

30


60 25


20

40

15


10

20

5


0

–100 –75 –50 –25 0 25 50 75 100

VOS (µV)


0

0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8

TCVOS (µV/°C)


2.0

08237-335

08237-028

Figure 42. Input Offset Voltage (VOS) Distribution, SOT-23 Figure 45. TCVOS Distribution, SOIC, MSOP, and TSSOP


60

VSY = ±5V

TA = 25°C

NUMBER OF AMPLIFIERS

50 RL = ∞


40


30

20

VSY = ±5V

18 RL = ∞

–40°C ≤ TA ≤ +125°C

NUMBER OF AMPLIFIERS

16


14


12


10


20


10


0

–100


–75


–50


–25


0 25

VOS (µV)


50 75


100


8


6


4


2


08237-338

0

0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2

TCVOS (µV/°C)

08237-027

Figure 43. Input Offset Voltage (VOS) Distribution, MSOP and TSSOP Figure 46. TCVOS Distribution for SOT-23


35

VSY = ±5V RL = ∞

30 –40°C ≤ TA ≤ +125°C


NUMBER OF AMPLIFIERS

25


20


15


10

–50


INPUT BIAS CURRENT (nA)

–100


–150


–200


VSY = ±5V VCM = 0V RL = ∞


IB+


IB


08237-084

08237-030

5


0

0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0

TCVOS (µV/°C)

Figure 47. TCVOS Distribution, LFCSP


–250

–40


–25 –10 5 20 35 50 65 80 95 110

TEMPERATURE (°C)


Figure 50. Input Bias Current vs. Temperature


125


600

500

INPUT OFFSET VOLTAGE (µV)

400

300

200

100

0

–100

–200

800


600


INPUT BIAS CURRENT (nA)

400


200


0


–200


VSY = ±5V


TA = +85°C


TA = +125°C


VSY = ±5V TA = 25°C RL = ∞












–300

–400

–500

–600

–5


–4 –3 –2 –1 0 1 2 3 4 5


–400


–600


08237-029

08237-031

–800

TA = +25°C

TA = –40°C

COMMON-MODE VOLTAGE (V)

–5 –4 –3 –2 –1 0 1 2 3 4 5

VCM (V)

Figure 48. Input Offset Voltage vs. Common-Mode Voltage Figure 51. Input Bias Current vs. VCM for Various Temperatures


100


75


INPUT OFFSET VOLTAGE (µV)

50


25


0


–25


–50


08237-133

–75


1000


VDO (mV)

100


10


VSY = ±5V TA = 25°C


(V+) – VOH


VSY = ±5V

































































–100

–50 –25 0 25 50 75 100 125 150

TEMPERATURE (°C)


Figure 49. Input Offset Voltage vs. Temperature


1

08237-032

0.001 0.01 0.1 1 10

SOURCE CURRENT (mA)

Figure 52. Dropout Voltage (VDO) vs. Source Current



VSY


= ±5V

1000


VSY = ±5V TA = 25°C

1000

TA = 25°C


100


AV = +10



VDO (mV)

100


10


VOL – (V–)

10


ZOUT (Ω)

1


0.10


AV = +100

AV = +1



1

0.001 0.01 0.1 1 10

SINK CURRENT (mA)

0.01

10


100 1k 10k 100k 1M

FREQUENCY (Hz)


10M


08237-036

100M

08237-033

Figure 53. Dropout Voltage (VDO) vs. Sink Current Figure 56. Output Impedance (ZOUT) vs. Frequency


120


100


VSY = ±5V TA = 25°C RL = 10kΩ

270


225

140


120


VSY = ±5V TA = 25°C


80 180 100


GAIN (dB)

PHASE (Degrees)

PSRR (dB)

60 135 80


40 90 60


20 45 40


0 0 20


PSRR+


PSRR–


–20 –45 0



–40

0.1


1 10 100 1k 10k FREQUENCY (kHz)


–90 100k

–20

10


100 1k 10k 100k 1M

FREQUENCY (Hz)


10M


08237-037

100M

08237-034

Figure 54. Open-Loop Gain and Phase vs. Frequency Figure 57. PSRR vs. Frequency


60


50


40


GAIN (dB)

30


20


10


0


–10

140

























VSY = ±5V TA = 25°C









































































































































































120


100


CMRR (dB)

80


60


40


20

























VSY = ±5V TA = 25°C





























AV = +100

























































AV = +10

























































AV = +1

























































–20

10


100 1k 10k 100k 1M

FREQUENCY (Hz)


10M


100M

0

10 100 1k 10k 100k 1M

FREQUENCY (Hz)


10M


08237-221

100M

08237-035

Figure 55. Closed-Loop Gain vs. Frequency Figure 58. CMRR vs. Frequency



































































































































































































































VSY = ±5V TA = 25°C

5 10


VOLTAGE NOISE DENSITY (nV/√Hz)

4


3


2


VOLTAGE (V)

1 4


0


–1


–2


–3 VSY = ±5V

TA = 25°C

–4 RL = 2kΩ

CL = 100pF

–5

0 2 4 6 8 10 12 14 16 18

TIME (µs)

Figure 59. Large Signal Transient Response


1

08237-042

1 10 100 1k 10k 100k FREQUENCY (Hz)

Figure 62. Voltage Noise Density vs. Frequency


08237-039

80 60


60

50

40

VOLTAGE (mV)

OVERSHOOT (%)

40

20


0 30


VSY = ±5V

VIN = 100mV p-p RL = 2kΩ

TA = 25°C


OS+


–20


–40


–60


–80

0 1


2 3 4


VSY = ±5V TA = 25°C RL = 2kΩ CL = 100pF

5 6 7


8 9 10


20


10


0

1 10


OS–


100


08237-043

1000

TIME (µs)

Figure 60. Small Signal Transient Response

LOAD CAPACITANCE (pF)

Figure 63. Overshoot vs. Load Capacitance


08237-040

VSY = ±5V TA = 25°C


INPUT



OUTPUT




10


5


0


VOLTAGE (V)

–5


–10


–15


–20


–25

–2 0 2 4


6 8 10 12

TIME (µs)


14 16

0.16


0.12


0.08


VOLTAGE (V)

0.04


0


–0.04


–0.08


–0.12

18


80


60


VOLTAGE NOISE (nV)

40


20


0


–20


–40


–60


–80


VSY = ±5V TA = 25°C


08237-044

0 1 2 3 4 5 6 7 8 9 10

TIME (Seconds)

08237-041

Figure 61. Settling Time Figure 64. Voltage Noise, 0.1 Hz to 10 Hz


0


–20


VSY = ±5V TA = 25°C VIN = 5V p-p


VCC


10kΩ VCC


1kΩ

0.1


TA = 25°C

VIN = 300mV rms

80kHz FILTER

































































































RL = 2kΩ





































































































































































































































































RL = 10kΩ












































































































































VSY = ±5V


CHANNEL SEPARATION (dB)

–40


–60


–80


–100


–120


–140


10V p-p

+

VEE CH A


2kΩ


2kΩ

+

VEE

CH B,

CH C, CH D


0.01


THD + N (%)

0.001


08237-045

0.0001


–160

100 1k 10k 100k FREQUENCY (Hz)

Figure 65. Channel Separation vs. Frequency

0.00001


08237-260

10 100 1k 10k 100k FREQUENCY (Hz)

Figure 68. THD + N vs. Frequency, 80 kHz Filter


1


THD + N (%)

0.1


0.01


0.001

6

VSY = ±5V TA = 25°C





INPUT

OUTPUT




VSY = ±5V TA = 25°C RL = 10kΩ

VIN AT 1kHz 4


VOLTAGE (V)

2


0


–2


–4



0.0001

0.001 0.01


0.1 1

AMPLITUDE (VRMS)

–6

0 100 200 300 400 500 600 700 800 900

TIME (µs)


1000

08237-150

08237-048

Figure 66. THD + N vs. Amplitude Figure 69. No Phase Reversal



1


0.1


VSY = ±5V TA = 25°C

VIN = 2V rms

500kHz FILTER

1 10


0 8

INPUT


VOLTAGE (V)

VOLTAGE (V)

–1 6


THD + N (%)

0.01


RL = 2kΩ

–2 4



0.001


RL = 10kΩ

–3


OUTPUT

–4


–5

2


0

VSY = ±5V TA = 25°C

08237-262

–2

0.0001

0.01 0.1


1 10 100

FREQUENCY (kHz)

–2 0

2 4 6

8 10 12

TIME (µs)

14 16 18

08237-151

Figure 67. THD + N vs. Frequency, 500 kHz Filter

Figure 70. Positive 50% Overload Recovery


1 6


0 4

INPUT


VOLTAGE (V)

VOLTAGE (V)

–1 2


OUTPUT

–2 0


–3 –2


–4


–5

–2 0 2 4


6 8 10 12

TIME (µs)

–4

VSY = ±5V TA = 25°C

08237-263

–6

14 16 18

Figure 71. Negative 50% Overload Recovery

±15 V CHARACTERISTICS

100

VSY = ±15V 90 TA = 25°C

RL = ∞

NUMBER OF AMPLIFIERS

80


70


200


NUMBER OF AMPLIFIERS

150


VSY = ±15V TA = 25°C RL = ∞


60


50 100


40


30

50

20


10


0

–100


–75


–50


–25


0 25

VOS (µV)


50 75 100


0

08237-079

–200 –150 –100 –50 0 50 100

VOS (µV)

08237-049

Figure 72. Input Offset Voltage (VOS) Distribution, SOIC Figure 75. Input Offset Voltage (VOS) Distribution, LFCSP


100


90


80


VSY = ±1.5V TA = 25°C RL = ∞

60

VSY = ±15V

RL = ∞

50 –40°C ≤ TA ≤ +125°C


NUMBER OF AMPLIFIERS

NUMBER OF AMPLIFIERS

70

40

60


50 30


40

30 20


20

10

10


0

–100 –75 –50 –25 0 25 50 75 100

VOS (µV)


0

0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8

TCVOS (µV/°C)


2.0

08237-364

08237-051

Figure 73. Input Offset Voltage (VOS) Distribution, SOT-23 Figure 76. TCVOS Distribution, SOIC, MSOP, and TSSOP


VSY = ±15V RL = ∞

–40°C ≤ TA ≤ +125°C

60 25

VSY = ±15V

TA = 25°C

50 RL = ∞

20


NUMBER OF AMPLIFIERS

NUMBER OF AMPLIFIERS

40

15


30


10

20


5

10


0

–100


–75


–50


–25


0 25

VOS (µV)


50 75


100

0

08237-367

0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0

TCVOS (µV)

08237-050

Figure 74. Input Offset Voltage (VOS) Distribution, MSOP and TSSOP Figure 77. TCVOS Distribution, SOT-23


30

VSY = ±15V RL = ∞

25 –40°C ≤ TA ≤ +125°C

–50


INPUT BIAS CURRENT (nA)

–100


IB+


NUMBER OF AMPLIFIERS

20


15 –150


10

–200


5


–250

IB


08237-053

VSY = ±15V VCM = 0V RL = ∞

08237-085

0

0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0

TCVOS (µV/°C)

Figure 78. TCVOS Distribution, LFCSP

–40

–25 –10 5 20 35 50 65 80 95 110

TEMPERATURE (°C)


Figure 81. Input Bias Current vs. Temperature

125


600

500

INPUT OFFSET VOLTAGE (µV)

400

300

200

100

0

–100

1200


INPUT BIAS CURRENT (nA)

800


400


0


VSY = ±15V


TA = +85°C


TA = +125°C

VSY = ±15V TA = 25°C RL = ∞




–200

–300

–400

–500

–600

–15 –10 –5 0


5 10 15


–400


–800


08237-052

–1200


TA = +25°C


TA = –40°C

COMMON-MODE VOLTAGE (V)

–15 –10 –5

0

VCM (V)

5 10 15

08237-054

Figure 79. Input Offset Voltage vs. Common-Mode Voltage Figure 82. Input Bias Current vs. VCM for Various Temperatures


100


75


INPUT OFFSET VOLTAGE (µV)

50


25


10000


1000


0


–25


–50


08237-165

–75


100


VDO (mV)

10


(V+) – VOH


VSY = ±15V

































































–100

–50 –25 0 25 50 75 100 125 150

TEMPERATURE (°C)

Figure 80. Input Offset Voltage vs. Temperature

1

VSY = ±15V TA = 25°C

08237-055

0.001 0.01 0.1 1 10

SOURCE CURRENT (mA)


Figure 83. Dropout Voltage (VDO) vs. Source Current



10000


VDO (mV)

1000


100


10


1


VSY = ±15V TA = 25°C


VOL – (V–)

1000


100


ZOUT (Ω)

10


1


0.1


0.01


AV = +100


AV = +10


AV = +1


08237-059

VSY = ±15V TA = 25°C

0.001 0.01 0.1 1 10

SINK CURRENT (mA)

10 100 1k 10k 100k 1M

FREQUENCY (Hz)

10M

100M

08237-056

Figure 84. Dropout Voltage (VDO) vs. Sink Current Figure 87. Output Impedance (ZOUT) vs. Frequency


120


VSY


= ±15V

270

140


VSY


= ±15V

100

TA = 25°C RL = 10kΩ

225


120

TA = 25°C


80 180 100


GAIN (dB)

PHASE (Degrees)

PSRR (dB)

60 135 80


40 90 60


PSRR–


20 45 40


0 0 20 PSRR+


–20 –45 0


–40

100


1k 10k 100k 1M 10M FREQUENCY (Hz)

–90 100M

–20

10


100 1k 10k 100k 1M

FREQUENCY (Hz)


10M


08237-060

100M

08237-057

Figure 85. Open-Loop Gain and Phase vs. Frequency Figure 88. PSRR vs. Frequency


60


50


40


GAIN (dB)

30


20


10


0


–10

140























VSY = ±15V TA = 25°C









































































































































































120


100


CMRR (dB)

80


60


40


20


VSY = ±15V TA = 25°C



















































AV = +100



























































AV = +10



























































AV = +1



























































–20

10


100 1k 10k 100k 1M

FREQUENCY (Hz)


10M


100M

0

10 100 1k 10k 100k 1M

FREQUENCY (Hz)


10M


08237-279

100M

08237-058

Figure 86. Closed-Loop Gain vs. Frequency Figure 89. CMRR vs. Frequency



































































































































































































































VSY = ±15V TA = 25°C

15 10


VOLTAGE NOISE DENSITY (nV/√Hz)

10


VOLTAGE (V)

5

4


0


–5



–10


–15

VSY = ±15V TA = 25°C RL = 2kΩ CL = 100pF

08237-062

08237-065

1

0 4 8 12 16 20

24 28 32 36

1 10 100 1k 10k 100k

TIME (µs)

Figure 90. Large Signal Transient Response

FREQUENCY (Hz)

Figure 93. Voltage Noise Density vs. Frequency


80


60


40


VOLTAGE (mV)

20


0


–20


–40


–60


–80


08237-063

VSY = ±15V TA = 25°C RL = 2kΩ CL = 100pF

70

VSY = ±15V

VIN = 100mV p-p

60 RL = 2kΩ

TA = 25°C OS+

OVERSHOOT (%)

50


40


30


20 OS–


10


08237-066

0

0 1 2 3 4

5 6 7 8 9 10

1 10

100

1000

TIME (µs)

Figure 91. Small Signal Transient Response

LOAD CAPACITANCE (pF)

Figure 94. Overshoot vs. Load Capacitance



INPUT


OUTPUT


VSY = ±15V TA = 25°C

10 0.20 60


5 0.15 40


0


VOLTAGE (V)

–5


–10


–15


0.10


VOLTAGE (V)

0.05


0


–0.05


20


VOLTAGE NOISE (nV)

0


–20



–20


–25

–2 0 2 4


6 8 10 12

TIME (µs)


14 16


–0.10


–0.15

18

–40


–60


VSY = ±15V TA = 25°C

08237-067

0 2 4 6 8 10

TIME (Seconds)

08237-064

Figure 92. Settling Time Figure 95. Voltage Noise 0.1 Hz to 10 Hz


0


–20


CHANNEL SEPARATION (dB)

–40


VSY = ±15V TA = 25°C VIN = 10V p-p


10V p-p


VCC


+

VEE


2kΩ


2kΩ


10kΩ VCC


+

VEE


1kΩ

0.1


0.01


VSY = ±15V TA = 25°C

VIN = 300mV rms

80kHz FILTER


RL = 2kΩ

–60


–80


–100

CH A

CH B, CH C, CH D


THD + N (%)

0.001


–120


–140


08237-068

–160


0.0001


RL = 10kΩ


–180

100 1k 10k 100k FREQUENCY (Hz)

Figure 96. Channel Separation vs. Frequency


0.00001


08237-289

10 100 1k 10k 100k FREQUENCY (Hz)

Figure 99. THD + N vs. Frequency, 80 kHz Filter



1


THD + N (%)

0.1


0.01


0.001


VSY = ±15V RL = 10kΩ VIN AT 1kHz

20


VSY = ±15V TA = 25°C




OUTPUT

INPUT



15


10


VOLTAGE (V)

5


0


–5


–10


08237-071

–15



0.0001

0.001 0.01


0.1 1 10

AMPLITUDE (VRMS)

–20

0


100 200 300 400 500 600 700 800 900

TIME (µs)


1000

08237-175

Figure 97. THD + N vs. Amplitude Figure 100. No Phase Reversal


1


THD + N (%)

0.1


0.01


0.001


1




VIN


VOUT


VSY = ±15V

CH1 AMPL 202mV


2


VSY = ±15V

TA = 25°C

VIN = 5V rms

500kHz FILTER





















































































































































































































RL = 2kΩ



























































































































RL = 10kΩ
































































































































0.0001

0.01 0.1


1 10 100

FREQUENCY (kHz)


CH1 100mV


CH2 5V


08237-178

M1µs A CH1 –84mV

T 10.2%

08237-176

Figure 98. THD + N vs. Frequency, 500 kHz Filter Figure 101. Positive 50% Overload Recovery


VCM = ±14V


VSY = ±15V





VIN







VOUT


140



CH1 AMPL 200mV

1


2

120


100


CMRR (dB)

80


VCM


= ±4V

VCM = ±1.5V

60


40


08237-179

20



CH1 100mV


CH2 5V


M2µs A CH1 44mV

T 10.4%

0

08237-180

–50 –25 0 25 50 75 100 125 150

TEMPERATURE (°C)

Figure 102. Negative 50% Overload Recovery

Figure 104. CMRR vs. Temperature


1000


900


800


ISY/AMPLIFIER (µA)

700


600


500


400


300


200


100


+125°C


+25°C


+85°C


–40°C


08237-072

TA = 25°C RL = ∞

150


140


130


120


PSRR (dB)

110


100


90


80


70


60


08237-181

50


VSY = ±2V TO ±18V, VCM = 0V


VSY = ±1.25V TO ±1.75V, VCM = 0V

0

0 4 8 12 16 20 24 28 32 36

VSY (V)

–50 –25 0 25 50 75 100 125 150

TEMPERATURE (°C)

Figure 103. Supply Current (ISY) per Amplifier vs. Supply Voltage (VSY) for Various Temperatures

Figure 105. PSRR vs. Temperature


APPLICATIONS INFORMATION

FUNCTIONAL DESCRIPTION

The ADA4084-1/ADA4084-2/ADA4084-4 devices are precision single-supply, rail-to-rail operational amplifiers. Intended for portable instrumentation, the ADA4084-1/ADA4084-2/ ADA4084-4 devices combine the attributes of precision, wide bandwidth, and low noise, making them an ideal choice in single-supply applications that require both ac and precision dc performance. Other low supply voltage applications for which the ADA4084-1/ADA4084-2/ADA4084-4 devices are well suited include active filters, audio microphone preamplifiers, power supply control, and telecommunications. To combine all of these attributes with rail-to-rail input/output operation, novel circuit design techniques are used.


A key issue in the input stage is the behavior of the input bias currents over the input common-mode voltage range. Input bias currents in the ADA4084-1/ADA4084-2/ADA4084-4 are the arithmetic sum of the base currents in Q1 and Q4 and in Q2 and Q3. As a result of this design approach, the input bias currents in the ADA4084-1/ADA4084-2/ADA4084-4 not only exhibit different amplitudes, but they also exhibit different polarities. This effect is best shown in Figure 19, Figure 20, Figure 50, Figure 51, Figure 81, and Figure 82. It is, therefore, important that the effective source impedances that are connected to the ADA4084-1/ ADA4084-2/ADA4084-4 inputs be balanced for optimum dc and ac performance.

To achieve rail-to-rail output, the ADA4084-1/ADA4084-2/ ADA4084-4 output stage design employs a unique topology for

R4


D2 Q1


Q4

R3


D1

Q2

D100


D101 Q3

both sourcing and sinking current. This circuit topology is shown in Figure 107. The output stage is voltage driven from the second gain stage. The signal path through the output stage is inverting; that is, for positive input signals, Q13 provides the base current drive to Q19 so that it conducts (sinks) current. For negative input signals, the signal path via Q18 to the mirror to Q24 provides the base current drive for Q23 to conduct (source) current. Both transistors provide output current until they are forced into saturation.

VCC


D5 D4


R6

Q24


Q23


08237-073

R1 R2

MIRROR


Figure 106. Equivalent Input Circuit

For example, Figure 106 illustrates a simplified equivalent circuit for the input stage of the ADA4084-1/ADA4084-2/ ADA4084-4. It comprises a PNP differential pair, Q1 and Q2, and an NPN differential pair, Q3 and Q4, operating concurrently. Diode D100 and Diode D101 serve to clamp the applied differential input voltage to the ADA4084-1/ADA4084-2/ ADA4084-4, thereby protecting the input transistors against Zener breakdown of the emitter-base junctions. Input stage voltage gains are kept low for input rail-to-rail operation. The two pairs of


Q13


R5


VBIAS

Q18

C1


Q21


R7 C2


D20


Q19


VOUT


08237-074

VEE

differential output voltages are connected to the second stage of the ADA4084-1/ADA4084-2/ADA4084-4, which is a modified compound folded cascade gain stage. It is also in the second gain stage that the two pairs of differential output voltages are combined into a single-ended output signal voltage used to drive the output stage.

Figure 107. Equivalent Output Circuit

Thus, the saturation voltage of the output transistors sets the limit on the ADA4084-1/ADA4084-2/ADA4084-4 maximum output voltage swing. Output short-circuit current limiting is determined by the maximum signal current into the base of Q13 from the second gain stage. The output stage also exhibits voltage gain. This is accomplished by the use of common-emitter amplifiers, and, as a result, the voltage gain of the output stage (thus, the open-loop gain of the device) exhibits a dependence on the total load resistance at the output of the ADA4084-1/ ADA4084-2/ADA4084-4.

START-UP CHARACTERISTICS

The ADA4084-1/ADA4084-2/ADA4084-4 are specified to operate from 3 V to 30 V (±1.5 V to ±15 V) under nominal power supplies. During power-up as the supply voltage increases from

0 V to the nominal power supply voltage, the supply current (ISY) increases as well, to the point at which it stabilizes and the amplifier is ready to operate. The stabilization varies with temperature, as


R1

VIN


R2


1/2

08237-075

ADA4084-1/ ADA4084-2/ ADA4084-4


VOUT

shown in Figure 103. For example, at −40°C, it requires a higher voltage and stabilizes at a lower supply current than at hot temperatures. At hot temperatures, it requires a lower voltage but stabilizes at a higher current. In all cases, the ADA4084-1/ ADA4084-2/ADA4084-4 are specified to start up and operate at a minimum of 3 V under all temperature conditions.

INPUT PROTECTION

As with any semiconductor device, if conditions exist where the applied input voltages to the device exceed either supply voltage, the input overvoltage I-to-V characteristic of the device must be considered. When an overvoltage occurs, the amplifier may be damaged, depending on the magnitude of the applied voltage and the magnitude of the fault current.

The D1, D2, D4, and D5 diodes conduct when the input common- mode voltage exceeds either supply pin by a diode drop. This diode drop voltage varies with temperature and is in the range of 0.3 V to 0.8 V. As shown in the simplified equivalent input circuit of Figure 106, the ADA4084-1/ADA4084-2/ADA4084-4 do not have any internal current limiting resistors; thus, fault currents can quickly rise to damaging levels.

This input current is not inherently damaging to the device, provided that it is limited to 5 mA or less. If a fault condition causes more than 5 mA to flow, add an external series resistor at the expense of additional thermal noise. Figure 108 shows a typical noninverting configuration for an overvoltage protected amplifier, where the series resistance (R1) is chosen, such that

R1 VIN MAX VSUPPLY

5 mA

For example, a 1 kΩ resistor protects the ADA4084-1/ADA4084-2/ ADA4084-4 against input signals up to 5 V above and below the supplies. Note that the thermal noise of a 1 kΩ resistor at room temperature is 4 nV/√Hz, which exceeds the voltage noise of the ADA4084-1/ADA4084-2/ADA4084-4. For other configurations in which both inputs are used, add a series resistor to limit the input current. To ensure optimum dc and ac performance, balance the source impedance levels.

Figure 108. Resistance in Series with the Input Limits Overvoltage Currents to Safe Values

To protect the Q1/Q2 and Q3/Q4 pairs from large differential voltages that may result in Zener breakdown of the emitter-base junction, D100 and D101 are connected between the two inputs. This precludes operation as a comparator. For a more complete description, see the MT-035 Tutorial, Op Amp Inputs, Outputs,

Single-Supply, and Rail-to-Rail Issues; the MT-083 Tutorial,

Comparators; the MT-084 Tutorial, Using Op Amps as Comparators; and the AN-849 Application Note, Using Op Amps as Comparators.

OUTPUT PHASE REVERSAL

Some operational amplifiers designed for single-supply operation exhibit an output voltage phase reversal when their inputs are driven beyond their useful common-mode range. Typically, for single-supply bipolar op amps, the negative supply determines the lower limit of their common-mode range. With these devices, external clamping diodes, with the anode connected to ground and the cathode to the inputs, prevent input signal excursions from exceeding the negative supply of the device (that is, GND), preventing a condition that causes the output voltage to change phase. JFET input amplifiers can also exhibit phase reversal, and, if so, a series input resistor is usually required to prevent it.

The ADA4084-1/ADA4084-2/ADA4084-4 are free from reasonable input voltage range restrictions, provided that input voltages no greater than the supply voltages are applied (see Figure 38, Figure 69, and Figure 100).

Although device output does not change phase, large currents can flow through the input protection diodes. Therefore, apply the technique recommended in the Input Protection section to those applications where the likelihood of input voltages exceeding the supply voltages is high.


DESIGNING LOW NOISE CIRCUITS IN SINGLE- SUPPLY APPLICATIONS

In single-supply applications, devices like the ADA4084-1/ ADA4084-2/ADA4084-4 extend the dynamic range of the application through the use of rail-to-rail operation. Referring to the op amp noise model circuit configuration illustrated in Figure 109, the expression for the total equivalent input noise voltage of an amplifier for a source resistance level, RS, is given by

Because circuit SNR is the critical parameter in the final analysis, the noise behavior of a circuit is sometimes expressed in terms of its noise figure (NF). The noise figure is defined as the ratio of the signal-to-noise output of a circuit to its signal-to-noise input.

Noise figure is generally used for RF and microwave circuit analysis in a 50 Ω system. This is not very useful for op amp circuits where the input and output impedances can vary greatly. For a more complete description of noise figure, see the MT-052 Tutorial,

enT

where:

2[(enR )2

2 (enOA)2

, units in V

Hz

Op Amp Noise Figure: Don’t be Misled.

Signal levels in the application invariably increase to maximize circuit SNR, which is not an option in low voltage, single-supply applications.

(enR)2 is the source resistance thermal noise voltage power (4kTR).

k is the Boltzmann’s constant, 1.38 × 10–23 J/K.

T is the ambient temperature in Kelvin of the circuit, 273.15 + TA (°C).

(inOA)2 is the op amp equivalent input noise current spectral power (1 Hz bandwidth).

RS = 2R, the effective, or equivalent, circuit source resistance. (enOA)2 is the op amp equivalent input noise voltage spectral power (1 Hz bandwidth).

Therefore, to achieve optimum circuit SNR in single-supply applications, choose an operational amplifier with the lowest equivalent input noise voltage, along with source resistance levels that are consistent with maintaining low total circuit noise.

COMPARATOR OPERATION

Although op amps are quite different from comparators, occasionally an unused section of a dual or a quad op amp can be used as a comparator; however, this is not recommended for

R NOISELESS


R NOISELESS

enR


enR

enOA


inOA


IDEAL NOISELESS OP AMP

any rail-to-rail output op amps. For rail-to-rail output op amps, the output stage is generally a ratioed current mirror with bipolar or MOSFET transistors. With the device operating open-loop, the second stage increases the current drive to the ratioed mirror to close the loop. However, the loop cannot close, which results in

08237-076

an increase in supply current. With the op amp configured as a

inOA

RS = 2R

comparator, the supply current can be significantly higher (see

Figure 109. Op Amp Noise Circuit Model Used to Determine Total Circuit Equivalent Input Noise Voltage and Noise Figure

As a design aid, Figure 110 shows the equivalent thermal noise of the ADA4084-1/ADA4084-2/ADA4084-4 vs. the total source resistance. Note that for source resistance less than 1 kΩ, the equivalent input noise voltage of the ADA4084-1/ADA4084-2/

ADA4084-4 is dominant.

Figure 111). Configure an unused section as a voltage follower with the noninverting input connected to a voltage within the input voltage range. The ADA4084-1/ADA4084-2/ADA4084-4 have unique second stage and output stage designs that greatly reduce the excess supply current when the op amp is operating open-loop.

800


EQUIVALENT THERMAL NOISE (nV/ Hz)

100


10


FREQUENCY = 1kHz TA = 25°C


ADA4084-1/ADA4084-2/ADA4084-4 TOTAL EQUIVALENT NOISE


RESISTOR THERMAL NOISE ONLY


700


SUPPLY CURRENT (µA)

600


500


400


300


200


100

COMPARATOR OUTPUT LOW


COMPARATOR OUTPUT HIGH



BUFFER


08237-077

TA = 25°C


1

100 1k


10k


100k

RL = ∞

08237-078

0

0 4 8 12 16 20 24 28 32 36

VSY (V)

TOTAL SOURCE RESISTANCE, RS (Ω)

Figure 110. Equivalent Thermal Noise vs. Total Source Resistance

Figure 111. Supply Current vs. Supply Voltage (VSY)

LONG-TERM DRIFT

The stability of a precision signal path over its lifetime or between calibration procedures is dependent on the long-term stability of the analog components in the path, such as op amps, references, and data converters. To help system designers predict the long-term drift of circuits that use the ADA4084-1/ ADA4084-2/ADA4084-4, Analog Devices measured the offset voltage of multiple units for 10,000 hours (more than 13 months) using a high precision measurement system, including an ultrastable oil bath. To replicate real-world system performance, the devices under test (DUTs) were soldered onto an FR4 PCB using a standard reflow profile (as defined in the JEDEC J-STD- 020D standard), as opposed to testing them in sockets. This manner of testing is important because expansion and contraction of the PCB can apply stress to the integrated circuit (IC) package and contribute to shifts in the offset voltage.

The ADA4084-1/ADA4084-2/ADA4084-4 have extremely low long-term drift, as shown in Figure 112. The red, blue, and green traces show sample units. Note that the mean drift of the ADA4084-1/ADA4084-2/ADA4084-4 over 10,000 hours is less than 3 μV, or less than 3% of their maximum specified offset voltage of 100 µV at room temperature.

15

MEAN

CHANGE IN OFFSET VOLTAGE (µV)

MEAN PLUS ONE STANDARD DEVIATION MEAN MINUS ONE STANDARD DEVIATION

10


5


0

TEMPERATURE HYSTERESIS

In addition to stability over time as described in the Long-Term Drift section, it is useful to know the temperature hysteresis, that is, the stability vs. cycling of temperature. Hysteresis is an important parameter because it tells the system designer how closely the signal returns to its starting amplitude after the ambient temperature changes and subsequent return to room temperature. Figure 113 shows the change in input offset voltage as the temperature cycles three times from room temperature to +125°C to −40°C and back to room temperature. The dotted line is an initial preconditioning cycle to eliminate the original temperature-induced offset shift from exposure to production solder reflow temperatures. In the three full cycles, the offset hysteresis is typically only 4 μV, or 2% of its 200 µV maximum offset voltage over the full operating temperature range. The histogram in Figure 114 shows that the hysteresis is larger when the device is cycled through only a half cycle, from room temperature to 125°C and back to room temperature.

VSY = 10V





PRECONDITION

CYCLE 1

CYCLE 2

CYCLE 3
















































































100


CHANGE IN OFFSET VOLTAGE (µV)

80


60


40


20


0


–20


–40


–60


–80


–5


–10


0

–15


SAMPLE 1

SAMPLE 2

1000

2000

3000

4000

5000

6000

SAMPLE 3


TIME (Hours)


7000

8000

9000

10,000

08237-112

VSY = 10V 27 UNITS TA = 25°C


–100

08237-113

–40 –20 0 20 40 60 80 100 120

TEMPERATURE (°C)

Figure 113. Change in Offset Voltage over Three Full Temperature Cycles

VSY = 10V

27 UNITS × 3 CYCLES

HALF CYCLE = +26°C, +125°C, +26°C

FULL CYCLE = +26°C, +125°C, +26°C, –40°C, +26°C

HALF CYCLE

FULL CYCLE












































































40

35

30

25

NUMBER OF DEVICES

20

15

Figure 112. Measured Long-Term Drift of the ADA4084-1/ADA4084-2/ ADA4084-4 Offset Voltage over 10,000 Hours

10

5

0





















































































40

35

30

25

20

15

10

5

08237-114

0

–40 –32 –24 –18 –8 0 8 18 24 32 40

OFFSET VOLTAGE HYSTERESIS (µV)

Figure 114. Histogram Showing the Temperature Hysteresis of the Offset Voltage over Three Full Cycles and over Three Half Cycles


OUTLINE DIMENSIONS


5.00 (0.1968)

4.80 (0.1890)


4.00 (0.1574)

3.80 (0.1497)

8

5

6.20 (0.2441)

4

1

5.80 (0.2284)



0.25 (0.0098)

0.10 (0.0040)

1.27 (0.0500) BSC


1.75 (0.0688)

1.35 (0.0532)

0.50 (0.0196)

0.25 (0.0099)


45°

COPLANARITY

0.51 (0.0201)


1.27 (0.0500)

0.10

SEATING PLANE

0.31 (0.0122)

0.25 (0.0098)

0.17 (0.0067)

0.40 (0.0157)


COMPLIANT TO JEDEC STANDARDS MS-012-AA

012407-A

CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.

Figure 115. 8-Lead Standard Small Outline Package [SOIC_N]

Narrow Body (R-8)

Dimensions shown in millimeters and (inches)

3.00

2.90

2.80



1.70

1.60

1.50


5


4

1 2 3

3.00

2.80

2.60



1.30

1.15

0.90


1.90 BSC

0.95 BSC


1.45 MAX

0.95 MIN


0.20 MAX

0.08 MIN


0.55

0.15 MAX

0.05 MIN


0.50 MAX

0.35 MIN


SEATING PLANE

10°

5°


0.60

BSC

0.45

0.35


11-01-2010-A

COMPLIANT TO JEDEC STANDARDS MO-178-AA

Figure 116. 5-Lead Small Outline Transistor Package [SOT-23] (RJ-5)

Dimensions shown in millimeters


3.20

3.00

2.80



3.20

3.00

2.80

8 5 5.15

4.90

4.65

1 4


PIN 1 IDENTIFIER


0.65 BSC


0.95

0.85

0.75

0.15

0.05

COPLANARITY 0.10


0.40

0.25


1.10 MAX



15° MAX


0.23

0.09


0.80

0.55

10-07-2009-B

0.40


COMPLIANT TO JEDEC STANDARDS MO-187-AA

Figure 117. 8-Lead Mini Small Outline Package [MSOP] (RM-8)

Dimensions shown in millimeters



3.10

3.00 SQ 2.90


2.44

2.34

2.24


DETAIL A (JEDEC 95)


0.50 BSC



PIN 1 INDEX

AREA


0.50

0.40

0.30


5 8


EXPOSED PAD


4 1


1.70

1.60

1.50


0.20 MIN

TOP VIEW

BOTTOM VIEW


PIN 1

INDIC ATOR AREA OPTIONS (SEE DETAIL A)


0.80

0.75

0.70


SEATING PLANE


SIDE VIEW


0.30

0.25

0.20


0.05 MAX

0.02 NOM

COPLANARITY

0.08

0.203 REF


FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET


PKG-005136

02-10-2017-C

COMPLIANT TO JEDEC STANDARDS MO-229-W3030D-4

Figure 118. 8-Lead Lead Frame Chip Scale Package [LFCSP] 3 mm × 3 mm Body and 0.75 mm Package Height

(CP-8-11)

Dimensions shown in millimeters



PIN 1 INDICATOR


4.10

4.00 SQ 3.90


0.65

BSC


0.35

0.30

0.25


13


12


DETAIL A (JEDEC 95)


PIN 1

16

INDIC ATOR AREA OPTIONS (SEE DETAIL A)


1

2.70

EXPOSED PAD

2.60 SQ 2.50

4

9


TOP VIEW

0.45 0.40

0.35


8 5

BOTTOM VIEW

0.20 MIN

0.80

0.75

0.70


SEATING


SIDE VIEW


0.05 MAX

0.02 NOM

02-22-2017-C

COPLANARITY 0.08


FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET.

PLANE

0.20 REF


PKG-004828

COMPLIANT TO JEDEC STANDARDS MO-220-WGGC.

Figure 119. 16-Lead Lead Frame Chip Scale Package [LFCSP] 4 mm × 4 mm Body and 075 mm Package Height

(CP-16-17)

Dimensions shown in millimeters


5.10

5.00

4.90



4.50

4.40

4.30


14 8


6.40

BSC

1 7


PIN 1


1.05

1.00


0.65 BSC


1.20


0.20

0.80

MAX

0.09 0.75

0.15

0.05 0.30

SEATING

PLANE

0.60

0.45

COPLANARITY 0.10

0.19


061908-A

COMPLIANT TO JEDEC STANDARDS MO-153-AB-1


Figure 120. 14-Lead Thin Shrink Small Outline Package [TSSOP] (RU-14)

Dimensions shown in millimeters

ORDERING GUIDE

Model1

Temperature Range

Package Description

Package Option

Branding

ADA4084-1ARZ ADA4084-1ARZ-R7 ADA4084-1ARZ-RL ADA4084-1ARJZ-R2 ADA4084-1ARJZ-R7

ADA4084-1ARJZ-RL

−40°C to +125°C

−40°C to +125°C

−40°C to +125°C

−40°C to +125°C

−40°C to +125°C

−40°C to +125°C

8-Lead Standard Small Outline Package [SOIC_N] 8-Lead Standard Small Outline Package [SOIC_N] 8-Lead Standard Small Outline Package [SOIC_N] 5-Lead Small Outline Transistor Package [SOT-23] 5-Lead Small Outline Transistor Package [SOT-23]

5-Lead Small Outline Transistor Package [SOT-23]

R-8

R-8

R-8 RJ-5 RJ-5 RJ-5


A38 A38 A38

ADA4084-2ARMZ ADA4084-2ARMZ-R7 ADA4084-2ARMZ-RL ADA4084-2ARZ ADA4084-2ARZ-R7 ADA4084-2ARZ-RL ADA4084-2ACPZ-R7

ADA4084-2ACPZ-RL

−40°C to +125°C

−40°C to +125°C

−40°C to +125°C

−40°C to +125°C

−40°C to +125°C

−40°C to +125°C

−40°C to +125°C

−40°C to +125°C

8-Lead Mini Small Outline Package [MSOP] 8-Lead Mini Small Outline Package [MSOP] 8-Lead Mini Small Outline Package [MSOP]

8-Lead Standard Small Outline Package [SOIC_N] 8-Lead Standard Small Outline Package [SOIC_N] 8-Lead Standard Small Outline Package [SOIC_N] 8-Lead Lead Frame Chip Scale Package [LFCSP]

8-Lead Lead Frame Chip Scale Package [LFCSP]

RM-8 RM-8 RM-8 R-8

R-8

R-8

CP-8-11 CP-8-11

A2Q A2Q A2Q


A2Q A2Q

ADA4084-4ACPZ-R7 ADA4084-4ACPZ-RL ADA4084-4ARUZ

ADA4084-4ARUZ-RL

−40°C to +125°C

−40°C to +125°C

−40°C to +125°C

−40°C to +125°C

16-Lead Lead Frame Chip Scale Package [LFCSP] 16-Lead Lead Frame Chip Scale Package [LFCSP]

14-Lead Thin Shrink Small Outline Package [TSSOP]

14-Lead Thin Shrink Small Outline Package [TSSOP]

CP-16-17 CP-16-17 RU-14

RU-14


1 Z = RoHS Compliant Part.


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D08237-0-5/17(I)

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ADA4084-2ARMZ ADA4084-2ARMZ-R7 ADA4084-2ARZ ADA4084-2ARZ-R7 ADA4084-2ACPZ-R7 ADA4084- 2ACPZ-RL ADA4084-2ARMZ-RL ADA4084-2ARZ-RL ADA4084-4ARUZ ADA4084-1ARZ ADA4084-4ARUZ-RL ADA4084-4ACPZ-RL ADA4084-4ACPZ-R7 ADA4084-1ARZ-RL ADA4084-1ARZ-R7 ADA4084-1ARJZ-R2 ADA4084- 1ARJZ-RL ADA4084-1ARJZ-R7 5962R1523601VXA