DATASHEET
ISL28194
Ultra-Small, 330nA and 1µA Single Supply, Rail-to-Rail Input/Output (RRIO) Op Amps
FN6236 Rev 5.00
January 14, 2014
The ISL28194 is micropower op amps optimized for low-power applications. The part is designed for
single-supply operation from 1.8V to 5.5V, making it suitable for applications with two 1.5V alkaline batteries. The ISL28194 consumes typically 330nA of supply current . The part feature rail-to-rail input and output swing (RRIO), allowing for maximum battery usage.
Equipped with a shutdown pin, the part draw typically 2nA when off. The combination of small footprint, low power, single supply, and rail-to-rail operation makes it ideally suited for all battery operated device.
Typical Supply Current 330nA
Ultra-Low Single-Supply Operation Down to +1.8V
Rail-to-Rail Input/Output Voltage Range (RRIO)
Maximum 2mV Offset Voltage
Maximum 60pA Input Bias Current
3.5kHz Gain Bandwidth Product
ENABLE Pin Feature
-40°C to +125°C Operation
Pb-Free (RoHS Compliant)
OUT 1
ISL28194 (6 LD SOT-23)
TOP VIEW
6 V+
2-Cell Alkaline Battery-Powered/Portable Systems
Window Comparators
V- 2
+ -
5 EN
Threshold Detectors/Discriminators
IN+ 3
ISL28194
4 IN-
Mobile Communications
Low Power Sensors
(6 LD 1.6X1.6X0.5 UTDFN)
+ - | ||
1 | 6 | |
2 | 5 | |
3 | 4 | |
TOP VIEW
IN-
V- IN+
V+ EN OUT
FN6236 Rev 5.00 Page 1 of 12
PART MARKING | PACKAGE Tape and Reel (Pb-Free) | PKG. DWG. # | |
6 Ld SOT-23 | P6.064A | ||
M3 | 6 Ld 1.6x1.6x0.5 UTDFN | L6.1.6x1.6A | |
ISL28194EVAL1Z | Evaluation Board |
NOTES:
Please refer to TB347 for details on reel specifications.
The part marking is located on the bottom of the part.
Absolute Maximum Ratings (TA = +25°C) Thermal Information
Supply Voltage (V+, V-) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.75V
Supply Turn On Voltage Slew Rate . . . . . . . . . . . . . . . . . . . . . 1V/s
Differential Input Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5mA Differential Input Voltage . . . . . . . . . . . . . . . . V- - 0.5V to V+ + 0.5V ESD Rating
Human Body Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3kV
Machine Model. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .300V
Thermal Resistance (Typical, Note 5) JA (°C/W) 6 Ld SOT-23. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230
6 Ld UTDFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
Output Short-Circuit Duration . . . . . . . . . . . . . . . . . . . . . . .Indefinite Ambient Operating Temperature Range . . . . . . . . .-40°C to +125°C Storage Temperature Range . . . . . . . . . . . . . . . . . .-65°C to +150°C
Operating Junction Temperature . . . . . . . . . . . . . . . . . . . . . +125°C
Pb-Free Reflow Profile. . . . . . . . . . . . . . . . . . . . . . . . .see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty.
NOTE:
JA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typical values are for information purposes only. Unless otherwise noted, all tests are at the specified temperature and are pulsed tests, therefore: TJ = TC = TA
Electrical Specifications V+ = 5V, V- = 0V, VCM = 2.5V, TA = +25°C, Unless Otherwise Specified.
Boldface limits apply over -40°C to +125°C.
PARAMETER | DESCRIPTION | CONDITIONS | MIN (Note 6) | TYP | MAX | UNIT |
VOS | Input Offset Voltage | -2 -2.5 | -0.1 | 2 2.5 | mV mV | |
VOS ---------------- T | Input Offset Voltage vs Temperature | 1.5 | µV/°C | |||
IOS | Input Offset Current | -60 -100 | 10 | 60 100 | pA pA | |
IB | Input Bias Current | -80 -150 | 15 | 80 150 | pA pA | |
eN | Input Noise Voltage Peak-to-Peak | f = 0.1Hz to 10Hz | 10 | µVP-P | ||
Input Noise Voltage Density | fo = 100Hz | 265 | nV/Hz | |||
iN | Input Noise Current Density | fo = 100Hz | 0.7 | pA/Hz | ||
CMIR | Common Mode Input Range | Established by CMRR test | 0 | 5 | V | |
CMRR | Common-Mode Rejection Ratio | VCM = 0.5V to 3.5V | 70 70 | 100 | dB | |
VCM = 0V to 5V | 55 | 90 | dB | |||
PSRR | Power Supply Rejection Ratio | V+ = 1.8V to 5.5V | 70 70 | 100 | dB | |
AVOL | Large Signal Voltage Gain | VO = 0.5V to 3.5V, RL = 100k, RL = 10k | 75 | 115 | dB | |
VOUT | Maximum Output Voltage Swing RL terminated to V+/2 | Output low, RL = 100k | 25 | 40 | mV | |
Output low, RL = 10k | 50 | 70 | mV | |||
Output high, RL = 100k | 4.96 | 4.975 | V | |||
Output high, RL = 10k | 4.93 | 4.94 | V | |||
SR | Slew Rate | ±1.5V, AV = 2 | 1.2 | V/ms | ||
GBW | Gain Bandwidth Product | AV = 101; RL = 10k | 3.5 | kHz | ||
IS,ON | Supply Current, Enabled | 330 | 450 500 | nA | ||
IS,OFF | Supply Current, Disabled | EN = 0.4V | 2 | 20 50 | nA nA | |
ISC+ | Short Circuit Sourcing Capability | RL = 10 | 9 | 11 | mA |
Electrical Specifications V+ = 5V, V- = 0V, VCM = 2.5V, TA = +25°C, Unless Otherwise Specified.
Boldface limits apply over -40°C to +125°C. (Continued)
PARAMETER | DESCRIPTION | CONDITIONS | MIN (Note 6) | TYP | MAX (Note 6) | UNIT |
ISC- | Short Circuit Sinking Capability RL terminated to V+/2 | RL = 10 | 11 | 12 | mA | |
V+ | Supply Voltage Range | 1.8 | 5.5 | V | ||
ENABLE INPUT | ||||||
VINH | Enable Pin High Level | (V+)x(0.8) | V | |||
VINL | Enable Pin Low Level | 0.4 | V | |||
IENH | Enable Pin Input Current | VEN = 5V | 30 | 150 200 | nA | |
IENL | Enable Pin Input Current | VEN = 0V | 30 | 150 200 | nA |
NOTE:
Typical Performance Curves V+ = 5V, V- = 0V, VCM = 2.5V, Unless Otherwise Specified.
1
0
-1 GAIN
-2
GAIN (dB)
-3
-4
-5
-6 V+ = 5V
-7 RL = 10k AV = +1
-8 VOUT = 10mVP-P
-9
10 100 1k 10k
FREQUENCY (Hz)
10
0
CMRR (dB)
-10
-20
-30
-40
-50
-60
V+ = 5V RL = 10k
CMRR
AV = +1
VSOURCE = 1VP-P
10 100 1k 10k FREQUENCY (Hz)
FIGURE 1. CLOSE LOOP GAIN vs FREQUENCY FIGURE 2. CMRR vs FREQUENCY
10
0
-10
PSRR (dB)
-20
-30
-40
-50
-60
-70
-80
V+ = 5V
RL = 10k AV = +1
VSOURCE = 1VP-P
PSRR-
PSRR+
5
4
3
INPUT NOISE (µV)
2
1
0
-1
-2
-3 V+ = 5V
RL = 10k
-4 AV = 1000
-5
10 100 1k 10k
FREQUENCY (Hz)
0 1 2 3 4 5 6 7 8 9 10
TIME (s)
FIGURE 3. PSRR vs FREQUENCY FIGURE 4. 0.1Hz TO 10Hz INPUT VOLTAGE NOISE
Typical Performance Curves V+ = 5V, V- = 0V, VCM = 2.5V, Unless Otherwise Specified. (Continued)
V+ = 5V RL = INF AV = +1 | |||||||
240
235
SUPPLY CURRENT (nA)
230
225
220
215
210
205
200
195
1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
SUPPLY VOLTAGE (V)
20
V+ = 5V RL = 10 AV = +1 | |||||||
SINK | |||||||
SOURCE | |||||||
18
OUTPUT CURRENT (mA)
16
14
12
10
8
6
4
2
0
1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
SUPPLY VOLTAGE (V)
FIGURE 5. SUPPLY CURRENT vs SUPPLY VOLTAGE FIGURE 6. OUTPUT SHORT CIRCUIT CURRENT
0.007
OUTPUT VOLTAGE (mV)
0.005
0.003
0.001
-0.001
-0.003
-0.005
-0.007
INPUT
3
OUTPUT VOLTAGE (V)
V+, V- = ±2.5V | ||||||||||
RL = 10k AV = +1 | ||||||||||
LARGE SIGNAL | ||||||||||
2
OUTPUT
1
0
V+, V- = ±2.5V -1
RL = 10k
AV = +1 -2
VOUT = 10mVP-P
-3
-3.00E-04 -1.00E-04 1.00E-04 3.00E-04 5.00E-04 7.00E-04 9.00E-04
TIME (ms)
-2.0 -10 0 10 20 30 40 50 60 70 80
TIME (ms)
FIGURE 7. SMALL SIGNAL TRANSIENT RESPONSE FIGURE 8. LARGE SIGNAL TRANSIENT RESPONSE
EN PIN | |||||||
OUTPUT | |||||||
V+ = 5V RL = 10k AV = +1 VIN = 3.5V | |||||||
6
5
ENABLE/OUTPUT (V)
4
3
2
1
0
-4 -2 0 2 4 6 8 10
TIME (ms)
6
EN PIN | V+ = 5V RL = 10k AV = +1 VIN = 3.5V | |||||||
OUTPUT | ||||||||
5
ENABLE/OUTPUT (V)
4
3
2
1
0
-1.0 -0.5 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5
TIME (µs)
FIGURE 9. ENABLE TO OUTPUT DELAY TIME FIGURE 10. DISABLE TO OUTPUT DELAY TIME
Typical Performance Curves V+ = 5V, V- = 0V, VCM = 2.5V, Unless Otherwise Specified. (Continued)
2.6
ENABLE THRESHOLD (V)
2.4
2.2
2.0
1.8
1.6
1.4
1.2
1.0
1.5 2.0 2.5
3.0
3.5 4.0 4.5 5.0
70
ENABLE TO OUTPUT DELAY (ms)
60
50
40
30
20
10
0
1.5 2.0 2.5
3.0
3.5 4.0 4.5 5.0
SUPPLY VOLTAGE (V)
FIGURE 11. ENABLE THRESHOLD VOLTAGE vs SUPPLY VOLTAGE
SUPPLY VOLTAGE (V)
FIGURE 12. ENABLE TO OUTPUT DELAY TIME vs SUPPLY VOLTAGE
50000
DISABLE TO OUTPUT DELAY (ns)
45000
40000
35000
30000
25000
20000
15000
10000
5000
0
1.5 2.0 2.5
3.0
3.5 4.0 4.5 5.0
450
SUPPLY CURRENT (nA)
N = 1000 | MAX | |||||||
MEDIAN | ||||||||
MIN |
400
350
300
250
200
-40 -20 0 20 40 60 80 100 120
SUPPLY VOLTAGE (V)
FIGURE 13. ENABLE LOW TO OUTPUT TURN-OFF TIME vs SUPPLY VOLTAGE
TEMPERATURE (°C)
FIGURE 14. SUPPLY CURRENT ENABLED vs TEMPERATURE, V+ = 5V, V- = 0V
N = 1000
N==110000 | ||||||||
MAX | ||||||||
MEDIAN | ||||||||
MIN | ||||||||
35 30
30 25
IBIAS + (pA)
25
20 MAX
MEDIAN
15
10
5
0
20
IBIAS - (pA)
15
10
5
MIN 0
-5
-40 -20 0 20 40 60 80 100 120
TEMPERATURE (°C)
-40 -20 0 20 40 60 80 100 120
TEMPERATURE (°C)
FIGURE 15. IBIAS + vs TEMPERATURE V+ = 5V FIGURE 16. BIAS vs TEMPERATURE, V+ = 2.4V
Typical Performance Curves V+ = 5V, V- = 0V, VCM = 2.5V, Unless Otherwise Specified. (Continued)
30
20
IOS (pA)
10
0
-10
-20
-30
N = 1000
MAX
MEDIAN
MIN
-30
N = 1000 | ||||||||
MEDIAN VIN = 2.5V | ||||||||
MEDIAN VIN = 4.7V | ||||||||
-50
-70
VOS (µV)
-90
-110
-130
-150
-170
-40 -20 0 20 40 60 80 100 120
TEMPERATURE (°C)
-40 -20 0 20 40 60 80 100 120
TEMPERATURE (°C)
FIGURE 17. IOS vs TEMPERATURE, V+ = 5V FIGURE 18. VOS vs TEMPERATURE, V+ = 5V VIN = 2.5V, 4.7V
N = 1000 | ||||||||
MEDIAN VIN = 1.5V | ||||||||
MEDIAN VIN = 0.3V | ||||||||
0
-20
-40
-60
VOS (µV)
-80
-100
-120
-140
-160
-180
-200
-40 -20 0 20 40 60 80 100 120
TEMPERATURE (°C)
100
N = 1000 | ||||||||
MEDIAN VCM: +1.0V TO -2.0V | ||||||||
MEDIAN VCM: +5.1V TO -0.1V | ||||||||
98
96
CMRR (dB)
94
92
90
88
86
84
-40 -20 0 20 40 60 80 100 120
TEMPERATURE (°C)
FIGURE 19. VOS vs TEMPERATURE, V+ = 1.8V,VIN = 1.5V, 0.3V FIGURE 20. CMRR vs TEMPERATURE, VCM = +1.0V TO -2.0V,
+5.1V TO -0.1V
140
130
120
PSRR (dB)
110
100
90
80
70
60
N = 1000 | ||||||||
MAX | ||||||||
MEDIAN | ||||||||
MIN | ||||||||
50
118
116
AVOL (dB)
114
112
110
108
106
N = 1000
MEDIAN RL = 10k
MEDIAN RL = 100k
-40 -20 0 20 40 60 80 100 120
TEMPERATURE (°C)
-40 -20 0 20 40 60 80 100 120
TEMPERATURE (°C)
FIGURE 21. PSRR vs TEMPERATURE, V+, V- = ±0.9V TO ±2.5V FIGURE 22. AVOL vs TEMPERATURE, V+ = 5V
Typical Performance Curves V+ = 5V, V- = 0V, VCM = 2.5V, Unless Otherwise Specified. (Continued)
N = 1000 | ||||||||
MEDIAN RL = 100k | ||||||||
MEDIAN RL = 10k | ||||||||
94
92
90
AVOL (dB)
88
86
84
82
80
78
76
-40 -20 0 20 40 60 80 100 120
TEMPERATURE (°C)
4.995
N = 1000 | ||||||||
MAX | ||||||||
MEDIAN | ||||||||
MIN | ||||||||
4.990
4.985
VOUT (V)
4.980
4.975
4.970
4.965
4.960
4.955
4.950
-40 -20 0 20 40 60 80 100 120
TEMPERATURE (°C)
FIGURE 23. AVOL vs TEMPERATURE, V+ = 1.8V FIGURE 24. VOUT HIGH vs TEMPERATURE, V+ = 5V, RL = 100k
4.944
4.942
4.940
VOUT (V)
4.938
4.936
4.934
4.932
4.930
4.928
N = 1 | 000 | |||||||
MAX | ||||||||
MEDIAN | ||||||||
MIN | ||||||||
4.926
35
N = 1000
30
VOUT (mV)
25
20
15
10
MAX
MEDIAN
MIN
-40 -20 0 20 40 60 80 100 120
TEMPERATURE (°C)
-40 -20 0 20 40 60 80 100 120
TEMPERATURE (°C)
FIGURE 25. VOUT HIGH vs TEMPERATURE, V+ = 5V, RL = 10k FIGURE 26. VOUT LOW vs TEMPERATURE,V+, V- = ±2.5V,
RL = 100k
N = 1000
57
56
55
VOUT (mV)
54 MAX
53
MEDIAN
52
51
50
49
48
47
MIN
-40 -20 0 20 40 60 80 100 120
TEMPERATURE (°C)
FIGURE 27. VOUT LOW vs TEMPERATURE V+, V- = ±2.5V, RL = 10
ISL28194 (6 LD SOT-23) | ISL28194 (6 LD ΜTDFN) | PIN NAME | EQUIVALENT CIRCUIT | DESCRIPTION |
1 | 4 | OUT_A | Circuit 3 | Amplifier output |
2 | 2 | V- | Circuit 4 | Negative power supply |
3 | 3 | IN+ | Circuit 1 | Amplifier non-inverting input |
4 | 1 | IN- | Circuit 1 | Amplifier inverting input |
5 | 5 | EN | Circuit 2 | Amplifier enable pin; Logic “1” selects the enabled state, Logic “0” selects the disabled state. |
6 | 6 | V+ | Circuit 4 | Positive power supply |
IN-
V+
IN+ V-
V+
LOGIC PIN
V-
100
V+ V+
CAPACITIVELY COUPLED
ESD CLAMP
OUT
V-
V-
CIRCUIT 1 CIRCUIT 2
CIRCUIT 3
CIRCUIT 4
VIN
5V
-
+
10k
EN
VOUT
1k
10 5V
-
+
VIN
EN
10k
VOUT
V+/2
VCM = V+/2
FIGURE 28. TEST CIRCUIT FOR AV = +1 FIGURE 29. TEST CIRCUIT FOR AV = +101
Introduction
The ISL28194 is a CMOS rail-to-rail input and output (RRIO) micropower operational amplifier. This device is designed to operate from single supply (1.8V to 5.5V) and has an input common mode range that extends to the positive rail and to the negative supply rail for true rail-to-rail performance. The CMOS output can swing within tens of millivolts to the rails. Featuring worst-case maximum supply current of 0.5µA, this amplifier is ideally suited for solar and battery-powered applications.
Input Protection
All input terminals have internal ESD protection diodes to both positive and negative supply rails, limiting the input voltage to within one diode beyond the supply rails. The ISL28194 has a maximum input differential voltage that includes the rails (-V - 0.5V to +V +0.5V).
Rail-to-Rail Output
A pair of complementary MOSFET devices are used to achieve the rail-to-rail output swing. The NMOS sinks current to swing the output in the negative direction. The PMOS sources current to swing the output in the positive direction. The ISL28194 will typically swing to within 40mV or less to either rail with a 100k load (reference Figures 24 and 26).
Enable/Disable Feature
This part offers an EN pin that enables the device when pulled high. The enable threshold is referenced to the -V terminal and has a level proportional to the total supply voltage (reference Figure 11 for EN threshold vs supply voltage). The enable circuit has a delay time that changes as a function of supply voltage. Figures 12 and 13 show the effect of supply voltage on the enable and disable times. For supply voltages less than 3V, it is recommended that the user account for the increase enable/disable delay time.
In the disabled state (output in a high impedance state), the supply current is reduced to typical of only 2nA. By disabling the devices, multiple parts can be connected together as a MUX. In this configuration, the outputs are tied together in parallel and a channel can be selected by the EN pin. The EN pin should never be left floating. The EN pin should be connected directly to the V+ supply when not in use.
The loading effects of the feedback resistors of the disabled
Power Dissipation
It is possible to exceed the +150°C maximum junction temperatures under certain load and power-supply conditions. It is therefore important to calculate the maximum junction temperature (TJMAX) for all applications to determine if power supply voltages, load conditions, or package type need to be modified to remain in the safe operating area. These parameters are related in Equation 1:
amplifier must be considered when multiple amplifier outputs are connected together.
Proper Layout Maximizes Performance
To achieve the maximum performance of the high input
TJMAX = TMAX + JAxPDMAXTOTAL
where:
PDMAXTOTAL is the sum of the maximum power
(EQ. 1)
impedance, care should be taken in the circuit board layout. The PC board surface must remain clean and free of moisture to avoid leakage currents between adjacent traces. Surface coating of the circuit board will reduce surface moisture and
provide a humidity barrier, reducing parasitic resistance on the
dissipation of each amplifier in the package (PDMAX)
PDMAX for each amplifier can be calculated as shown in Equation 2:
VO UTM AX
L
PDMAX = 2*VS ISMAX + VS - VOUTMAX ---------------------------
board. When input leakage current is a concern, the use of guard rings around the amplifier inputs will further reduce leakage currents. Figure 30 shows a guard ring example for a unity gain amplifier that uses the low impedance amplifier output at the same voltage as the high impedance input to eliminate surface leakage. The guard ring does not need to be
where:
TMAX = Maximum ambient temperature
JA = Thermal resistance of the package
R
a specific width, but it should form a continuous loop around both inputs. For further reduction of leakage currents, components can be mounted to the PC board using Teflon standoff insulators.
HIGH IMPEDANCE INPUT V+ IN
PDMAX = Maximum power dissipation of 1 amplifier
VS = Supply voltage (Magnitude of V+ and V-)
IMAX = Maximum supply current of 1 amplifier
VOUTMAX = Maximum output voltage swing of the application
RL = Load resistance
FIGURE 30. GUARD RING EXAMPLE FOR UNITY GAIN AMPLIFIER
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For additional products, see www.intersil.com/en/products.html
Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted in the quality certifications found at www.intersil.com/en/support/qualandreliability.html
Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
PIN 1 REFERENCE
0.15
2X
E A B
6 4
D
A
6 LEAD ULTRA THIN DUAL FLAT NO-LEAD PLASTIC PACKAGE
C
SYMBOL | MILLIMETERS | NOTES | ||
MIN | NOMINAL | MAX | ||
A | 0.45 | 0.50 | 0.55 | - |
A1 | - | - | 0.05 | - |
A3 | 0.127 REF | - | ||
b | 0.15 | 0.20 | 0.25 | - |
D | 1.55 | 1.60 | 1.65 | 4 |
D2 | 0.40 | 0.45 | 0.50 | - |
E | 1.55 | 1.60 | 1.65 | 4 |
E2 | 0.95 | 1.00 | 1.05 | - |
e | 0.50 BSC | - | ||
L | 0.25 | 0.30 | 0.35 | - |
1 3
C
0.15
2X
TOP VIEW A1
e
1.00 REF
4 6
L
D2 CO.2
3 1
E2
BOTTOM VIEW
DAP SIZE 1.30 x 0.76
b 6X
0.10 M | C | A | B | ||
NOTES:
Dimensions are in MM. Angles in degrees.
Rev. 1 6/06
0.10 C
6X 0.08 C
SIDE VIEW
DETAIL A
A3 C SEATING PLANE
Coplanarity applies to the exposed pad as well as the terminals. Coplanarity shall not exceed 0.08mm.
Warpage shall not exceed 0.10mm.
Package length/package width are considered as special characteristics.
JEDEC Reference MO-229.
For additional information, to assist with the PCB Land Pattern Design effort, see Intersil Technical Brief TB389.
0.127±0.008
0.127 +0.058
-0.008
TERMINAL THICKNESS
A1
DETAIL A
0.25
0.50
1.00 0.45
1.00
2.00
0.30
1.25
LAND PATTERN 6
P6.064A
6 LEAD SMALL OUTLINE TRANSISTOR PLASTIC PACKAGE
Rev 0, 2/10
1.90
0.95
0-3°
D 0.08-0.20
A
6 5 4
PIN 1 INDEX AREA
3
1.60
2.80
3 5
0.15 C D
2x 1 2
B
3
0.20 M | C | A-B | D |
0.40 ±0.05
0.20 C 2x
3
SEE DETAIL X
(0.60)
TOP VIEW END VIEW
10° TYP
A-B
C
0.15
2.90
5 (2 PLCS)
2x
H
1.14 ±0.15
1.45 MAX
C
SIDE VIEW
0.05-0.15
C
0.10
SEATING PLANE
(0.25) GAUGE
PLANE
DETAIL "X" 0.45±0.1 4
(0.60)
(1.20)
NOTES:
(2.40)
(0.95)
Dimensions are in millimeters. Dimensions in ( ) for Reference Only.
Dimensioning and tolerancing conform to ASME Y14.5M-1994.
Dimension is exclusive of mold flash, protrusions or gate burrs.
Foot length is measured at reference to guage plane.
This dimension is measured at Datum “H”.
Package conforms to JEDEC MO-178AA.
(1.90)
TYPICAL RECOMMENDED LAND PATTERN
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