Data Sheet
Low power
250 µA maximum supply current per amplifier FET input
2 pA maximum input bias current at 25°C Extremely high input impedance
Low noise
13 nV/√Hz voltage noise at 1 kHz
0.4 µV p-p voltage noise (0.1 Hz to 10 Hz)
0.8 fA/√Hz current noise at 1 kHz High dc precision
3 µV/°C maximum offset drift (B grade) 3 MHz bandwidth
Unique pinout
No leakage from inputs to supply pins Provides guarding capability
Rail-to-rail output Single-supply operation
Input range extends to ground Wide supply range
Single-supply: 3 V to 36 V
Dual-supply: ±1.5 V to ±18 V Available in a compact 10-lead MSOP
Biopotential electrodes Medical instrumentation
High impedance sensor conditioning Filters
Photodiode amplifiers
The AD8244 is a precision, low power, FET input, quad unity-gain buffer that is designed to isolate very large source impedances from the rest of the signal chain. The 2 pA maximum bias current, near zero current noise, and 10 TΩ input impedance introduce almost no error, even with source impedance well into the megaohms.
Many traditional operational amplifier pinouts have a supply pin that is next to the noninverting input. A guard trace must be routed between these pins to avoid leakage currents much larger than the bias current of a FET input op amp. Guard traces can be routed between pins for large packages, such as DIP or even SOIC; however, the board area consumed by these packages is prohibitive for many modern applications. The AD8244 solves this problem with a unique pinout that physically separates the
AD8244
IN A | 1 | 10 | IN D |
OUT A | 2 | 9 | OUT D |
+VS | 3 | 8 | –VS |
OUT B | 4 | 7 | OUT C |
IN B | 5 | 6 | IN C |
11689-001
Figure 1. Pinout Isolates Inputs from Low-Impedance Leakage Sources
1s/DIV | |||||||||
200nV/DIV |
11689-002
Figure 2. 0.1 Hz to 10 Hz Voltage Noise
high impedance inputs from the low impedance supplies and outputs of the other buffers. This configuration simplifies guarding while reducing board space, allowing high performance and high density in the same design.
The AD8244 design is focused on solving problems specific to buffers. This includes close channel-to-channel matching which allows channels of the AD8244 to be used in differential signal chains with minimal error. With its low voltage noise, wide supply range, and high precision, the AD8244 is also flexible enough to provide high performance anywhere a unity-gain buffer is needed, even with low source resistance.
The AD8244 is specified over the industrial temperature range of −40°C to +85°C. It is available in a 10-lead MSOP package.
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibilityisassumedby AnalogDevices foritsuse, norforanyinfringementsofpatentsor other rightsofthirdpartiesthatmayresultfromitsuse. Specificationssubjecttochangewithoutnotice.No license isgranted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 ©2013–2014 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com
Pin Configuration and Function Descriptions 7
Typical Performance Characteristics 8
Low Output Impedance vs. Frequency 15
Low Noise, JFET Input Buffer 18
12/14—Rev. 0 to Rev. A
Added Figure 1 Caption and Changes to Figure 2 1
Changes to Low Output Impedance vs. Frequency Section 15
Changes to Electrocardiogram (ECG) Section, Filtering Section, Figure 42, and Figure 43 16
Changes to Figure 44 17
Changes to Ordering Guide 19
10/13—Revision 0: Initial Version
+VS = 5 V, –VS = 0 V, TA = 25°C, VIN = 0.2 V, RL = 10 kΩ to ground, unless otherwise noted.
Table 1.
Parameter | Test Conditions/Comments | Min | AD8244A Typ | Max | Min | AD8244B Typ | Max | Unit |
DC PERFORMANCE Offset Voltage Over Temperature Average Temperature Coefficient Offset Voltage Matching Input Bias Current Over Temperature Input Bias Current Matching Over Temperature | 100 | 600 | 100 | 350 | µV | |||
TA = −40°C to +85°C | 1.25 | 0.675 | mV | |||||
TA = −40°C to +85°C | 10 | 5 | µV/°C | |||||
Channel to channel | 800 | 500 | µV | |||||
0.5 | 10 | 0.5 | 2 | pA | ||||
TA = 85°C | 150 | 50 | pA | |||||
Channel to channel | 0.05 | 0.05 | 0.2 | pA | ||||
TA = 85°C | 2 | 2 | pA | |||||
SYSTEM PERFORMANCE Nominal Gain System Error1 Average Temperature Coefficient Gain Matching | 1 | 1 | V/V | |||||
VOUT = 0.2 V to 3 V | 0.08 | 0.05 | % | |||||
TA = −40°C to +85°C | 2 | 1 | ppm/°C | |||||
Channel to channel | 0.10 | 0.08 | % | |||||
NOISE PERFORMANCE Voltage Noise Spectral Density Peak-to-Peak Current Noise Spectral Density Peak-to-Peak | f = 1 kHz | 13 | 13 | nV/√Hz | ||||
f = 0.1 Hz to 10 Hz | 0.4 | 0.4 | 2 | µV p-p | ||||
f = 1 kHz | 0.8 | 0.8 | fA/√Hz | |||||
f = 0.1 Hz to 10 Hz | 8 | 8 | fA p-p | |||||
DYNAMIC PERFORMANCE | ||||||||
Small Signal Bandwidth | −3 dB | 3 | 3 | MHz | ||||
Slew Rate | 0.8 | 0.8 | V/µs | |||||
Settling Time to 0.01% | VOUT = 0.2 V to 3 V | 8 | 8 | µs | ||||
INPUT CHARACTERISTICS Input Voltage Range2 Over Temperature Input Impedance3 | 0 | 4 | 0 | 4 | V | |||
TA = −40°C to +85°C | 0 | 3.5 | 0 | 3.5 | V | |||
10||4 | 10||4 | TΩ||pF | ||||||
OUTPUT CHARACTERISTICS Output Swing Over Temperature Output Swing Over Temperature Short-Circuit Current Capacitive Load Drive | RL = 10 kΩ to ground | 0.025 | 4.9 | 0.025 | 4.9 | V | ||
TA = −40°C to +85°C | 0.03 | 4.88 | 0.03 | 4.88 | V | |||
RL = no load | 0.025 | 4.97 | 0.025 | 4.97 | V | |||
TA = −40°C to +85°C | 0.03 | 4.95 | 0.03 | 4.95 | V | |||
8 | 8 | mA | ||||||
200 | 200 | pF | ||||||
POWER SUPPLY Operating Range Power Supply Rejection Supply Current per Amplifier Over Temperature | Single supply Dual supply VIN = 2.5 V, +VS = 4.5 V to 5.5 V IOUT = 0 mA TA = −40°C to +85°C | 3 ±1.5 | 80 180 | 36 ±18 250 300 | 3 ±1.5 | 80 180 | 36 ±18 250 300 | V V dB µA µA |
TEMPERATURE RANGE Specified Performance | −40 | +85 | −40 | +85 | °C |
1 Error as a percentage of the measurement. This includes the effects of open-loop gain and common-mode rejection ratio.
2 The inputs of the AD8244 can go up to the positive supply; however, the input range is derated because error increases near the positive supply as the input transistors start to saturate. The inputs also maintain high impedance when driven slightly below ground.
VS = ±5 V, TA = 25°C, VIN = 0 V, RL = 10 kΩ, unless otherwise noted.
Table 2.
Parameter | Test Conditions/Comments | AD8244A Min Typ Max | AD8244B Min Typ Max | Unit |
DC PERFORMANCE Offset Voltage Over Temperature Average Temperature Coefficient Offset Voltage Matching Input Bias Current Over Temperature Input Bias Current Matching Over Temperature | 100 600 | 100 350 | µV | |
TA = −40°C to +85°C | 1.25 | 0.675 | mV | |
TA = −40°C to +85°C | 10 | 5 | µV/°C | |
Channel to channel | 800 | 500 | µV | |
0.5 10 | 0.5 2 | pA | ||
TA = 85°C | 150 | 50 | pA | |
Channel to channel | 0.05 | 0.05 0.2 | pA | |
TA = 85°C | 2 | 2 | pA | |
SYSTEM PERFORMANCE Nominal Gain System Error1 Average Temperature Coefficient Gain Matching Nonlinearity | 1 | 1 | V/V | |
VOUT = −3 V to +3 V | 0.05 | 0.03 | % | |
TA = −40°C to +85°C | 2 | 1 | ppm/°C | |
Channel to channel | 0.08 | 0.05 | % | |
VOUT = −3 V to +3 V | 20 | 20 | ppm | |
NOISE PERFORMANCE Voltage Noise Spectral Density Peak-to-Peak Current Noise Spectral Density Peak-to-Peak | f = 1 kHz | 13 | 13 | nV/√Hz |
f = 0.1 Hz to 10 Hz | 0.4 | 0.4 2 | µV p-p | |
f = 1 kHz | 0.8 | 0.8 | fA/√Hz | |
f = 0.1 Hz to 10 Hz | 8 | 8 | fA p-p | |
DYNAMIC PERFORMANCE | ||||
Small Signal Bandwidth | −3 dB | 3.3 | 3.3 | MHz |
Slew Rate | 0.8 | 0.8 | V/µs | |
Settling Time to 0.01% | VOUT = −3 V to +3 V | 14 | 14 | µs |
INPUT CHARACTERISTICS Input Voltage Range2 Over Temperature Input Impedance3 | −5 +4 | −5 +4 | V | |
TA = −40°C to +85°C | –5 +3.5 | –5 +3.5 | V | |
10||4 | 10||4 | TΩ||pF | ||
OUTPUT CHARACTERISTICS Output Swing Over Temperature Output Swing Over Temperature Short-Circuit Current Capacitive Load Drive | RL = 10 kΩ | −4.9 +4.9 | −4.9 +4.9 | V |
TA = −40°C to +85°C | –4.88 +4.88 | –4.88 +4.88 | V | |
RL = no load | −4.975 +4.97 | −4.975 +4.97 | V | |
TA = −40°C to +85°C | –4.95 +4.95 | –4.95 +4.95 | V | |
10 | 10 | mA | ||
200 | 200 | pF | ||
POWER SUPPLY Operating Range Power Supply Rejection Supply Current per Amplifier Over Temperature | Single supply Dual supply VS = ±3 V to ±18 V IOUT = 0 mA TA = −40°C to +85°C | 3 36 ±1.5 ±18 90 180 250 300 | 3 36 ±1.5 ±18 80 90 180 250 300 | V V dB µA µA |
TEMPERATURE RANGE Specified Performance | TA | −40 +85 | −40 +85 | °C |
1 Error as a percentage of the measurement. This includes the effects of open-loop gain and common-mode rejection ratio.
2 The inputs of the AD8244 can go up to the positive supply; however, the input range is derated because error increases near the positive supply as the input transistors start to saturate.
3 For more information on the input impedance, see Figure 24 and Figure 37.
VS = ±15 V, TA = 25°C, VIN = 0 V, RL = 10 kΩ, unless otherwise noted.
Table 3.
Parameter | Test Conditions/Comments | AD8244A Min Typ Max | AD8244B Min Typ Max | Unit |
DC PERFORMANCE Offset Voltage Over Temperature Average Temperature Coefficient Offset Voltage Matching Input Bias Current Over Temperature Input Bias Current Matching Over Temperature | 100 600 | 100 350 | µV | |
TA = −40°C to +85°C | 1.25 | 0.545 | mV | |
TA = −40°C to +85°C | 10 | 3 | µV/°C | |
Channel to channel | 800 | 500 | µV | |
0.9 10 | 0.9 3 | pA | ||
TA = 85°C | 150 | 100 | pA | |
Channel to channel | 0.05 | 0.05 0.2 | pA | |
TA = 85°C | 2 | 2 | pA | |
SYSTEM PERFORMANCE Nominal Gain System Error1 Average Temperature Coefficient Gain Matching Nonlinearity | 1 | 1 | V/V | |
VOUT = −10 V to +10 V | 0.03 | 0.008 | % | |
TA = −40°C to +85°C | 2 | 1 | ppm/°C | |
Channel to channel | 0.05 | 0.01 | % | |
VOUT = −10 V to +10 V | 5 | 5 | ppm | |
NOISE PERFORMANCE Voltage Noise Spectral Density Peak-to-Peak Current Noise Spectral Density Peak-to-Peak | f = 1 kHz | 13 | 13 | nV/√Hz |
f = 0.1 Hz to 10 Hz | 0.4 | 0.4 | µV p-p | |
f = 1 kHz | 0.8 | 0.8 | fA/√Hz | |
f = 0.1 Hz to 10 Hz | 8 | 8 | fA p-p | |
DYNAMIC PERFORMANCE | ||||
Small Signal Bandwidth | −3 dB | 3.6 | 3.6 | MHz |
Slew Rate | 0.8 | 0.8 | V/µs | |
Settling Time to 0.01% | VOUT = −10 V to +10 V | 18 | 18 | µs |
INPUT CHARACTERISTICS Input Voltage Range2 Over Temperature Input Impedance3 | −15 +14 | −15 +14 | V | |
TA = −40°C to +85°C | –15 +13.5 | –15 +13.5 | V | |
10||4 | 10||4 | TΩ||pF | ||
OUTPUT CHARACTERISTICS Output Swing Over Temperature Output Swing Over Temperature Short-Circuit Current Capacitive Load Drive | RL = 10 kΩ | −14.87 +14.87 | −14.87 +14.87 | V |
TA = −40°C to +85°C | –14.84 +14.84 | –14.84 +14.84 | V | |
RL = no load | −14.95 +14.95 | −14.95 +14.95 | V | |
TA = −40°C to +85°C | –14.93 +14.93 | –14.93 +14.93 | V | |
20 | 20 | mA | ||
200 | 200 | pF | ||
POWER SUPPLY Operating Range Power Supply Rejection Supply Current per Amplifier Over Temperature | Single supply Dual supply VS = ±3 V to ±18 V IOUT = 0 mA TA = −40°C to +85°C | 3 36 ±1.5 ±18 90 180 250 300 | 3 36 ±1.5 ±18 80 90 180 250 300 | V V dB µA µA |
TEMPERATURE RANGE Specified Performance | TA | −40 +85 | −40 +85 | °C |
1 Error as a percentage of the measurement. This includes the effects of open-loop gain and common-mode rejection ratio.
2 The inputs of the AD8244 can go up to the positive supply; however, the input range is derated because error increases near the positive supply as the input transistors start to saturate.
Table 4.
Parameter | Rating |
Supply Voltage Output Short-Circuit Current Duration Maximum Voltage at IN x or OUT x1 Minimum Voltage at IN x or OUT x1 Storage Temperature Range Operating Temperature Range Maximum Junction Temperature ESD Human Body Model (HBM) Charged Device Model (CDM) Machine Model (MM) | ±18 V Indefinite +VS + 0.3 V −VS − 0.3 V −65°C to +150°C −40°C to + 85°C 150°C 3 kV 1.25 kV 100 V |
θJA is specified for the worst-case conditions, that is, a device
soldered in a circuit board for surface-mount packages.
Table 5. Thermal Resistance
Package Type | θJA | Unit |
10-Lead MSOP | 152 | °C/W |
1 For voltages beyond these limits, use input protection resistors. See the Input Protection section for more information.
IN A | 1 | 10 | IN D | |
OUT A | 2 | AD8244 | 9 | OUT D |
+VS | 3 | TOP VIEW | 8 | –VS |
OUT B | 4 | (Not to Scale) | 7 | OUT C |
IN B | 5 | 6 | IN C |
11689-003
Figure 3. Pin Configuration
Table 6. Pin Function Description
Pin Number | Mnemonic | Description |
1 | IN A | Channel A Input |
2 | OUT A | Channel A Output |
3 | +VS | Positive Supply Voltage |
4 | OUT B | Channel B Output |
5 | IN B | Channel B Input |
6 | IN C | Channel C Input |
7 | OUT C | Channel C Output |
8 | −VS | Negative Supply Voltage |
9 | OUT D | Channel D Output |
10 | IN D | Channel D Input |
VS = ±5 V, TA = 25°C, VIN = 0 V, RL = 10 kΩ, unless otherwise noted.
50
40
40
30
HITS
HITS
30
20
20
10 10
11689-004
0
–400 –200 0 200 400 600
OFFSET VOLTAGE (µV)
Figure 4. Typical Distribution of Offset Voltage
0
11689-007
–800 –600 –400 –200 0 200 400 600 800
OFFSET VOLTAGE MATCHING (µV)
Figure 7. Typical Distribution of Offset Voltage Matching
VIN = ±3V
12
VS = ±15V
TA = –40°C TO +85°C 40
10
35
8 30
HITS
HITS
25
6
20
4 15
2
0
–10 –9 –8 –7 –6 –5 –4 –3 –2 –1 0 1 2 3 4 5 6 7 8 9 10
OFFSET VOLTAGE DRIFT (µV/°C)
10
5
0
–300
–200
11689-008
–100 0 100 200 300
SYSTEM ERROR (µV/V)
11689-005
Figure 5. Typical Distribution of Offset Voltage Drift
Figure 8. Typical Distribution of System Error
25
50 VS = ±3V TO ±18V
20
40
15
HITS
HITS
30
10
20
5
10
0
–0.60 –0.55 –0.50 –0.45 –0.40 –0.35
INPUT BIAS CURRENT (pA)
0
–40
–20
11689-009
0 20 40 60 80
PSRR (µV/V)
11689-006
Figure 6. Typical Distribution of Input Bias Current
Figure 9. Typical Distribution of Power Supply Rejection Ratio (PSRR)
10
5
GAIN (dB)
0
–5
VS = +3V
120
110
100
90
PSRR (dB)
80
70
60
–PSRR VS = ±5V VIN = 0V
+PSRR, SINGLE SUPPLY
+VS = +5V, –VS = GND VIN = +2.5V
REPRESENTATIVE SAMPLE
+PSRR VS = ±5V VIN = 0V
–10 VS = +5V
VS = ±5V 50
VS = ±15V
–15 40
11689-010
30
–20
1k 10k 100k 1M FREQUENCY (Hz)
Figure 10. Gain vs. Frequency
20
11689-013
0.1 1 10 100 1k 10k FREQUENCY (Hz)
Figure 13. PSRR vs. Frequency
10
CL = 100pF
5
0
10
1/2
AD8244
GAIN MATCHING (%)
1 IN-AMP
TYPICAL MISMATCH BETWEEN ANY TWO CHANNELS
GAIN (dB)
–5
VS = +3V
0.1
–10 VS = +5V VS = ±5V VS = ±15V
0.01
11689-011
–15
–20
1k 10k 100k 1M FREQUENCY (Hz)
Figure 11. Gain vs. Frequency, CL = 100 pF
0.001
11689-014
10 100 1k 10k 100k FREQUENCY (Hz)
Figure 14. Gain Matching vs. Frequency
1k 10
TYPICAL MISMATCH BETWEEN ANY TWO CHANNELS
OUTPUT IMPEDANCE (Ω)
GAIN MATCHING (%)
100 1 IN-AMP
1/2
AD8244
10 0.1
1 0.01
0.1
11689-012
11689-015
10 100 1k 10k 100k 1M FREQUENCY (Hz)
0.001
10 100 1k 10k 100k FREQUENCY (Hz)
Figure 12. Output Impedance vs. Frequency
Figure 15. Gain Matching vs. Frequency, 1 kΩ Source Imbalance
1k
INPUT BIAS CURRENT (pA)
100
10
1
0.1
REPRESENTATIVE SAMPLE
15
SHORT-CIRCUIT CURRENT (mA)
VS = ±5V | ISHORT+ | |||||
ISHORT– | ||||||
10
5
0
–5
11689-016
–10
0.01
–40 –20 0 20 40 60 80
TEMPERATURE (°C)
Figure 16. Input Bias Current vs. Temperature
–15
11689-019
–40 –20 0 20 40 60 80
TEMPERATURE (°C)
Figure 19. Short-Circuit Current vs. Temperature
REPRE | SENTATIV | E SAMPLE | S NORMA | LIZED AT | 25°C | |
VIN = ±3 | V | |||||
100 +VS
OUTPUT VOLTAGE SWING (mV) REFERRED TO SUPPLY VOLTAGES
80 –50
60 –100 –40°C
SYSTEM ERROR (µV/V)
+25°C
40
20
0
–20
–40
–60
–80
–100
–40 –20 0 20 40 60 80
TEMPERATURE (°C)
–150
–200
+200
+150
+100
+50
–VS
+85°C RL = 100kΩ
11689-020
0 3 6 9 12 15 18
SUPPLY VOLTAGE (±VS)
11689-017
Figure 17. System Error vs. Temperature, Normalized at 25°C Figure 20. Output Voltage Swing vs. Supply Voltage, RL = 100 kΩ
VS = ±15V | ||||||
VS = +5V | ||||||
240 +VS
SUPPLY CURRENT PER AMPLIFIER (µA)
–0.1
OUTPUT VOLTAGE SWING (V) REFERRED TO SUPPLY VOLTAGES
220
–0.2 –40°C
+25°C
200
180
160
140
120
100
–40 –20 0 20 40 60 80
TEMPERATURE (°C)
–0.3
–0.4
+0.4
+0.3
+0.2
+0.1
–VS
+85°C RL = 10kΩ
11689-021
0 3 6 9 12 15 18
SUPPLY VOLTAGE (±VS)
11689-018
Figure 18. Supply Current vs. Temperature Figure 21. Output Voltage Swing vs. Supply Voltage, RL = 10 kΩ
5 25
4 20
OUTPUT VOLTAGE SWING (V)
3 15
REPRESENTATIVE SAMPLE VS = ±15V
NONLINEARITY (ppm)
2 10
1
–40°C
0 +25°C
+85°C
5
0
RL = 100kΩ
–1
–2
–3
–4
–5
100 1k 10k 100k 1M
LOAD RESISTANCE (Ω)
Figure 22. Output Voltage Swing vs. Load Resistance
–5 RL = 10kΩ
–10
–15
–20
11689-025
–25
–10 –8 –6 –4 –2 0 2 4 6 8 10
OUTPUT VOLTAGE (V)
Figure 25. Nonlinearity, VS = ±15 V
11689-022
+VS
OUTPUT VOLTAGE SWING (V) REFERRED TO SUPPLY VOLTAGES
–0.2
–0.4
–0.6
100
80
60
NONLINEARITY (ppm)
40
REPRESENTATIVE SAMPLE VS = ±5V
–0.8
–40°C
+25°C
+85°C
20
0
RL = 100kΩ
+0.8
+0.6
+0.4
+0.2
–VS
–20 RL = 10kΩ
–40
–60
–80
11689-126
–100
11689-023
10µ 100µ 1m 10m
–3 –2 –1
0 1 2 3
OUTPUT CURRENT (A)
Figure 23. Output Voltage Swing vs. Output Current
OUTPUT VOLTAGE (V)
Figure 26. Nonlinearity, VS = ±5 V
10 1k
8
INPUT BIAS CURRENT (pA)
NOISE (nV/√Hz)
6 100
4
2
11689-026
0 VS = ±5V
10
VS = ±15V
–2
–15 –10 –5 0 5 10 15
INPUT VOLTAGE (V)
Figure 24. Input Bias Current vs. Input Voltage
1
11689-028
0.1 1 10 100 1k 10k FREQUENCY (Hz)
Figure 27. Voltage Noise Spectral Density vs. Frequency
1s/DIV | |||||||||
200nV/DIV |
30
MAXIMUM OUTPUT VOLTAGE (V p-p)
VS = ±15V
25
20
15
10 VS = ±5V
11689-029
5 VS = +5V
Figure 28. 0.1 Hz to 10 Hz Voltage Noise
0
11689-031
100 1k 10k 100k 1M FREQUENCY (Hz)
Figure 31. Large Signal Frequency Response
5
VS = ±15V
4
CHANGE IN OFFSET VOLTAGE (µV)
3
2
5V/DIV
18.4µs TO 0.01%
1
0
–1
–2 0.002%/DIV
11689-129
–3
–4
–5
0 10 20 30 40 50 60 70 80
WARM-UP TIME (Seconds)
Figure 29. Change in Offset Voltage vs. Warm-Up Time
50μs/DIV
11689-032
Figure 32. Large Signal Pulse Response and Settling Time, RL = 10 kΩ, CL = 100 pF
VS = ±5V VIN = ±5.5V
SETTLED TO 0.01% | ||||||||
40
35
SETTLING TIME (µs)
30
25
20
INPUT VOLTAGE 15
OUTPUT VOLTAGE
10
2V/DIV 1ms/DIV
5
11689-033
0
2 4 6 8 10 12 14 16 18 20
STEP SIZE (V)
11689-030
Figure 30. No Phase Reversal Figure 33. Settling Time vs. Step Size, RL = 10 kΩ, CL = 100 pF
TYPICAL CHANNEL-TO-CHANNEL ISOLATION | ||||||||||||||||||||||||
CHANNEL A FULLY DRIVEN | ||||||||||||||||||||||||
–20
20mV/DIV | 4µs/DIV |
–40 RL = 10kΩ
CHANNEL ISOLATION (dB)
–60
–80
–100
–120
11689-036
–140
Figure 34. Small Signal Pulse Response, RL = 10 kΩ, CL = 100 pF
–160
11689-136
10 100 1k 10k 100k FREQUENCY (Hz)
Figure 36. Channel Isolation vs. Frequency
CL = NO LOAD CL = 100pF CL = 200pF | |||||||||||
25mV/DIV | 4µs/DIV |
5.0
4.8
INPUT CAPACITANCE (pF)
4.6
4.4
4.2
4.0
3.8
3.6
3.4
INPUT CAPACITANCE DOES NOT DEPEND ON NEGATIVE SUPPLY VOLTAGE
11689-037
3.2
3.0
–16 –14 –12 –10 –8 –6 –4 –2
VIN (V) REFERRED TO +VS
+VS
11689-038
Figure 35. Small Signal Pulse Response with Various Capacitive Loads, RL = No Load
Figure 37. Input Capacitance vs. Input Voltage (VIN) Referred to +VS
+VS
+VS
+VS
OUT
500Ω
IN
–VS
11689-039
–VS
–VS
Figure 38. Simplified Schematic
of these op amps is to route the guard trace between the input
The AD8244 is a precision, quad, FET input, unity-gain buffer that is designed to isolate very large source impedances from the rest of the signal chain. N-channel JFETs are used as the input transistors to provide a low offset (350 μV maximum),
pin and the supply pin. Traces can be routed between pins for large packages, such as DIP or even SOIC; however, the board area consumed by these packages is prohibitive for many modern applications.
low noise (13 nV/√Hz typical), high impedance (more than
10 TΩ) input stage that operates right down to the negative supply
LARGE FOOTPRINT
PACKAGES
SINGLE
SMALL FOOTPRINT
PACKAGES
voltage. Using a new drift trimming method, the B grade AD8244 is able to achieve very low offset voltage over temperature
(0.545 mV maximum), and it introduces minimal system error
GUARD INPUT
1
–IN 2
+IN 3
OP AMP
8
7 +VS
6 OUT
GUARD INPUT
1
–IN 2
+IN 3
SINGLE OP AMP
8
7 +VS
6 OUT
over temperature. The AD8244 design is optimized for high precision applications, such as buffers for biopotential electrodes,
GUARD
–VS 4
GUARD
5
–VS 4 5
where it is important that buffers have very high impedance inputs and channels that match closely. Because the AD8244 fits into a 10-lead package, whereas a quad op amp requires a minimum of 14 leads, routing space is reduced and parasitics from the feedback traces are eliminated. Furthermore, the flexible design and the high channel density of the AD8244 allow it to be used in the signal chain anywhere a unity-gain buffer is needed.
When using low input bias current FET input amplifiers, designers must pay careful attention to voltage gradients from the input node to adjacent conductors on the board. These gradients can create leakage currents that overwhelm the input impedance and bias current performance of the FET input.
These leakage currents get much worse with contamination,
*LEAKAGE PATH FROM +IN TO –VS CAUSES LARGE INPUT CURRENT
11689-041
Figure 39. Single Op Amp Guarding Patterns
The AD8244 solves this problem with a unique pinout that naturally isolates the high impedance inputs from the low impedance nodes, such as the supplies and outputs of the other buffers. Additionally, the buffers of the AD8244 can be used to guard their own inputs, reducing the voltage gradient seen by the input to only the low offset voltage of the buffer. The AD8244 facilitates this by making guard traces easy to route without the need for traces to go between pins.
GUARD TRACE SURROUNDS INPUT NODE
FROM SENSOR
humidity, and temperature. Guarding techniques can be used to protect against parasitic leakage currents by greatly reducing the voltage gradient seen by the input node. Physically, a guard is a
IN A
1
IN A
low impedance conductor that surrounds a high impedance node and is raised to the voltage of that node. It serves to buffer leakage by diverting it away from the sensitive node and into
GUARD TRACE
SOLDER MASK REMOVED
OUT A
2 OUT A
AD8244
the low impedance guard. A complication results from the fact that many traditional op amp pinouts place a supply pin next to the noninverting input. The only way to guard the input of one
3 +VS
11689-042
Figure 40. Guarding with the AD8244
All terminals of the AD8244 are protected against ESD. In addition, the input structure allows for dc overload conditions up to a diode drop above the positive supply and a diode drop below the negative supply. Voltages more than a diode drop beyond the supplies cause the ESD diodes to conduct and enable current to flow through the diode. Therefore, use an external resistor in series with each of the inputs to limit current for voltages beyond the supplies. In either scenario, the AD8244 input safely handles a continuous 6 mA current at room temperature.
For applications where the AD8244 encounters extreme overload voltages, as in cardiac defibrillators, use external series resistors and low leakage diode clamps, such as FJH1100 or BAV199L.
The inputs of the AD8244 buffers are extremely high impedance. Shunt impedances from leakage resistance and parasitic capacitance in the printed circuit board (PCB) layout can severely degrade the performance of the JFET input. If a buffer output is used to surround the corresponding input node, leakage resistance and parasitic capacitance from the layout can be kept extremely low. Remove solder mask from the guard traces to guard against surface leakage due to contamination. In addition to the guard traces on the primary side, route a guard trace around any vias in the input net on the other side of the board as well. Keep the parasitic capacitance seen by the output small to maintain the optimum step response. Amplifiers used in the same signal path, such as buffering the voltage for two inputs of an in- amp or difference amplifier, must have matched impedance in the input traces. This includes matched length and symmetrical traces. Place any input resistors close to the AD8244 inputs to avoid interaction with trace parasitics. If one of the channels is not in use, connect the input to a voltage that is within its linear range to avoid overdrive conditions that can interfere with other channels. Leave the output unconnected. Place decoupling capacitors, such as 0.1 µF, near the AD8244. Larger capacitors, such as 10 µF, can be used farther away from the device.
The AD8244 can be used to buffer the inputs of difference amplifiers and instrumentation amplifiers to take advantage of qualities of the JFET input. In applications such as these, which use two channels of the AD8244 to buffer the positive and negative of a differential signal path, it is the mismatch between the channels, rather than the absolute error, that introduces error into the system. The AD8244 is designed so that the channels closely match and can be used in differential circuits with excellent results. Channel-to-channel matching errors are specified to aid in the design process. When driving the inputs of an instrumentation amplifier, difference amplifier, or other differential input circuit, the gain matching from channel to channel defines the common-mode rejection ratio (CMRR) error introduced to the system by the AD8244. The unit conversion is as follows:
CMRR (dB) = 20 × log10(100/Gain Matching (%))
The JFET pinch-off voltage can vary from channel to channel and cause additional mismatch when the JFET begins to saturate near the positive rail. The CMRR error is minimized by keeping the input voltage away from the positive input range limit. Because the input impedance is very high, the CMRR achieved in differential systems stays high, even with large or mismatched source resistance. See the Typical Performance Characteristics section for more information.
The closed-loop output impedance of the AD8244 increases at higher frequencies when the loop gain is reduced, as shown in Figure 12. The AD8244 drives 200 pF directly with slight ringing, as shown in Figure 35. By placing a small resistor in series with the output, the capacitive load drive of the AD8244 can be increased. For applications that need the AD8244 input performance and very low output impedance over frequency, such as driving a cable shield, a switching load, or a large amount of capacitance at high frequencies, an op amp can be added in a configuration, such as the one in Figure 41. This configuration takes advantage of the low op amp output impedance at low frequencies, and the load capacitor reduces the output impedance at high frequencies. Typically, RF × CF should be less than or equal to RO × CL.
RS VIN
1/4
AD8244
A1
RO
VOUT
CL
11689-043
CF
RF
Figure 41. Adding an Op Amp for Low Output Impedance
In an ECG system, mismatches between the source impedance of different leads, working against the input impedance of the front-end amplifier, can create unbalanced voltage dividers that reduce the system CMRR. When presented to a moderately
R1 R2
C1
2nF
1/4
high input impedance amplifier, the combined impedance of the skin, electrolyte, electrodes, and the protection resistors can be enough to cause power line noise pickup, current noise issues, and
VIN
NOTES
AD8244 VOUT C2
1nF
signal division. Dry electrode systems, which are becoming increasingly common and have significantly higher source impedance, are especially sensitive to these errors. Typically, a high input impedance, low bias current, FET input op amp is used to buffer the electrode signal before it is presented to an instrumentation amplifier. This buffer solves the majority of
1. R1 = R2 = R
11689-143
2. R = 112.5MΩ/fC, Q = 0.707
Figure 42. Sallen-Key Low-Pass Filter
The following equations describe the corner frequency, fC, and quality factor, Q, for the low-pass filter case of the Sallen-Key topology, shown in Figure 42:
these problems; however, when an instrument is in the field, it
fC = 1/(2π
R1× R2 × C1× C2 )
can be subject to dust pickup and humidity. If the op amp input
is not guarded, these environmental factors can create unwanted
Q = (
R1× R2 × C1× C2 )/(C2 × (R1 + R2))
leakage currents that bring back the aforementioned issues from insufficient input impedance. The AD8244 pinout is configured to make it simple to guard the inputs from parasitic resistance and capacitance while it also drives the instrumentation amplifier inputs, creating a more robust design, while saving power and board space. The CMRR of the AD8244 driving an instrumentation amplifier initially depends on the gain matching for the chosen supplies and voltage range, as well as the instrumentation amplifier used, but it can be improved with design techniques such as right leg drive (RLD) or digital filtering.
In filtering applications, it is generally recommended to use capacitors such as C0G or NP0 ceramics for distortion and
For an example of a design with this topology, choose a filter where Q = 0.707 and R1 = R2 = R. This requires that C1 = 2 × C2.
The corner frequency equation can now be simplified to
fC = 1/(2π × R × C2 × √2)
If an available capacitor, such as 1 nF, is chosen for C2, R can be written in terms of the desired cutoff frequency:
R = 1/(2√2 × π × 1 nF × fC) = 112.5 MΩ/fc (that is,
R = 750 kΩ for fC = 150 Hz)
R1
dielectric absorption performance. These types of capacitors do not have a high volumetric efficiency and are only available in values less than a few tens of nanofarads, depending on the
case size and voltage rating. For a given cutoff frequency, using
VIN
C1
22nF
NOTES
C2
22nF
R2
1/4
AD8244 VOUT
smaller capacitors requires larger resistor values. At low frequencies where the resistor values become very large, the bias current of a typical op amp can introduce significant offsets and additional noise. The subpicoampere bias current of the AD8244 allows resistor values in the tens of megaohms with no
1. R2 = R, R1 = R/2
11689-144
2. R = 10.2MΩ/fC, Q = 0.707
Figure 43. Sallen-Key High-Pass Filter
The high-pass filter case of the Sallen-Key topology has the same corner frequency equation as the low-pass filter. However, the equation for Q changes to
additional error while providing an excellent low power, small
footprint solution for filter design. Between the four channels of
Q = (
R1× R2 × C1× C2 )/(R1 × (C1 + C2))
the AD8244, a filter with more than eight poles can be implemented while using less space than the same filter with a quad op amp.
In this case, a Q of 0.707 is achieved with C1 = C2 = C, and 2 × R1 = R2 = R, which is a symmetrical result to the low-pass filter case.
The corner frequency then simplifies to
fC = 1/(√2 × π × R × C)
For a low corner frequency, a larger available capacitor such as 22 nF can be chosen, yielding the following expression for R:
R = 10.2 MΩ/fc (that is, a 0.5 Hz filter requires R1 = 10 MΩ and R2 = 20 MΩ)
C = 7500pF 60Hz: R = 357kΩ
50Hz: R = 422kΩ
R R
2C
VIN
R/2
C C
1/4
AD8244 VOUT
(1 – K) × R'
1/4
AD8244
K × R'
Photodiodes in precision circuits are typically measured in photovoltaic mode, in which there is no reverse bias voltage. Two benefits to this measurement mode are that there is no dark current, and the output is linearly related to the light intensity.
However, in photovoltaic mode, the signal current can be very small, requiring a high gain transimpedance amplifier (TIA). There are a limited number of amplifiers suited for building TIAs for measuring photodiodes or other low current sensors, which can make it difficult to achieve high performance. Using an AD8244 as the interface to the photodiode eliminates the need
11689-145
Figure 44. Twin-T Notch Filter
The following equations describe the parameters of the Twin-T notch filter with active feedback shown in Figure 44:
fO = 1/(2πRC)
Q = 0.25/(1 − K)
where K is an attenuation factor from 0 to 1, as shown in Figure 44. A K of either 0 or 1 can be achieved with only one buffer.
One of the best things about this filter is that fO and Q are independent, which allows for easy tuning of filter characteristics. However, designers use the Twin-T notch filter sparingly in production designs because of its sensitivity to component tolerances, which affect both the depth and the frequency of the notch. Reducing the Q is one way to ensure that the desired
frequency has sufficient attenuation independent of component
for a low bias current op amp, allowing optimization of other parameters, such as precision, slew rate, output drive, board space, and cost. As with any composite amplifier, it is important to pay special attention to stability. The unity-gain crossover frequency of the op amp must be less than the AD8244 bandwidth for this configuration to be unity-gain stable. The noise gain of the op amp varies with the shunt resistance of the diode, which is temperature dependent.
GUARD
RF
CF
1/4
AD8244 VOUT
variance and drift; however, reducing the Q also linearly increases the distance between the pass bands. The notch depth can be improved and the stop-band width decreased simultaneously by cascading multiple filter stages.
To illustrate the benefit of cascading stages, Figure 45 shows the response of two filters, both designed to provide greater than 26 dB of attenuation at 60 Hz ± 5%, which allows for component tolerance. The single stage filter requires a Q of 0.5 and results in a −3 dB notch bandwidth of 120 Hz. The two stage filter has a Q of 2.25 for each stage, and the −3 dB notch bandwidth is reduced to about 40 Hz.
20
IPHD
A1
11689-044
Figure 46. AD8244 in a Photodiode Application
10
0
MAGNITUDE (dB)
–10
–26dB FROM 57Hz TO 63Hz
–20
–30
–40
–50
–60
–70 SINGLE STAGE NOTCH
TWO STAGE CASCADED NOTCH
11689-046
–80
10 100 1k FREQUENCY (Hz)
Figure 45. Cascading Notch Filters
The voltage noise of the AD8244 can be reduced by placing multiple buffers in parallel. For example, two buffers in parallel reduce the voltage noise by √2, or all four buffers placed in parallel act as a buffer with ½ the noise. The trade-offs to this method are increased bias current, current noise, and input capacitance. Place a small resistor, such as 50 Ω, between the outputs to avoid extra current flow due to the slight differences between each output. For less power sensitive applications, these 50 Ω resistors can be omitted to boost the available output current.
RS VIN
1/4 RO
AD8244
1/4 RO
AD8244
1/4 RO
AD8244
VOUT
1/4 RO
11689-045
AD8244
Figure 47. Reducing the Voltage Noise
3.10
3.00
2.90
3.10
3.00
2.90
10 6
1 5
5.15
4.90
4.65
PIN 1 IDENTIFIER
0.50 BSC
0.95
0.85
0.75
0.15
0.05
COPLANARITY 0.10
0.30 0.15
1.10 MAX
6°
0°
15° MAX
0.23
0.13
0.70
0.55
0.40
091709-A
COMPLIANT TO JEDEC STANDARDS MO-187-BA
Figure 48. 10-Lead Mini Small Outline Package [MSOP] (RM-10)
Dimensions shown in millimeters
Model1 | Temperature Range | Package Description | Package Option | Branding |
AD8244ARMZ | −40°C to +85°C | 10-Lead Mini Small Outline Package [MSOP], Standard Grade | RM-10 | Y54 |
AD8244ARMZ-R7 | −40°C to +85°C | 10-Lead Mini Small Outline Package [MSOP], Standard Grade, 7” Tape and Reel | RM-10 | Y54 |
AD8244BRMZ | −40°C to +85°C | 10-Lead Mini Small Outline Package [MSOP], High Performance Grade | RM-10 | Y55 |
AD8244BRMZ-R7 | −40°C to +85°C | 10-Lead Mini Small Outline Package [MSOP], High Performance Grade, 7” Tape and Reel | RM-10 | Y55 |
AD8244-EVALZ | Evaluation Board |
1 Z = RoHS Compliant Part.
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