Data Sheet
Low offset voltage: 1 μV | NC | 1 | 8 | NC |
Input offset drift: 0.005 μV/°C | –IN A | 2 | AD8571 7 | V+ |
Rail-to-rail input and output swing 5 V/2.7 V single-supply operation
+IN A V–
3 TOP VIEW 6
(Not to Scale)
4 5
OUT A NC
High gain: 145 dB typical CMRR: 140 dB typical
PSRR: 130 dB typical
NC = NO CONNECT
Figure 1. 8-Lead MSOP (RM Suffix)
Ultralow input bias current: 10 pA typical Low supply current: 750 μA per op amp Overload recovery time: 50 μs
NC 1
–IN A 2
+IN A 3
V– 4
AD8571
TOP VIEW
(Not to Scale)
8 NC
01104-001
7 V+
6 OUT A
01104-004
5 NC
No external capacitors required
Temperature sensors
NC = NO CONNECT
Figure 2. 8-Lead SOIC (R Suffix)
1 | AD8572 TOP VIEW (Not to Scale) | 8 |
2 | 7 | |
3 | 6 | |
4 | 5 |
OUT A V+
Pressure sensors Precision current sensing
–IN A
+IN A V–
OUT B
01104-002
–IN B
+IN B
Strain gage amplifiers
Medical instrumentation Thermocouple amplifiers
Figure 3. 8-Lead TSSOP (RU Suffix)
1 | AD8572 TOP VIEW (Not to Scale) | 8 |
2 | 7 | |
3 | 6 | |
4 | 5 |
OUT A V+
–IN A
+IN A V–
OUT B
01104-005
–IN B
+IN B
This family of amplifiers has ultralow offset, drift, and bias
Figure 4. 8-Lead SOIC (R Suffix)
current. The AD8571/AD8572/AD85741 are single, dual, and quad amplifiers, respectively, featuring rail-to-rail input and output swings. All are guaranteed to operate from 2.7 V to 5 V
single supply.
OUT A 1
–IN A 2
+IN A 3
V+ 4
AD8574
TOP VIEW
14 OUT D
13 –IN D
12 +IN D
11 V–
+IN B 5
(Not to Scale) 10 +IN C
The AD8571/AD8572/AD8574 provide benefits previously found only in expensive auto-zeroing or chopper-stabilized
–IN B 6
OUT B 7
9 –IN C
01104-003
8 OUT C
amplifiers. Using Analog Devices, Inc., topology, these zero-
drift amplifiers combine low cost with high accuracy. (No
Figure 5. 14-Lead TSSOP (RU Suffix)
external capacitors are required.) Using a spread-spectrum, auto-zero technique, the AD8571/AD8572/AD8574 eliminate the intermodulation effects from interaction of the chopping
OUT A 1
–IN A 2
+IN A 3
V+ 4
AD8574
TOP VIEW
14 OUT D
13 –IN D
12 +IN D
11 V–
function with the signal frequency in ac applications.
With an offset voltage of only 1 μV and drift of 0.005 μV/°C, the
+IN B 5
–IN B 6
OUT B 7
(Not to Scale) 10 +IN C
01104-006
9 –IN C
8 OUT C
AD8571/AD8572/AD8574 are perfectly suited for applications where error sources cannot be tolerated. Position and pressure sensors, medical equipment, and strain gage amplifiers benefit greatly from nearly zero drift over their operating temperature range. Many more systems require the rail-to-rail input and output swings provided by the AD8571/AD8572/AD8574.
1 Protected by U.S. Patent 6,130,578.
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibilityis assumedby Analog Devicesforitsuse, norforanyinfringements ofpatents orother rightsofthirdpartiesthatmayresultfromitsuse.Specificationssubjecttochangewithoutnotice.No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
Figure 6. 14-Lead SOIC (R Suffix)
The AD8571/AD8572/AD8574 are specified for the extended industrial/ automotive temperature range (−40°C to +125°C). The AD8571 single amplifier is available in 8-lead MSOP and narrow SOIC packages. The AD8572 dual amplifier is available in 8-lead narrow SOIC and surface-mount TSSOP packages. The AD8574 quad amplifier is available in 14-lead narrow SOIC and TSSOP packages.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 ©1999–2015 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com
5 V Electrical Characteristics 4
2.7 V Electrical Characteristics 5
Typical Performance Characteristics 7
Basic Auto-Zero Amplifier Theory 15
Maximizing Performance Through Proper Layout 17
Random Auto-Zero Correction Eliminates Intermodulation Distortion 18
Broadband and External Resistor Noise Considerations 19
Input Overvoltage Protection 19
5 V Precision Strain Gage Circuit 21
3 V Instrumentation Amplifier 21
High Accuracy Thermocouple Amplifier 22
Precision Voltage Comparator 22
6/15—Rev. E to Rev. F
Added Patent Note, Note 1 1
Change to Input Voltage Parameter, Table 3 6
Changes to Ordering Guide 25
2/11—Rev. D to Rev. E
Changes to Figure 66 21
Updated Outline Dimensions 22
Changes to Ordering Guide 23
6/08—Rev. C to Rev. D
Changes to Figure 19 and Figure 20 8
Changes to Figure 44 12
Changes to Figure 38 13
Moved Figure 50 and Figure 51 14
Changes to Figure 66, Precision Current Meter Section, Layout, Figure 67, Equation 24, and Figure 68 21
5/07—Rev. B to Rev. C
Changes to Features 1
Changes to Table 1 3
Changes to Table 2 4
Changes to Basic Auto-Zero Amplifier Theory Section 14
Changes to Figure 50 15
Changes to Figure 55 16
Changes to Figure 66 21
Updated Outline Dimensions 22
9/06—Rev. A to Rev. B
Updated Format ................................................................. Universal
Changes to Table 1 3
Changes to Table 2 4
Changes to Figure 50 14
Changes to Figure 51 15
Changes to Figure 66 21
Deleted Figure 69 and SPICE Macro-Model Section 17
Deleted SPICE Macro-Model for the AD857x Section 18
Updated Outline Dimensions 22
Changes to Ordering Guide 23
7/03—Rev. 0 to Rev. A
Renumbered Figures.......................................................... Universal
Changes to Ordering Guide 4
Change to Figure 15 16
Updated Outline Dimensions 19
10/99—Revision 0: Initial Version
VS = 5 V, VCM = 2.5 V, VO = 2.5 V, TA = 25°C, unless otherwise noted.
Table 1.
Parameter | Symbol | Conditions | Min | Typ | Max | Unit |
INPUT CHARACTERISTICS Offset Voltage Input Bias Current AD8571/AD8574 AD8572 Input Offset Current AD8571/AD8574 AD8572 Input Voltage Range Common-Mode Rejection Ratio Large Signal Voltage Gain1 Offset Voltage Drift | VOS | 1 | 5 | μV | ||
−40°C ≤ TA ≤ +125°C | 10 | μV | ||||
IB | 10 | 50 | pA | |||
−40°C ≤ TA ≤ +125°C | 1.0 | 1.5 | nA | |||
−40°C ≤ TA ≤ +85°C | 160 | 300 | pA | |||
−40°C ≤ TA ≤ +125°C | 2.5 | 4 | nA | |||
IOS | 20 | 70 | pA | |||
−40°C ≤ TA ≤ +125°C | 150 | 200 | pA | |||
−40°C ≤ TA ≤ +85°C | 30 | 150 | pA | |||
−40°C ≤ TA ≤ +125°C | 150 | 400 | pA | |||
0 | 5 | V | ||||
CMRR | VCM = 0 V to 5 V | 120 | 140 | dB | ||
−40°C ≤ TA ≤ +125°C | 115 | 130 | dB | |||
AVO | RL = 10 kΩ, VO = 0.3 V to 4.7 V | 125 | 145 | dB | ||
−40°C ≤ TA ≤ +125°C | 120 | 135 | dB | |||
∆VOS/∆T | −40°C ≤ TA ≤ +125°C | 0.005 | 0.04 | μV/°C | ||
OUTPUT CHARACTERISTICS | ||||||
Output Voltage High | VOH | RL = 100 kΩ to GND | 4.99 | 4.998 | V | |
RL = 100 kΩ to GND @ −40°C to +125°C | 4.99 | 4.997 | V | |||
RL = 10 kΩ to GND | 4.95 | 4.98 | V | |||
RL = 10 kΩ to GND @ −40°C to +125°C | 4.95 | 4.975 | V | |||
Output Voltage Low | VOL | RL = 100 kΩ to V+ | 1 | 10 | mV | |
RL = 100 kΩ to V+ @ −40°C to +125°C | 2 | 10 | mV | |||
RL = 10 kΩ to V+ | 10 | 30 | mV | |||
RL = 10 kΩ to V+ @ −40°C to +125°C | 15 | 30 | mV | |||
Short-Circuit Limit | ISC | ±25 | ±50 | mA | ||
−40°C to +125°C | ±40 | mA | ||||
Output Current | IO | ±30 | mA | |||
−40°C to +125°C | ±15 | mA | ||||
POWER SUPPLY Power Supply Rejection Ratio Supply Current per Amplifier | PSRR ISY | VS = 2.7 V to 5.5 V −40°C ≤ TA ≤ +125°C VO = 0 V −40°C ≤ TA ≤ +125°C | 120 115 | 130 130 850 1000 | 975 1075 | dB dB μA μA |
DYNAMIC PERFORMANCE | ||||||
Slew Rate | SR | RL = 10 kΩ | 0.4 | V/μs | ||
Overload Recovery Time | 0.05 | 0.3 | ms | |||
Gain Bandwidth Product | GBP | 1.5 | MHz | |||
NOISE PERFORMANCE | ||||||
Voltage Noise | en p-p | 0 Hz to 10 Hz | 1.3 | μV p-p | ||
0 Hz to 1 Hz | 0.41 | μV p-p | ||||
Voltage Noise Density | en | f = 1 kHz | 51 | nV/√Hz | ||
Current Noise Density | in | f = 10 Hz | 2 | fA/√Hz |
1 Gain testing is dependent upon test bandwidth.
VS = 2.7 V, VCM = 1.35 V, VO = 1.35 V, TA = 25°C, unless otherwise noted.
Table 2.
Parameter | Symbol | Conditions | Min | Typ | Max | Unit |
INPUT CHARACTERISTICS Offset Voltage Input Bias Current AD8571/AD8574 AD8572 Input Offset Current AD8571/AD8574 AD8572 Input Voltage Range Common-Mode Rejection Ratio Large Signal Voltage Gain1 Offset Voltage Drift | VOS | 1 | 5 | μV | ||
−40°C ≤ TA ≤ +125°C | 10 | μV | ||||
IB | 10 | 50 | pA | |||
−40°C ≤ TA ≤ +125°C | 1.0 | 1.5 | nA | |||
−40°C ≤ TA ≤ +85°C | 160 | 300 | pA | |||
−40°C ≤ TA ≤ +125°C | 2.5 | 4 | nA | |||
IOS | 10 | 50 | pA | |||
−40°C ≤ TA ≤ +125°C | 150 | 200 | pA | |||
−40°C ≤ TA ≤ +85°C | 30 | 150 | pA | |||
−40°C ≤ TA ≤ +125°C | 150 | 400 | pA | |||
0 | 2.7 | V | ||||
CMRR | VCM = 0 V to 2.7 V | 115 | 130 | dB | ||
−40°C ≤ TA ≤ +125°C | 110 | 130 | dB | |||
AVO | RL = 10 kΩ, VO = 0.3 V to 2.4 V | 110 | 140 | dB | ||
−40°C ≤ TA ≤ +125°C | 105 | 130 | dB | |||
∆VOS/∆T | −40°C ≤ TA ≤ +125°C | 0.005 | 0.04 | µV/°C | ||
OUTPUT CHARACTERISTICS | ||||||
Output Voltage High | VOH | RL = 100 kΩ to GND | 2.685 | 2.697 | V | |
RL = 100 kΩ to GND @ −40°C to +125°C | 2.685 | 2.696 | V | |||
RL = 10 kΩ to GND | 2.67 | 2.68 | V | |||
RL = 10 kΩ to GND @ −40°C to +125°C | 2.67 | 2.675 | V | |||
Output Voltage Low | VOL | RL = 100 kΩ to V+ | 1 | 10 | mV | |
RL = 100 kΩ to V+ @ −40°C to +125°C | 2 | 10 | mV | |||
RL = 10 kΩ to V+ | 10 | 20 | mV | |||
RL = 10 kΩ to V+ @ −40°C to +125°C | 15 | 20 | mV | |||
Short-Circuit Limit | ISC | ±10 | ±15 | mA | ||
−40°C to +125°C | ±10 | mA | ||||
Output Current | IO | ±10 | mA | |||
−40°C to +125°C | ±5 | mA | ||||
POWER SUPPLY Power Supply Rejection Ratio Supply Current per Amplifier | PSRR ISY | VS = 2.7 V to 5.5 V −40°C ≤ TA ≤ +125°C VO = 0 V −40°C ≤ TA ≤ +125°C | 120 115 | 130 130 750 950 | 900 1000 | dB dB μA μA |
DYNAMIC PERFORMANCE | ||||||
Slew Rate | SR | RL = 10 kΩ | 0.5 | V/μs | ||
Overload Recovery Time | 0.05 | ms | ||||
Gain Bandwidth Product | GBP | 1 | MHz | |||
NOISE PERFORMANCE | ||||||
Voltage Noise | en p-p | 0 Hz to 10 Hz | 2.0 | μV p-p | ||
Voltage Noise Density | en | f = 1 kHz | 94 | nV/√Hz | ||
Current Noise Density | in | f = 10 Hz | 2 | fA/√Hz |
1 Gain testing is dependent upon test bandwidth.
Parameter | Rating |
Supply Voltage | 6 V |
Input Voltage | GND − 0.3 V to VS + 0.3 V |
Differential Input Voltage1 | ±5.0 V |
ESD (Human Body Model) | 2000 V |
Output Short-Circuit Duration to GND | Indefinite |
Storage Temperature Range | −65°C to +150°C |
Operating Temperature Range | −40°C to +125°C |
Junction Temperature Range | −65°C to +150°C |
Lead Temperature (Soldering, 60 sec) | 300°C |
Table 3.
1 Differential input voltage is limited to ±5.0 V or the supply voltage, whichever is less.
Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability.
θJA is specified for the worst-case conditions, that is, θJA is specified for a device soldered in a circuit board for SOIC and TSSOP packages.
Table 4. Thermal Resistance
Package Type | θJA | θJC | Unit |
8-Lead SOIC (R) | 158 | 43 | °C/W |
8-Lead MSOP (RM) | 190 | 44 | °C/W |
8-Lead TSSOP (RU) | 240 | 43 | °C/W |
14-Lead SOIC (R) | 120 | 36 | °C/W |
14-Lead TSSOP (RU) | 180 | 36 | °C/W |
VS = 2.7V | |||||||||||||
VCM = 1.35V TA = 25°C | |||||||||||||
180
160
NUMBER OF AMPLIFIERS
140
120
100
80
60
40
20
180
160
NUMBER OF AMPLIFIERS
140
120
100
80
60
40
20
VS = 5V VCM = 2.5V TA = 25°C
0
–2.5
–1.5
–0.5 0.5 1.5 2.5
OFFSET VOLTAGE (µV)
0
–2.5
–1.5
01104-010
–0.5 0.5 1.5 2.5
OFFSET VOLTAGE (µV)
+85°C
°C
C, +25°C, +85
01104-007
Figure 7. Input Offset Voltage Distribution Figure 10. Input Offset Voltage Distribution
VS = 5V
TA = –40°
50
40
INPUT BIAS CURRENT (pA)
30
20
10
0
–10
01104-008
–20
12
VS = 5V
10 VCM = 2.5V
NUMBER OF AMPLIFIERS
TA = –40°C TO +125°C
8
6
4
2
–40°C
+25°C
–30
0 1 2 3 4 5
0
01104-011
0 1 2 3 4 5 6
INPUT COMMON-MODE VOLTAGE (V)
INPUT OFFSET DRIFT (nV/°C)
Figure 8. Input Bias Current vs. Input Common-Mode Voltage Figure 11. Input Offset Voltage Drift Distribution
1500
1000
INPUT BIAS CURRENT (pA)
500
0
10k
OUTPUT VOLTAGE (mV)
1k
100
VS = 5V TA = 25°C
–500
–1000
–1500
SOURCE
10
1
SINK
–2000
0 1 2 3 4 5
0.1
0.0001 0.001 0.01 0.1 1
VS = 5V TA = 125°C | ||||
10 100
COMMON-MODE VOLTAGE (V)
LOAD CURRENT (mA)
01104-009
01104-012
10k
OUTPUT VOLTAGE (mV)
1k
100
10
1
VS = 2.7V TA = 25°C
SOURCE SINK
800
SUPPLY CURRENT PER AMPLIFIER (µA)
700
600
500
400
300
200
100
TA = 25°C
0.1
0.0001 0.001 0.01 0.1 1 10 100
LOAD CURRENT (mA)
0
01104-016
0 1 2 3 4 5 6
SUPPLY VOLTAGE (V)
01104-013
1000
INPUT BIAS CURRENT (pA)
750
500
250
60
50
40
OPEN-LOOP GAIN (dB)
30
20
10
0
–10
–20
0
PHASE SHIFT (Degrees)
VS = 2.7V CL = 0pF RL = ∞ | |||||||||||||||||||
45
90
135
180
225
270
VCM = 2.5V VS = 5V | ||||||||
0
–75 –50 –25 0 25 50 75 100 125 150
TEMPERATURE (°C)
–30
01104-017
–40
10k 100k 1M 10M 100M
FREQUENCY (Hz)
01104-014
Figure 14. Input Bias Current vs. Temperature Figure 17. Open-Loop Gain and Phase Shift vs. Frequency
1.0
SUPPLY CURRENT (mA)
0.8
0.6
0.4
0.2
60
50
40
OPEN-LOOP GAIN (dB)
30
20
10
0
–10
01104-015
–20
0
PHASE SHIFT (Degrees)
VS = 5V CL = 0pF RL = ∞ | |||||||||||||||||||
45
90
135
180
225
270
5V | ||||||||
2.7V | ||||||||
0
–75
–50
–25 0
25 50
75 100
125
150
–30
01104-018
–40
10k 100k 1M 10M 100M
TEMPERATURE (°C)
Figure 15. Supply Current vs. Temperature
FREQUENCY (Hz)
Figure 18. Open-Loop Gain and Phase Shift vs. Frequency
60
50
CLOSED-LOOP GAIN (dB)
40
30
20
10
0
–10
–20
300
270
OUTPUT IMPEDANCE (Ω)
240
210
180
150
120
90
01104-019
60
VS = 5V
AV = 100
AV = 10
VS = 2.7V CL = 20pF RL = 2kΩ | ||||||||||||||||||||||||
AV = 100 | ||||||||||||||||||||||||
AV = 10 | ||||||||||||||||||||||||
AV = 1 | ||||||||||||||||||||||||
–30
–40
100
1k 10k
100k 1M
10M
30
0
100
1k 10k
100k
AV = 1 1M
01104-022
10M
FREQUENCY (Hz)
Figure 19. Closed-Loop Gain vs. Frequency
FREQUENCY (Hz)
Figure 22. Output Impedance vs. Frequency
60
50
CLOSED-LOOP GAIN (dB)
40
30
20
10
0
–10
AV = 100
AV = 10
AV = 1
VS = 5V CL = 20pF RL = 2kΩ
–20
–30
–40
100
VS = 2.7V CL = 300pF RL = 2kΩ AV = 1 | |||||||||||
2µs | 500mV | ||||||||||
1k 10k
100k 1M
01104-020
01104-023
10M
FREQUENCY (Hz)
Figure 20. Closed-Loop Gain vs. Frequency Figure 23. Large Signal Transient Response
300
270
OUTPUT IMPEDANCE (Ω)
240
210
180
150
120
90
VS = 2.7V
VS = 5V CL = 300pF RL = 2kΩ AV = 1 | |||||||||||
5µs | 1V | ||||||||||
AV = 100
AV = 10
60
30
0
100
1k 10k
100k
AV = 1 1M
01104-021
01104-024
10M
FREQUENCY (Hz)
Figure 21. Output Impedance vs. Frequency
Figure 24. Large Signal Transient Response
VS = ±1.35V CL = 50pF | |||||||||||
RL = ∞ AV = 1 | |||||||||||
5µs | 50mV | ||||||||||
VS = ±2.5V RL = 2kΩ TA = 25°C | ||||||||||||||
+OS | ||||||||||||||
–OS | ||||||||||||||
45
SMALL SIGNAL OVERSHOOT (%)
40
35
30
25
20
15
10
01104-025
5
01104-028
0
10 100 1k 10k
CAPACITANCE (pF)
Figure 25. Small Signal Transient Response Figure 28. Small Signal Overshoot vs. Load Capacitance
VS = ±2.5V VIN = –200mV p-p (RET TO GND) CL = 0pF RL = 10kΩ AV = –100 | |||||||||||
20µs | 1V | ||||||||||
VS = ±2.5V CL = 50pF RL = ∞ AV = 1 | |||||||||||
5µs | 50mV | ||||||||||
0V VIN
VOUT
01104-026
0V
Figure 26. Small Signal Transient Response
BOTTOM SCALE: 1V/DIV TOP SCALE: 200mV/DIV
01104-029
Figure 29. Positive Overvoltage Recovery
VS = ±1.35V RL = 2kΩ TA = 25°C | |||||||||||||||
+OS | |||||||||||||||
–OS | |||||||||||||||
50
45
SMALL SIGNAL OVERSHOOT (%)
40
35
30
25
20
15
10
5
0
10 100 1k 10k
CAPACITANCE (pF)
Figure 27. Small Signal Overshoot vs. Load Capacitance
VIN 0V
0V
01104-027
VOUT
VS = ±2.5V VIN = 200mV p-p (RET TO GND) CL = 0pF RL = 10kΩ AV = –100 | |||||||||||
20µs | 1V | ||||||||||
01104-030
BOTTOM SCALE: 1V/DIV TOP SCALE: 200mV/DIV
Figure 30. Negative Overvoltage Recovery
VS = ±2.5V RL = 2kΩ AV = –100
VIN = 60mV p-p
140
120
100
VS = ±1.35V
PSRR (dB)
80
60
40 –PSRR +PSRR
200µs 1V
20
0
100
1k 10k
100k 1M
01104-034
10M
01104-031
FREQUENCY (Hz)
Figure 31. No Phase Reversal Figure 34. PSRR vs. Frequency
140
120
100
CMRR (dB)
80
60
140
120
100
PSRR (dB)
80
60
VS = ±2.5V
+PSRR
VS = 2.7V | ||||||||||||||||||||||||
40 40 –PSRR
01104-032
20 20
0
100
1k 10k
100k 1M
10M
0
100
1k 10k
100k 1M
01104-035
10M
FREQUENCY (Hz)
Figure 32. CMRR vs. Frequency
FREQUENCY (Hz)
Figure 35. PSRR vs. Frequency
140
3.0
120
100
CMRR (dB)
80
60
40
20
2.5
OUTPUT SWING (V p-p)
2.0
1.5
1.0
0.5
VS = ±1.35V RL = 2kΩ AV = 1
THD + N < 1%
TA = 25°C
VS = 5V | ||||||||||||||||||||||||
0
100
1k 10k
100k 1M
10M
0
100
1k 10k
01104-036
100k 1M
FREQUENCY (Hz)
Figure 33. CMRR vs. Frequency
FREQUENCY (Hz)
01104-033
Figure 36. Maximum Output Swing vs. Frequency
5.5
5.0
4.5
OUTPUT SWING (V p-p)
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
100
1k 10k
FREQUENCY (Hz)
VS = ±2.5V RL = 2kΩ AV = 1
THD + N < 1%
TA = 25°C
100k 1M
364
312
en (nV/ Hz)
260
208
156
104
52
VS = 2.7V RS = 0Ω
01104-040
0 0.5 1.0 1.5 2.0 2.5
FREQUENCY (kHz)
01104-037
Figure 37. Maximum Output Swing vs. Frequency Figure 40. Voltage Noise Density from 0 Hz to 2.5 kHz
VS = ±1.35V AV = 120,000
112
VS = 2.7V RS = 0Ω
96
en (nV/ Hz)
80
0V 64
48
32
01104-038
16
1sec 50mV
Figure 38. 0.1 Hz to 10 Hz Noise
0 5 10 15 20 25
01104-041
FREQUENCY (kHz)
Figure 41. Voltage Noise Density from 0 Hz to 25 kHz
VS = ±2.5V AV = 120,000
182
VS = 5V RS = 0Ω
156
en (nV/ Hz)
130
104
78
52
01104-039
26
1sec 50mV
Figure 39. 0.1 Hz to 10 Hz Noise
0 0.5 1.0 1.5 2.0 2.5
01104-042
FREQUENCY (kHz)
Figure 42. Voltage Noise Density from 0 Hz to 2.5 kHz
112
96
en (nV/ Hz)
80
64
48
32
16
VS = 5V RS = 0Ω
0 5 10 15 20 25
FREQUENCY (kHz)
150
POWER SUPPLY REJECTION (dB)
VS = 2.7V TO 5.5V | ||||||||
145
140
135
130
01104-045
125
–75 –50 –25 0 25 50 75 100 125 150
TEMPERATURE (°C)
01104-043
Figure 43. Voltage Noise Density from 0 Hz to 25 kHz Figure 45. Power Supply Rejection vs. Temperature
210
180
en (nV/ Hz)
150
VS = 5V RS = 0Ω
50
OUTPUT SHORT-CIRCUIT CURRENT (mA)
40 VS = 2.7V
ISC–
30
20
10
120
90
60
30
0
–10
–20
–30
–40
ISC+
01104-044
0 5 10
FREQUENCY (Hz)
Figure 44. Voltage Noise Density from 0 Hz to 10 Hz
–50
01104-046
–75 –50 –25 0 25 50 75 100 125 150
TEMPERATURE (°C)
Figure 46. Output Short-Circuit Current vs. Temperature
100
OUTPUT SHORT-CIRCUIT CURRENT (mA)
80
60
40
20
0
VS = 5V
250
225
OUTPUT VOLTAGE (mV)
200
175
150
125
ISC–
VS = 5V
RL = 1kΩ
–20 100
–40
–60
–80
75
50 RL = 10kΩ
01104-047
25
ISC+
RL = 100kΩ
–100
–75 –50 –25 0 25 50 75 100 125 150
TEMPERATURE (°C)
Figure 47. Output Short-Circuit Current vs. Temperature
0
01104-049
–75 –50 –25 0 25 50 75 100 125 150
TEMPERATURE (°C)
Figure 49. Output Voltage to Supply Rail vs. Temperature
250
225
200
VS = 2.7V
OUTPUT VOLTAGE (mV)
175
RL = 1kΩ
150
125
100
75
RL = 100kΩ
RL = 10kΩ
50
25
01104-048
0
–75 –50 –25 0 25 50 75 100 125 150
TEMPERATURE (°C)
Figure 48. Output Voltage to Supply Rail vs. Temperature
The AD8571/AD8572/AD8574 are CMOS amplifiers that achieve their high degree of precision through random frequency auto-zero stabilization. The autocorrection topology allows the AD8571/AD8572/AD8574 to maintain its low offset voltage over a wide temperature range, and the randomized auto-zero clock eliminates any inter-modulation distortion (IMD) errors at the amplifier output.
The AD8571/AD8572/AD8574 can run from a single-supply voltage as low as 2.7 V. The extremely low offset voltage of 1 µV and no IMD products allow the amplifier to be easily configured for high gains without risk of excessive output voltage errors, which makes the AD8571/AD8572/AD8574 an ideal amplifier for applications requiring both dc precision and low distortion for ac signals. The extremely small temperature drift of 5 nV/°C ensures a minimum of offset voltage error over its −40°C to
+125°C temperature range. These combined features make the AD8571/AD8572/AD8574 an excellent choice for a variety of sensitive measurement and automotive applications.
Each AD8571/AD8572/AD8574 op amp consists of two
amplifiers: a main amplifier and a secondary amplifier that is used to correct the offset voltage of the main amplifier. Both consist of
Autocorrection amplifiers are not a new technology. Various IC implementations have been available for more than 15 years, and some improvements have been made over time. The AD8571/AD8572/AD8574 design offers a number of significant performance improvements over older versions while attaining a very substantial reduction in device cost. This section offers a simplified explanation of how the AD8571/AD8572/AD8574 are able to offer extremely low offset voltages and high open- loop gains.
As noted in the Amplifier Architecture section, each AD8571/AD8572/AD8574 op amp contains two internal amplifiers. One is used as the primary amplifier, and the other as an autocorrection, or nulling, amplifier. Each amplifier has an associated input offset voltage that can be modeled as a dc voltage source in series with the noninverting input. In Figure 50 and Figure 51, these are labeled as VOSA and VOSB, where A denotes the nulling amplifier and B denotes the primary amplifier. The open-loop gain for the +IN and −IN inputs of each amplifier is given as AX. Both amplifiers also have a third voltage input with an associated open-loop gain of BX.
VOSB
a rail-to-rail input stage, allowing the input common-mode voltage range to reach both supply rails. The input stage consists of an NMOS differential pair operating concurrently with a
VIN+
VIN–
ΦB
+
AB VOUT
BB
parallel PMOS differential pair. The outputs from the differential input stages are combined in another gain stage whose output is used to drive a rail-to-rail output stage.
ΦA1
VOSA
+
VOA
ΦB
AA
CM2
The wide voltage swing of the amplifier is achieved by using two
–BA
ΦA2
CM1
output transistors in a common-source configuration. The output voltage range is limited by the drain-to-source resistance of these transistors. As the amplifier is required to source or sink more output current, the voltage drop across these transistors
increases due to their on resistance (RDS). Simply put, the output
VIN+
VNA
01104-050
Figure 50. Auto-Zero Phase of the Amplifier
VOSB
+
voltage does not swing as close to the rail under heavy output current conditions as it does with light output current. This is a
VIN–
ΦB
AB VOUT
BB
characteristic of all rail-to-rail output amplifiers. Figure 12 and Figure 13 show how close the output voltage can get to the rails with a given output current. The output of the AD8571/
ΦA VOSA
+
VOA
ΦB
AA
CM2
AD8572/AD8574 is short-circuit protected to approximately 50 mA of current.
–BA ΦA
CM1
The AD8571/AD8572/AD8574 amplifiers have exceptional gain, yielding greater than 120 dB of open-loop gain with a load of 2 kΩ. Because the output transistors are configured in a common-source configuration, the gain of the output stage, and thus the open-loop gain of the amplifier, is dependent on the load resistance. Open-loop gain decreases with smaller load resistances, which is another characteristic of rail-to-rail output amplifiers.
VNA
01104-051
Figure 51. Output Phase of the Amplifier
There are two modes of operation determined by the action of two sets of switches in the amplifier: an auto-zero phase and an amplification phase.
In this phase, all ΦAX switches are closed, and all ΦB switches are open. Here, the nulling amplifier is taken out of the gain loop by shorting its two inputs together. Of course, there is a degree of offset voltage, shown as VOSA, inherent in the nulling amplifier, that maintains a potential difference between the +IN
and −IN inputs. The nulling amplifier feedback loop is closed
For the sake of simplification, it can be assumed that the auto- correction frequency is much faster than any potential change in VOSA or VOSB. This is a good assumption because changes in offset voltage are a function of temperature variation or long- term wear time, both of which are much slower than the
auto-zero clock frequency of the AD8571/AD8572/AD8574, which effectively makes the VOS time invariant, and Equation 5
through ΦA2, and VOSA appears at the output of the nulling amplifier and on CM1, an internal capacitor in the AD8571/
can be rewritten as
V t A V
t AA (1 BA )VOSA AABAVOSA
(6)
AD8572/AD8574. Mathematically, this can be expressed in the time domain as
VOA[t] = AAVOSA[t] − BAVOA[t] (1)
This can also be expressed as
OA A IN
or
VOSA
1 BA
OA
V t AAVOSA t
(2)
VOA t AA VIN t
1 BA
(7)
1 BA
Here, the auto-zeroing becomes apparent. Note that the VOS
The previous equations show that the offset voltage of the nulling amplifier times a gain factor appears at the output of the nulling amplifier and thus on the CM1 capacitor.
When the ΦB switches close and the ΦAX switches open for the amplification phase, the offset voltage remains on CM1 and essentially corrects any error from the nulling amplifier. The
voltage across CM1 is designated as VNA. The potential difference
term is reduced by a factor of 1 + BA, which shows how the nulling amplifier has greatly reduced its own offset voltage error even before correcting the primary amplifier. Therefore, the primary amplifier output voltage is the voltage at the output of the AD8571/AD8572/AD8574 amplifier. It is equal to
VOUT[t] = AB(VIN[t] + VOSB) + BBVNB (8)
In the amplification phase, VOA = VNB, so this can be rewritten as
VOUT t
between the two inputs to the primary amplifier is designated as VIN, or VIN = (VIN+ − VIN−). The output of the nulling amplifier
A V t A V B A V t VOSA
B IN B OSB B A IN
1 B
(9)
can then be expressed as
VOA[t] = AA(VIN[t] − VOSA[t]) − BAVNA[t] (3)
Because ΦAX is now open and there is no place for CM1 to
Combining terms yield
VOUT t
A
discharge, the voltage (VNA) at the present time (t) is equal to
V tA A B AABBVOSA A V
(10)
the voltage at the output of the nulling amp (VOA) at the time when ΦAX is closed. If the period of the autocorrection switching
IN B A B
1 BA
B OSB
frequency is designated as TS, the amplifier switches between phases every 0.5 × TS. Therefore, in the amplification phase
The AD8571/AD8572/AD8574 architecture is optimized in such a way that AA = AB, BA = BB, and BA >> 1. In addition, the
NA NA t S
V t V 1 T
2
(4)
gain product to AABB is much greater than AB. Therefore,
Equation 10 can be simplified to
VOUT[t] = VIN[t]AABA + AA(VOSA+ VOSB) (11)
and substituting Equation 4 and Equation 2 into Equation 3 yields
A B V 1
Most obvious is the gain product of both the primary and nulling amplifiers. This AABA term is what gives the AD8571/AD8572/
A A OSA t 2 TS
VOA t AAVIN t AAVOSAt
1 BA
(5)
AD8574 extremely high open-loop gain. To understand how
VOSA and VOSB relate to the overall effective input offset voltage of the complete amplifier, set up the generic amplifier equation of
VOUT = k × (VIN + VOS, EFF) (12)
where:
k is the open-loop gain of an amplifier.
VOS, EFF is its effective offset voltage.
Putting Equation 12 into the form of Equation 11 gives
VOUT[t] = VIN[t]AABA + VOS, EFFAABA (13)
Therefore,
V V
R1 R2
V+
AD8572 R2 R1
VOS,EFF
OSA OSB
BA
(14)
VIN1
VIN2
Thus, the offset voltages of both the primary and nulling ampli- fiers are reduced by the gain factor BA, which takes a typical input offset voltage from several millivolts down to an effective input
01104-053
GUARD RING
VREF
V–
VREF
GUARD RING
offset voltage of submicrovolts. This autocorrection scheme makes the AD8571/AD8572/AD8574 amplifiers extremely precise.
Common-mode and power supply rejection are indications of the amount of offset voltage an amplifier has as a result of a change in its input common-mode or power supply voltages. As shown in the Amplification Phase section, the autocorrection architecture of the AD8571/AD8572/AD8574 allows it to effectively minimize offset voltages. The technique also corrects for offset errors caused by common-mode voltage swings and power supply variations, which results in superb CMRR and PSRR figures in excess of 130 dB. Because the autocorrection occurs continuously, these figures can be maintained across the temperature range of the device (−40°C to +125°C).
To achieve the maximum performance of the extremely high input impedance and low offset voltage of the AD8571/AD8572/ AD8574, care should be taken in the circuit board layout. The PCB surface must remain clean and free of moisture to avoid leakage currents between adjacent traces. Surface coating of the
Figure 53. Top View of AD8572 SOIC Layout with Guard Rings
Other potential sources of offset error are thermoelectric voltages on the circuit board. This voltage, also called Seebeck voltage, occurs at the junction of two dissimilar metals and is proportional to the junction temperature. The most common metallic junctions on a circuit board are solder-to-board trace and solder-to-component lead. Figure 54 shows a cross-section view of the thermal voltage error sources. When the temperature of the PCB at one end of the component (TA1) differs from the temperature at the other end (TA2), the Seebeck voltages are not equal, resulting in a thermal voltage error.
This thermocouple error can be reduced by using dummy components to match the thermoelectric error source. Placing the dummy component as close as possible to its partner ensures that both Seebeck voltages are equal, thus canceling the thermo- couple error. Maintaining a constant ambient temperature on the circuit board further reduces this error. The use of a ground plane helps distribute heat throughout the board and also reduces EMI noise pickup.
COMPONENT LEAD
SOLDER
circuit board reduces surface moisture and provides a humidity barrier, reducing parasitic resistance on the board. The use of guard rings around the amplifier inputs further reduces leakage currents. Figure 52 shows how the guard ring should be config- ured, and Figure 53 shows the top view of how a surface-mount
VSC1 +
VTS1 –
+
–
TA1
SURFACE MOUNT COMPONENT
PC BOARD
TA2
VSC2
+
– VTS2
+
–
layout can be arranged. The guard ring does not need to be a
COPPER TRACE
IF TA1 ≠ TA2, THEN
01104-054
V V ≠ V V
specific width, but it should form a continuous loop around both
TS1 + SC1 TS2 +
SC2
inputs. By setting the guard ring voltage equal to the voltage at the non-inverting input, parasitic capacitance is minimized as well. For further reduction of leakage currents, components can be mounted to the PCB using Teflon® standoff insulators.
Figure 54. Mismatch in Seebeck Voltages Causes a Thermoelectric Voltage Error
RF
R1
VOUT VOUT
VOUT
VIN AD8571/AD8572/
VIN
AD8572
VIN
AD8572
RS = R1
AD8574
01104-055
AV = 1 + (RF /R1)
VIN
AD8572
VOUT
RS SHOULD BE PLACED IN CLOSE PROXIMITY AND ALIGNMENT TO R1 TO BALANCE SEEBECK VOLTAGES
01104-052
Figure 55. Using Dummy Components to Cancel Thermoelectric Voltage Errors
Figure 52. Guard Ring Layout and Connections to Reduce PCB Leakage Currents
Another advantage of auto-zero amplifiers is their ability to cancel flicker noise. Flicker noise, also known as 1/f noise, is noise inherent in the physics of semiconductor devices and increases 3 dB for every octave decrease in frequency. The 1/f corner frequency of an amplifier is the frequency at which the flicker noise is equal to the broadband noise of the amplifier. At lower frequencies, flicker noise dominates, causing higher degrees of error for sub-Hertz frequencies or dc precision applications.
Because the AD8571/AD8572/AD8574 amplifiers are self- correcting op amps, they do not have increasing flicker noise at lower frequencies. In essence, low frequency noise is treated as a
0
–20
OUTPUT SIGNAL
–40
–60
–80
–100
–120
VS = 5V AV = 60dB
01104-057
0 1 2 3 4 5 6 7 8 9 10
FREQUENCY (kHz)
slowly varying offset error and is greatly reduced with autocorrection. The correction becomes more effective as the noise frequency approaches dc, offsetting the tendency of the noise to increase exponentially as frequency decreases, which allows the AD8571/AD8572/AD8574 to have lower noise near dc than standard low noise amplifiers that are susceptible to 1/f noise.
Figure 57. Spectral Analysis of AD8571/AD8572/AD8574 Output
with 60 dB Gain
Figure 58 shows the spectral output of an AD8572 configured in a high gain (60 dB) with a 1 mV input signal applied. Note the absence of any IMD products in the spectrum. The signal-to- noise ratio (SNR) of the output signal is better than 60 dB, or 0.1%.
0
VS = 5V
The AD8571/AD8572/AD8574 can be used as conventional op amps for gains up to 1 MHz. The auto-zero correction frequency of the device continuously varies, based on a pseudorandom generator with a uniform distribution from
2 kHz to 4 kHz. The randomization of the autocorrection clock creates a continuous randomization of IMD products that show up as simple broadband noise at the output of the amplifier. This broadband noise naturally combines with the amplifier voltage noise in a root-squared-sum fashion, resulting in an output free IMD. Figure 56 shows the spectral output of an AD8572 with the amplifier configured for unity gain and the input grounded.
–20
OUTPUT SIGNAL
–40
–60
–80
–100
–120
AV = 60dB
01104-058
0 1 2 3 4 5 6 7 8 9 10
FREQUENCY (kHz)
Figure 57 shows the spectral output with the amplifier configured for a gain of 60 dB.
0
Figure 58. Spectral Analysis of AD8572 in High Gain with an Input Signal
–20
–40
VS = 5V AV = 0dB
OUTPUT SIGNAL
–60
–80
–100
–120
01104-056
–140
–160
1 2 3 4 5 6 7 8 9 10
FREQUENCY (kHz)
Figure 56. Spectral Analysis of AD8572 Output in Unity Gain Configuration
The total broadband noise output from any amplifier is primarily a function of three types of noise: input voltage noise from the amplifier, input current noise from the amplifier, and Johnson noise from the external resistors used around the amplifier.
Input voltage noise, or en, is strictly a function of the amplifier used. The Johnson noise from a resistor is a function of the resistance and the temperature. Input current noise, or in, creates an equivalent voltage noise proportional to the resistors used around the amplifier. These noise sources are not correlated with each other and their combined noise sums in a root- squared-sum fashion. The full equation is given as
en, TOTAL = [en2 + 4kTrs + (inrs)2]1/2 (15)
where:
en is the input voltage noise of the amplifier.
in is the input current noise of the amplifier.
rs is the source resistance connected to the noninverting terminal.
k is Boltzmann’s constant (1.38 × 10−23 J/K).
T is the ambient temperature in Kelvin (K = 273.15 + °C).
The input voltage noise density, en, of the AD8571/AD8572/ AD8574 is 51 nV/√Hz, and the input noise, in, is 2 fA/√Hz. The en, TOTAL is dominated by the input voltage noise provided that the source resistance is less than 172 kΩ. With source resistance greater than 172 kΩ, the overall noise of the system is dominated by the Johnson noise of the resistor itself.
Because the input current noise of the AD8571/AD8572/ AD8574 is very small, in does not become a dominant term unless rs > 4 GΩ, which is an impractical value of source resistance.
The total noise, en, TOTAL, is expressed in volts-per-square-root Hertz, and the equivalent rms noise over a certain bandwidth can be found as
en = en, TOTAL × BW (16)
where BW is the bandwidth of interest in Hertz.
The AD8571/AD8572/AD8574 amplifiers have an excellent overdrive recovery of only 200 μs from either supply rail. This characteristic is particularly difficult for autocorrection amplifiers because the nulling amplifier requires a substantial amount of time to error correct the main amplifier back to a valid output. Figure 29 and Figure 30 show the positive and negative overdrive recovery times for the AD8571/AD8572/ AD8574.
The output overdrive recovery for an autocorrection amplifier is defined as the time it takes for the output to correct to its final voltage from an overload state. It is measured by placing the amplifier in a high gain configuration with an input signal that forces the output voltage to the supply rail. The input voltage is then stepped down to the linear region of the amplifier, usually to halfway between the supplies. The time from the input signal step-down to the output settling to within 100 μV of its final value is the overdrive recovery time. Many autocorrection amplifiers require a number of auto-zero clock cycles to recover from output overdrive, and some can take several milliseconds for the output to settle properly.
Although the AD8571/AD8572/AD8574 are rail-to-rail input amplifiers, care should be taken to ensure that the potential difference between the inputs does not exceed 5 V. Under normal operating conditions, the amplifier corrects its output to ensure that the two inputs are at the same voltage. However, if the device is configured as a comparator, or is under some unusual operating condition, the input voltages may be forced to different potentials, which could cause excessive current to flow through the internal diodes in the AD8571/AD8572/AD8574 used to protect the input stage against overvoltage.
If either input exceeds either supply rail by more than 0.3 V, large amounts of current begin to flow through the ESD protection diodes in the amplifier. These diodes are connected between the inputs and each supply rail to protect the input transistors against an electrostatic discharge event and are normally reverse-biased. However, if the input voltage exceeds the supply voltage, these ESD diodes become forward-biased. Without current-limiting, excessive amounts of current can flow through these diodes, causing permanent damage to the device. If inputs are subject to overvoltage, appropriate series resistors should be inserted to limit the diode current to less than 2 mA.
Output phase reversal occurs in some amplifiers when the input common-mode voltage range is exceeded. As common-mode voltage moves outside the common-mode range, the outputs of these amplifiers suddenly jump in the opposite direction to
the supply rail. This is the result of the differential input pair shutting down, causing a radical shifting of internal voltages that results in the erratic output behavior.
The AD8571/AD8572/AD8574 amplifiers have been carefully designed to prevent any output phase reversal, provided that both inputs are maintained within the supply voltages. If one or both inputs exceed either supply voltage, a resistor should be placed in series with the input to limit the current to less than
2 mA to ensure that the output does not reverse its phase.
The AD8571/AD8572/AD8574 have excellent capacitive load driving capabilities and can safely drive up to 10 nF from a single 5 V supply. Although the device is stable, capacitive loading limits the bandwidth of the amplifier. Capacitive loads also increase the amount of overshoot and ringing at the output. The RC snubber network shown in Figure 59 can be used to reduce the capacitive load ringing and overshoot.
The optimum value for the resistor and capacitor is a function of the load capacitance and is best determined empirically because actual CL includes stray capacitances and can differ substantially from the nominal capacitive load. Table 5 shows some snubber network values that can be used as starting points.
CL (nF) | Rx (Ω) | Cx |
1 | 200 | 1 nF |
4.7 | 60 | 0.47 µF |
10 | 20 | 10 µF |
Table 5. Snubber Network Values for Driving Capacitive Loads
5V
–
VIN +
AD8571/ AD8572/ AD8574
Rx
VOUT
01104-059
200mV p-p
60Ω
Cx 0.47µF
CL 4.7nF
At power-up, the AD8571/AD8572/AD8574 settle to a valid output within 5 μs. Figure 61 shows an oscilloscope photo of the
Figure 59. Snubber Network Configuration for Driving Capacitive Loads
Although the snubber network does not recover the loss of amplifier bandwidth from the load capacitance, it does allow the amplifier to drive larger values of capacitance while maintaining a minimum of overshoot and ringing. Figure 60 shows the output of an AD8571/AD8572/AD8574 driving a 1 nF capacitor with and without a snubber network.
10μs
WITH SNUBBER
WITHOUT SNUBBER
output of the amplifier along with the power supply voltage. Figure 62 shows the test circuit. With the amplifier configured for unity gain, the device takes approximately 5 µs to settle to its final output voltage, hundreds of microseconds faster than many other autocorrection amplifiers.
5µs | 1V |
VOUT
0V
V+ 0V
VS = 5V CL = 4.7nF
100mV
BOTTOM TRACE = 2V/DIV TOP TRACE = 1V/DIV
01104-060
01104-061
Figure 61. AD8571/AD8572/AD8574 Output Behavior at Power-Up
Figure 60. Overshoot and Ringing Are Substantially Reduced Using a Snubber Network
100kΩ
VSY = 0V TO 5V
100kΩ
AD8571/ AD8572/ AD8574
VOUT
01104-062
Figure 62. AD8571/AD8572/AD8574 Test Circuit for Power-Up Time
The extremely low offset voltage of the AD8572 makes it an ideal amplifier for any application requiring accuracy with high gains, such as a weigh scale or strain gage. Figure 63 shows a configura- tion for a single-supply, precision strain gage measurement system.
R2
R1
V2
R3 VOUT
V1 AD8571/
01104-064
R4 AD8572/ AD8574
R4 R2
IF = , THEN V
= R2 (V1 – V2)
The REF192 provides a 2.5 V precision reference voltage for A2.
R3 R1
OUT R1
The A2 amplifier boosts this voltage to provide a 4.0 V reference for the top of the strain gage resistor bridge. Q1 provides the current drive for the 350 Ω bridge network. A1 is used to amplify the output of the bridge with the full-scale output voltage equal to
Figure 64. Using the AD8571/AD8572/AD8574 as a Difference Amplifier
In an ideal difference amplifier, the ratio of the resistors is set equal to
2 R1 R2
A R2 R4
(19)
(17)
RB
where RB is the resistance of the load cell.
Using the values given in Figure 63, the output voltage linearly varies from 0 V with no strain to 4 V under full strain.
V R1 R3
Set the output voltage of the system to
VOUT = AV (V1 − V2) (20)
Due to finite component tolerance, the ratio between the four resistors is not exactly equal, and any mismatch results in a reduction of common-mode rejection from the system. Referring
Q1 2N2222
OR EQUIVALENT
4.0V
1kΩ
AD8572-B
12kΩ
5V
2.5V 6
A2
20kΩ
R1 R2
2
3
REF192
4
to Figure 64, the exact common-mode rejection ratio can be expressed as
CMRR R1R4 2R2R4 R2R3 (21)
2R1R4 2R2R3
In the 3-op amp instrumentation amplifier configuration shown
350Ω LOAD CELL
40mV FULL-SCALE
17.4kΩ
A1
R3
100Ω
AD8572-A
R4
VOUT
0V TO 4V
in Figure 65, the output difference amplifier is set to unity gain with all four resistors equal in value. If the tolerance of the resistors used in the circuit is given as δ, the worst-case CMRR of the instrumentation amplifier is
01104-063
1
NOTE:
USE 0.1% TOLERANCE RESISTORS.
17.4kΩ
100Ω
CMRR
MIN
2
(22)
Figure 63. 5 V Precision Strain Gage Amplifier
The high common-mode rejection, high open-loop gain, and operation down to 3 V of the supply voltage make the AD8571/AD8572/AD8574 an excellent op amp choice for discrete single-supply instrumentation amplifiers. The common-mode rejection ratio of the AD8571/AD8572/ AD8574 is greater than 120 dB, but the CMRR of the system is also a function of the external resistor tolerances. The gain
V2
RG
V1
VOUT
AD8574-A
R R
AD8574-B
= 1 + 2R (V1 – V2) RG
R R
01104-065
R RTRIM
R
AD8574-C
VOUT
of the difference amplifier shown in Figure 64 is given as
Figure 65. Discrete Instrumentation Amplifier Configuration
V V1 R4 1 R1 V 2 R2
(18)
Therefore, using 1% tolerance resistors results in a worst-case
OUT
R3 R4 R2 R1
system CMRR of 0.02, or 34 dB. To achieve high common- mode rejection, either high precision resistors or an additional trimming resistor, as shown in Figure 65, should be used. The value of this trimming resistor should be equal to the value of R multiplied by its tolerance. For example, using 10 kΩ resistors with 1% tolerance would require a series trimming resistor equal to 100 Ω.
Figure 66 shows a K-type thermocouple amplifier configuration with cold-junction compensation. Even from a 5 V supply, the AD8571 can provide enough accuracy to achieve a resolution of better than 0.02°C from 0°C to 500°C. D1 is used as a tempera- ture measuring device to correct the cold-junction error from the thermocouple and should be placed as close as possible to the two terminating junctions. With the thermocouple measuring
through R2. The monitor output is given by
Monitor Output = R2 × (RSENSE/R1) × IL (23)
Using the components shown in Figure 67, the monitor output transfer function is 2.49 V/A.
RSENSE IL
0.1Ω
V+
V+
0.1µF
tip immersed in a 0°C ice bath, R6 should be adjusted until the output is at 0 V.
R1 100Ω
3 8
+
1/2 1
LOAD
AD8572
2
Using the values shown in Figure 66, the output voltage tracks temperature at 10 mV/°C. For a wider range of temperature
measurement, R9 can be decreased to 62 kΩ. This creates a
– 4
S
M1 G
Si9433
5 mV/°C change at the output, allowing measurements of up to 1000°C.
MONITOR OUTPUT
D
01104-067
R2 2.49kΩ
REF02EZ 5V
12V 2 6
Figure 67. High-Side Load Current Monitor
0.1µF
4
R1 10.7kΩ
1N4148 D1
R5
40.2kΩ R9
124kΩ
5V
+
10µF
Figure 68 shows the low-side monitor equivalent. In this circuit, the input common-mode voltage to the AD8572 is at or near ground. Again, a 0.1 Ω resistor provides a voltage drop propor- tional to the return current. The output voltage is given as
K-TYPE – – THERMOCOUPLE + +
R2 2.74kΩ
R8 453Ω 2
0.1µF
7
6
Monitor Output V
R2 R
R1
SENSE I
(24)
40.7µV/°C
R4 5.62kΩ
R6
200Ω
R3 53.6Ω
3
L
4 AD8571
0V TO 5V
(0°C TO 500°C)
For the component values shown in Figure 68, the monitor
output transfer function is V+ − 2.49 V/A.
V+
01104-066
Figure 66. Precision K-Type Thermocouple Amplifier with Cold-Junction Compensation
Because of its low input bias current and superb offset voltage at single-supply voltages, the AD8571/AD8572/AD8574 are excellent amplifiers for precision current monitoring. Its rail-to-
MONITOR OUTPUT
R2 2.49kΩ
Q1
R1
V+
V+
2
3
1/2 AD8572
LOAD
rail input allows the amplifier to be used as either a high-side or a low-side current monitor. Using both amplifiers in the
100Ω
RSENSE
01104-068
0.1Ω
IL
AD8572 provides a simple method to monitor both current supply and return paths for load or fault detection.
Figure 67 shows a high-side current monitor configuration. Here, the input common-mode voltage of the amplifier is at or near the positive supply voltage. The rail-to-rail input of the amplifier provides a precise measurement, even with the input common-mode voltage at the supply voltage. The CMOS input structure does not draw any input bias current, ensuring a minimum of measurement error.
The 0.1 Ω resistor creates a voltage drop to the noninverting input of the AD8571/AD8572/AD8574. The output of the amplifier is corrected until this voltage appears at the inverting input, which creates a current through R1 that in turn flows
Figure 68. Low-Side Load Current Monitor
The AD8571/AD8572/AD8574 can be operated open loop and used as a precision comparator. The AD8571/AD8572/AD8574 have less than 50 µV of offset voltage when they run in this configuration. The slight increase of offset voltage stems from the fact that the autocorrection architecture operates with the lowest offset in a closed-loop configuration, that is, one with negative feedback. With 50 mV of overdrive, the device has a propagation delay of 15 µs on the rising edge and 8 µs on the falling edge.
Care should be taken to ensure that the maximum differential voltage of the device is not exceeded. For more information, see the Input Overvoltage Protection section.
3.20
3.00
2.80
3.20
3.00
2.80
5.15
8 | 5 |
1 | 4 |
4.90
4.65
PIN 1 IDENTIFIER
0.65 BSC
0.95
0.85
0.75
0.15
0.05
COPLANARITY 0.10
0.40
0.25
1.10 MAX
6°
0°
15° MAX
0.23
0.09
0.80
0.55
10-07-2009-B
0.40
COMPLIANT TO JEDEC STANDARDS MO-187-AA
Figure 69. 8-Lead Mini Small Outline Package [MSOP] (RM-8)
Dimensions shown in millimeters
5.00 (0.1968)
4.80 (0.1890)
4.00 (0.1574)
3.80 (0.1497)
8
5
6.20 (0.2441)
4
1
5.80 (0.2284)
1.27 (0.0500) 0.50 (0.0196)
45°
0.25 (0.0098)
0.10 (0.0040)
BSC
1.75 (0.0688)
1.35 (0.0532) 8°
0°
0.25 (0.0099)
COPLANARITY
0.51 (0.0201)
1.27 (0.0500)
0.10
SEATING PLANE
0.31 (0.0122)
0.25 (0.0098)
0.17 (0.0067)
0.40 (0.0157)
COMPLIANT TO JEDEC STANDARDS MS-012-AA
012407-A
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
Figure 70. 8-Lead Standard Small Outline Package [SOIC_N] Narrow Body (R-8)
Dimensions shown in millimeters and (inches)
3.10
3.00 2.90
8 5
4.50
4.40
4.30
6.40 BSC
1 4
PIN 1
0.65 BSC
0.15 1.20
0.05
MAX
8°
COPLANARITY 0.10
0.30
0.19
SEATING PLANE
0.20 0° 0.09
0.75
0.60
0.45
COMPLIANT TO JEDEC STANDARDS MO-153-AA
Figure 71. 8-Lead Thin Shrink Small Outline Package [TSSOP] (RU-8)
Dimensions shown in millimeters
5.10
5.00
4.90
4.50
4.40
4.30
14 8
6.40
BSC
1 7
PIN 1
1.05
1.00
0.65 BSC
1.20
0.20
0.80
MAX
0.09 0.75
0.15
0.05 0.30
8°
SEATING 0°
PLANE
0.60
0.45
COPLANARITY 0.10
0.19
061908-A
COMPLIANT TO JEDEC STANDARDS MO-153-AB-1
Figure 72. 14-Lead Thin Shrink Small Outline Package [TSSOP] (RU-14)
Dimensions shown in millimeters
8.75 (0.3445)
8.55 (0.3366)
4.00 (0.1575)
3.80 (0.1496)
6.20 (0.2441)
7
8
14
1
5.80 (0.2283)
0.25 (0.0098)
0.10 (0.0039) COP
1.27 (0.0500) BSC
1.75 (0.0689)
1.35 (0.0531)
0.50 (0.0197)
0.25 (0.0098)
8°
0°
LANARITY 0.10 | 0.51 (0.0201) | SEATING PLANE | 0.25 (0.0098) |
0.31 (0.0122) | 0.17 (0.0067) |
1.27 (0.0500)
0.40 (0.0157)
45°
COMPLIANT TO JEDEC STANDARDS MS-012-AB
060606-A
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
Figure 73. 14-Lead Standard Small Outline Package [SOIC_N] Narrow Body (R-14)
Dimensions shown in millimeters and (inches)
Model1 | Temperature Range | Package Description | Package Option | Branding |
AD8571ARZ | −40°C to +125°C | 8-Lead SOIC_N | R-8 | |
AD8571ARZ-REEL | −40°C to +125°C | 8-Lead SOIC_N | R-8 | |
AD8571ARZ-REEL7 | −40°C to +125°C | 8-Lead SOIC_N | R-8 | |
AD8571ARMZ | −40°C to +125°C | 8-Lead MSOP | RM-8 | AJA# |
AD8571ARMZ-REEL | −40°C to +125°C | 8-Lead MSOP | RM-8 | AJA# |
AD8572AR | −40°C to +125°C | 8-Lead SOIC_N | R-8 | |
AD8572AR-REEL | −40°C to +125°C | 8-Lead SOIC_N | R-8 | |
AD8572AR-REEL7 | −40°C to +125°C | 8-Lead SOIC_N | R-8 | |
AD8572ARZ | −40°C to +125°C | 8-Lead SOIC_N | R-8 | |
AD8572ARZ-REEL | −40°C to +125°C | 8-Lead SOIC_N | R-8 | |
AD8572ARZ-REEL7 | −40°C to +125°C | 8-Lead SOIC_N | R-8 | |
AD8572ARUZ | −40°C to +125°C | 8-Lead TSSOP | RU-8 | |
AD8572ARUZ-REEL | −40°C to +125°C | 8-Lead TSSOP | RU-8 | |
AD8574ARZ | −40°C to +125°C | 14-Lead SOIC_N | R-14 | |
AD8574ARZ-REEL | −40°C to +125°C | 14-Lead SOIC_N | R-14 | |
AD8574ARZ-REEL7 | −40°C to +125°C | 14-Lead SOIC_N | R-14 | |
AD8574ARU | −40°C to +125°C | 14-Lead TSSOP | RU-14 | |
AD8574ARU-REEL | −40°C to +125°C | 14-Lead TSSOP | RU-14 | |
AD8574ARUZ | −40°C to +125°C | 14-Lead TSSOP | RU-14 | |
AD8574ARUZ-REEL | −40°C to +125°C | 14-Lead TSSOP | RU-14 |
1 Z = RoHS Compliant Part, # denotes RoHS compliant product may be top or bottom marked.
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