Data Sheet
2
1
High slew rate: 9 V/µs Wide bandwidth: 4 MHz
Low supply current: 250 µA/amplifier maximum Low offset voltage: 3 mV maximum
Low bias current: 100 pA maximum
OUT A
–IN A
+IN A V–
V+ OUT B
6
OP282
7
8
00301-001
–IN B
5
OP-482
+IN B
4
3
Fast settling time
Common-mode range includes V+
Figure 1. 8-Lead, Narrow-Body SOIC (S-Suffix) [R-8]
Unity-gain stable
14-ball wafer level chip scale for quad
OUT A 1
–IN A 2
+IN A 3
V– 4
OP282
TOP VIEW
(Not to Scale)
8 V+
7 OUT B
00301-002
6 –IN B
5 +IN B
3
1
Active filters Fast amplifiers
Figure 2. 8-Lead MSOP [RM-8]
Integrators
Supply current monitoring
The OP282/OP482 dual and quad operational amplifiers feature excellent speed at exceptionally low supply currents. The slew rate is typically 9 V/µs with a supply current of less than 250 µA per amplifier. These unity-gain stable amplifiers have a typical
OUT A
–IN A
+IN A V+
+IN B
–IN B OUT B
2
4
5
6
– + + –
7
14 OUT D
13
– + + –
–IN D
10
11
OP482
12
+IN D V–
+IN C
8
9
00301-003
–IN C OUT C
gain bandwidth of 4 MHz.
Figure 3. 14-Lead PDIP (P-Suffix) [N-14]
The JFET input stage of the OP282/OP482 ensures that the bias current is typically a few picoamps and is less than 500 pA over the full temperature range. The offset voltage is less than 3 mV for the dual amplifier and less than 4 mV for the quad amplifier.
With a wide output swing (within 1.5 V of each supply), low power consumption, and high slew rate, the OP282/OP482 are ideal for battery-powered systems or power-restricted applica- tions. An input common-mode range that includes the positive
OUT A
–IN A
+IN A V+
+IN B
–IN B OUT B
OUT D
1 | 14 | |
2 | 13 | |
3 | 12 | |
4 | OP482 | 11 |
5 | 10 | |
6 | 9 | |
7 | 8 |
–IN D
+IN D V–
+IN C
00301-004
–IN C OUT C
supply makes the OP282/OP482 an excellent choice for high- side signal conditioning.
Figure 4. 14-Lead, Narrow-Body SOIC (S-Suffix) [R-14]
BALL A1 CORNER
1 2 3
The OP282/OP482 are specified over the extended industrial temperature range. The OP282 is available in the standard
8-lead, narrow SOIC and MSOP packages. The OP482 is available in the PDIP and narrow SOIC packages, as well as a 14-ball WLCSP.
OUT D
A
B +IN D
C
D V–
E
F +IN C
G
H OUT C
J
–IN D
+IN A
+IN B
–IN C
OUT A
–IN A
V+
–IN B
OUT B
00301-048
TOP VIEW (BALL SIDE DOWN)
Not to Scale
Figure 5. 14-Ball WLCSP [CB-14-2]
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibilityis assumedby AnalogDevicesforitsuse, norforanyinfringements ofpatents orother rightsofthirdpartiesthatmayresultfromitsuse.Specificationssubjecttochangewithoutnotice.No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
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Typical Performance Characteristics 5
High-Side Signal Conditioning 12
Programmable State Variable Filter 13
9/13—Rev. H to Rev. I
Changes to Figure 5 1
Updated Outline Dimensions 14
Changes to Ordering Guide 16
9/10—Rev. G to Rev. H
Added WLCSP ....................................................................Universal
Changes to Features Section 1
Changes to General Description Section 1
Added Figure 5; Renumbered Sequentially 1
Changes to Large-Signal Voltage Gain Parameter, Table 1 3
Changes to Table 2, Thermal Resistance Section, and Table 3 ... 4 Change to Figure 30 9
Added Figure 53 16
Changes to Ordering Guide 16
7/08—Rev. F to Rev. G
Changes to Phase Inversion Section 12
Deleted Figure 45 12
Added Figure 45 and Figure 46 12
Updated Outline Dimensions 14
Changes to Ordering Guide 16
10/04—Rev. E to Rev. F
Deleted 8-Lead PDIP .........................................................Universal
Added 8-Lead MSOP .........................................................Universal
Changes to Format and Layout.........................................Universal Changes to Features 1
Changes to Pin Configurations 1
Changes to General Description 1
Changes to Specifications 3
Changes to Absolute Maximum Ratings 4
Changes to Table 3 4
Added Figure 5 through Figure 20; Renumbered
Successive Figures 5
Updated Figure 21 and Figure 22 7
Updated Figure 23 and Figure 27 8
Updated Figure 29 9
Updated Figure 35 and Figure 36 10
Updated Figure 43 11
Changes to Applications Information 12
Changes to Figure 44 12
Deleted OP282/OP482 Spice Macro Model Section 9
Deleted Figure 4 9
Deleted OP282 Spice Marco Model 10
Updated Outline Dimensions 14
Changes to Ordering Guide 14
10/02—Rev. D to Rev. E
Edits to 8-Lead Epoxy DIP (P-Suffix) Pin 1
Edits to Ordering Guide 3
Edits to Outline Dimensions 11
9/02—Rev. C to Rev. D
Edits to 14-Lead SOIC (S-Suffix) Pin 1
Replaced 8-Lead SOIC (S-Suffix) 11
4/02—Rev. B to Rev. C
Wafer Test Limits Deleted 2
Edits to Absolute Maximum Ratings 3
Dice Characteristics Deleted 3
Edits to Ordering Guide 3
Edits to Figure 1 7
Edits to Figure 3 8
20-Position Chip Carrier (RC Suffix) Deleted 11
At VS = ±15.0 V, TA = 25°C, unless otherwise noted; applies to both A and G grades.
Table 1.
Parameter | Symbol | Test Conditions/Comments | Min | Typ | Max | Unit |
INPUT CHARACTERISTICS | ||||||
Offset Voltage | VOS | 0.2 3 | mV | |||
OP282, −40°C ≤ TA ≤ +85°C | 4.5 | mV | ||||
0.2 4 | mV | |||||
OP482, −40°C ≤ TA ≤ +85°C | 6 | mV | ||||
Input Bias Current | IB | VCM = 0 V | 3 | 100 | pA | |
500 | pA | |||||
Input Offset Current | IOS | VCM = 0 V | 1 | 50 | pA | |
250 | pA | |||||
Input Voltage Range | −11 | +15 | V | |||
Common-Mode Rejection Ratio | CMRR | −11 V ≤ VCM ≤ +15 V, −40°C ≤ TA ≤ +85°C | 70 | 90 | dB | |
Large-Signal Voltage Gain | AVO | RL = 10 kΩ, VO = ±13.5 V | 20 | V/mV | ||
RL = 10 kΩ, −40°C ≤ TA ≤ +85°C | 15 | V/mV | ||||
Offset Voltage Drift | ΔVOS/ΔT | 10 | µV/°C | |||
Bias Current Drift | ΔIB/ΔT | 8 | pA/°C | |||
OUTPUT CHARACTERISTICS Output Voltage High Output Voltage Low Short-Circuit Limit Open-Loop Output Impedance | VOH VOL ISC ZOUT | RL = 10 kΩ RL = 10 kΩ Source Sink f = 1 MHz | 13.5 3 | 13.9 −13.9 10 −12 200 | −13.5 −8 | V V mA mA Ω |
POWER SUPPLY | ||||||
Power Supply Rejection Ratio | PSRR | VS = ±4.5 V to ±18 V, −40°C ≤ TA ≤ +85°C | 25 | 316 | µV/V | |
Supply Current/Amplifier | ISY | VO = 0 V, −40°C ≤ TA ≤ 85°C | 210 | 250 | µA | |
Supply Voltage Range | VS | ±4.5 | ±18 | V | ||
DYNAMIC PERFORMANCE | ||||||
Slew Rate | SR | RL = 10 kΩ | 7 | 9 | V/µs | |
Full-Power Bandwidth | BWP | 1% distortion | 125 | kHz | ||
Settling Time | tS | To 0.01% | 1.6 | µs | ||
Gain Bandwidth Product | GBP | 4 | MHz | |||
Phase Margin | ØM | 55 | Degrees | |||
NOISE PERFORMANCE | ||||||
Voltage Noise | en p-p | 0.1 Hz to 10 Hz | 1.3 | µV p-p | ||
Voltage Noise Density | en | f = 1 kHz | 36 | nV/√Hz | ||
Current Noise Density | in | 0.01 | pA/√Hz |
1 The input bias and offset currents are characterized at TA = TJ = 85°C. Bias and offset currents are guaranteed but not tested at −40°C.
Table 2.
Parameter | Rating |
Supply Voltage | ±18 V |
Input Voltage | ±18 V |
36 V | |
Output Short-Circuit Duration | Indefinite |
Storage Temperature Range | −65°C to +150°C |
Operating Temperature Range | −40°C to +85°C |
Junction Temperature Range | −65°C to +150°C |
Lead Temperature (Soldering 60 sec) | 300°C |
1 For supply voltages less than ±18 V, the absolute maximum input voltage is equal to the supply voltage.
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
θJA is specified for the worst-case conditions, that is, a device in socket for PDIP. θJA is specified for a device soldered in the circuit board for SOIC_N, MSOP, and WLCSP packages. This was measured using a standard 4-layer board.
Table 3.
Package Type | θJA | θJC | Unit |
8-Lead MSOP [RM] | 142 | 45 | °C/W |
8-Lead SOIC_N (S-Suffix) [R] | 120 | 45 | °C/W |
14-Lead PDIP (P-Suffix) [N] | 83 | 39 | °C/W |
14-Lead SOIC_N (S-Suffix) [R] | 112 | 35 | °C/W |
70 | 16 | °C/W |
1 Simulated thermal numbers per JESD51-9.
2 Junction-to-board thermal resistance.
VS = ±15V TA = 25°C
80 180 70
60
60 135
50
VS = ±15V TA = 25°C
AVCL = 100
OPEN-LOOP GAIN (dB)
CLOSED-LOOP GAIN (dB)
40
PHASE (Degrees)
40 90
AVCL = 10
30
20 45 20
AVCL = 1
10
0 0
0
–20
–45
–10
00301-008
–20
–40
1k
10k
100k FREQUENCY (Hz)
–90
1M 10M
–30
1k
10k
100k FREQUENCY (Hz)
1M 10M
00301-005
Figure 6. OP282 Open-Loop Gain and Phase vs. Frequency Figure 9. OP282 Closed-Loop Gain vs. Frequency
VS = ±15V RL = 10kΩ CL = 50pF | ||||||||
–SR | ||||||||
+SR | ||||||||
45 30
VS = ±15V
40 RL = 10kΩ
25
OPEN-LOOP GAIN (V/mV)
35
SLEW RATE (V/µs)
30 20
25
15
20
15 10
10
5
00301-006
00301-009
5
0
–75
–50
–25 0
25 50
75 100 125
0
–75
–50
–25 0
25 50
75 100 125
TEMPERATURE (°C)
Figure 7. OP282 Open-Loop Gain vs. Temperature
TEMPERATURE (°C)
Figure 10. OP282 Slew Rate vs. Temperature
VS = ±15V RL = 2kΩ VIN = 100mV p-p AVCL = 1 TA = 25°C | |||||
+OS | |||||
–OS | |||||
VS = ±15V VCM = 0V | |||||||
80 1000
70
INPUT BIAS CURRENT (pA)
60 100
OVERSHOOT (%)
50
40 10
30
20 1
00301-007
00301-010
10
0
0 100
200
300
400 500
0.1
–75
–50
–25 0
25 50
75 100 125
LOAD CAPACITANCE (pF)
Figure 8. OP282 Small-Signal Overshoot vs. Load Capacitance
TEMPERATURE (°C)
Figure 11. OP282 Input Bias Current vs. Temperature
VOLTAGE NOISE DENSITY (nV/√Hz)
1000
100
10
20
VS = ±15V TA = 25°C
TA = 25°C RL = 10kΩ | |||
VOH | |||
VOL | |||
15
OUTPUT VOLTAGE SWING (V)
10
5
0
–5
–10
00301-014
–15
1
10 100 1k FREQUENCY (Hz)
00301-011
10k
–20
0
±5 ±10
SUPPLY VOLTAGE (V)
±15
±20
Figure 12. OP282 Voltage Noise Density vs. Frequency Figure 15. OP282 Output Voltage Swing vs. Supply Voltage
1000
INPUT BIAS CURRENT (pA)
100
10
1
VS = ±15V TA = 25°C
1000
OUTPUT IMPEDANCE (Ω)
VS = ±15V TA = 25°C | |||||||||||||||||||||||||||
AVCL = 100 | |||||||||||||||||||||||||||
AVCL = 10 | |||||||||||||||||||||||||||
AVCL = 1 | |||||||||||||||||||||||||||
100
10
1
0.1
–15
00301-015
–10 –5 0
00301-012
5 10 15
0.1
100
1k 10k
100k 1M
COMMON-MODE VOLTAGE (V)
Figure 13. OP282 Input Bias Current vs. Common-Mode Voltage
FREQUENCY (Hz)
Figure 16. OP282 Closed-Loop Output Impedance vs. Frequency
TA = 25°C | |||
480 480
475 475
SUPPLY CURRENT (µA)
SUPPLY CURRENT (µA)
470 470
465 465
460 460
455 455
450
0
±5 ±10
±15
00301-013
±20
450
–50
–25 0
25 50
75 100
00301-016
125
SUPPLY VOLTAGE (V)
Figure 14. OP282 Supply Current vs. Supply Voltage
TEMPERATURE (°C)
Figure 17. OP282 Supply Current vs. Temperature
VS = ±15V TA = 25°C | |||||||||||||||||
VOL | |||||||||||||||||
VOH | |||||||||||||||||
16 30
14
ABSOLUTE OUTPUT VOLTAGE (V)
MAXIMUM OUTPUT SWING (V p-p)
25
12
20
10
8 15
6
10
4
5
00301-017
2
VS = ±15V TA = 25°C RL = 10kΩ AVCL = 1
0
100
00301-020
1k 10k
LOAD RESISTANCE (Ω)
0
100
1k 10k
FREQUENCY (Hz)
100k 1M
Figure 18. OP282 Absolute Output Voltage vs. Load Resistance Figure 21. OP282 Maximum Output Swing vs. Frequency
140
120
VS = ±15V TA = 25°C
140
120
VS = ±15V TA = 25°C
100
80
+PSRR
100
80
PSRR (dB)
CMRR (dB)
60 60
40 40
20 –PSRR 20
0 0
–20 –20
00301-018
00301-021
–40 –40
–60
100
1k 10k
100k 1M
–60
100
1k 10k
100k 1M
FREQUENCY (Hz)
VS = ±15V TA = 25°C
Figure 19. OP282 PSRR vs. Frequency
FREQUENCY (Hz)
Figure 22. OP282 CMRR vs. Frequency
14
SHORT-CIRCUIT CURRENT (mA)
12
10 SINK
8
SOURCE
6
200
160
UNITS
120
80
VS = ±15V TA = 25°C 300 × OP282
(600 OP AMPS)
4
40
00301-022
2
0
–50
–25 0
25 50
75 100
125
0
–2000
–1200
–400 0
400 1200 2000
TEMPERATURE (°C)
Figure 20. OP282 Short-Circuit Current vs. Temperature
VOS (µV)
Figure 23. OP282 VOS Distribution, SOIC_N Package
400
360
320
280
UNITS
240
200
160
120
80
40
VS = ±15V 300 × OP282
(600 OP AMPS)
70
VS = ±15V
60 RL = 2kΩ
VIN = 100mV p-p
OVERSHOOT (%)
50
40
30
20
10
AVCL = 1 NEGATIVE EDGE
AVCL = 1 POSITIVE EDGE
0
0 4 8
00301-026
12 16
20 24
28 32 36
0
0 100 200
00301-023
300
400
500
TCVOS (µV/°C)
Figure 24. OP282 TCVOS Distribution, SOIC_N Package
LOAD CAPACITANCE (pF)
Figure 27. OP482 Small-Signal Overshoot vs. Load Capacitance
VS = ±15V TA = 25°C | ||||||||||||||||||||||||
VS = ±15V TA = 25°C | |||||||||||||||||||||||||
AVCL = 100 | |||||||||||||||||||||||||
AVCL = 10 | |||||||||||||||||||||||||
AVCL = 1 | |||||||||||||||||||||||||
80 0 60
50
60 45
OPEN-LOOP GAIN (dB)
CLOSED-LOOP GAIN (dB)
40
PHASE (Degrees)
40 90 30
20
20 135
10
0
1k 10k 100k 1M FREQUENCY (Hz)
10M
180
100M
0
–10
–20
1k 10k 100k 1M
FREQUENCY (Hz)
10M
00301-027
100M
00301-024
Figure 25. OP482 Open-Loop Gain and Phase vs. Frequency Figure 28. OP482 Closed-Loop Gain vs. Frequency
–SR | ||||||||
VS = ±15V RL = 10kΩ CL = 50pF | ||||||||
+SR | ||||||||
35 25
VS = ±15V
30 RL = 10kΩ
OPEN-LOOP GAIN (V/mV)
20
SLEW RATE (V/µs)
25
20 15
15
10
10
5
00301-025
00301-028
5
0
–75 –50 –25 0
25 50 75
100
125
0
–75
–50 –25 0 25 50 75 100 125
TEMPERATURE (°C)
Figure 26. OP482 Open-Loop Gain vs. Temperature
TEMPERATURE (°C)
Figure 29. OP482 Slew Rate vs. Temperature
1000
INPUT BIAS CURRENT (pA)
100
10
1.0
1000
INPUT BIAS CURRENT (pA)
VS = ±15V TA = 25°C | |||||
100
10
1
VS = ±15V VCM = 0V | |||||||
0.1
–75
00301-032
–50
–25 0
25 50
75 100
00301-029
125
0.1
–15
–10 –5
0 5 10 15
TEMPERATURE (°C)
Figure 30. OP482 Input Bias Current vs. Temperature
COMMON-MODE VOLTAGE (V)
Figure 33. OP482 Input Bias Current vs. Common-Mode Voltage
VS = ±15V RL = 10kΩ | |||||||
GBW ØM | |||||||
60 5.0
PHASE MARGIN (Degrees)
GAIN BANDWIDTH PRODUCT (MHz)
55 4.5
50 4.0
45 3.5
1.15
RELATIVE SUPPLY CURRENT (ISY)
TA = 25°C | |||
1.10
1.05
1.00
0.95
00301-033
0.90
40
–75
3.0
–50 –25 0 25 50 75 100 125
TEMPERATURE (°C)
0.85
0
±5 ±10
SUPPLY VOLTAGE (V)
±15
±20
00301-030
Figure 31. OP482 Phase Margin and Gain Bandwidth Product vs.
Temperature
Figure 34. OP482 Relative Supply Current vs. Supply Voltage
VS = ±15V TA = 25°C | ||||||||||||||
RL = 10kΩ TA = 25°C | |||
80 20
VOLTAGE NOISE DENSITY (nV/√Hz)
70 15
OUTPUT VOLTAGE SWING (V)
60 10
50 5
40 0
30 –5
20 –10
00301-031
00301-034
10 –15
0
10 100 1k 10k
FREQUENCY (Hz)
–20
0
±5 ±10
SUPPLY VOLTAGE (V)
±15
±20
Figure 32. OP482 Voltage Noise Density vs. Frequency Figure 35. OP482 Output Voltage Swing vs. Supply Voltage
600
500
IMPEDANCE (Ω)
400
VS = ±15V TA = 25°C
100
80
60
+PSRR
–PSRR
VS = ±15V ΔV = 100mV TA = 25°C
PSRR (dB)
300 40
200
100
AVCL = 100
20
AVCL = 10
0
00301-035
00301-038
AVCL = 1
0
100
1k 10k
FREQUENCY (Hz)
100k 1M
20
100
1k 10k
FREQUENCY (Hz)
100k 1M
Figure 36. OP482 Closed-Loop Output Impedance vs. Frequency Figure 39. OP482 Power Supply Rejection Ratio (PSRR) vs. Frequency
SINK | VS = ±15V | ||||||
SOURCE | |||||||
VS = ±15V | |||||||
1.20 20
RELATIVE SUPPLY CURRENT (ISY)
SHORT-CIRCUIT CURRENT (mA)
1.15
1.10 15
1.05
1.00 10
0.95
0.90 5
00301-036
00301-039
0.85
0.80
–75
–50
–25 0
25 50
75 100
125
0
–75
–50 –25
0 25 50
75 100 125
TEMPERATURE (°C)
Figure 37. OP482 Relative Supply Current vs. Temperature
TEMPERATURE (°C)
Figure 40. OP482 Short-Circuit Current vs. Temperature
VS = ±15V TA = 25°C | ||||||||||
POSITIVE SWING | ||||||||||
NEGATIVE SWING | ||||||||||
VS = ±15V TA = 25°C AVCL = 1 RL = 10kΩ | |||||||||||||||
16 30
ABSOLUTE OUTPUT VOLTAGE (V)
14
MAXIMUM OUTPUT SWING (V)
25
12
10 20
8 15
6
10
4
00301-037
00301-040
2 5
0
100
1k
LOAD RESISTANCE (Ω)
10k
0
1k 10k
100k 1M
FREQUENCY (Hz)
Figure 38. OP482 Maximum Output Voltage vs. Load Resistance Figure 41. OP482 Maximum Output Swing vs. Frequency
100
80
CMRR (dB)
60
40
20
0
320
280
240
UNITS
200
160
120
80
00301-043
40
VS = ±15V TA = 25°C VCM = 100mV |
–20
100 1k
10k
00301-041
100k 1M
0
0 4 8
12 16
20 24
28 32
FREQUENCY (Hz)
Figure 42. OP482 Common-Mode Rejection Ratio (CMRR) vs. Frequency
TCVOS (µV/°C)
Figure 44. OP482 TCVOS Distribution, PDIP Package
VS = ±15V TA = 25°C | ||||||||||
300 × OP482 (1200 OP AMPS) | ||||||||||
700
600
500
UNITS
400
300
200
00301-045
100
0
–2000 –1600 –1200 –800 –400 0
400
800
1200 1600 2000
VOS (µV)
Figure 43. OP482 VOS Distribution, PDIP Package
The OP282 and OP482 are dual and quad JFET op amps that are optimized for high speed at low power. This combination makes these amplifiers excellent choices for battery-powered or low power applications that require above average performance. Applications benefiting from this performance combination include telecommunications, geophysical exploration, portable
amp against phase reversal. R1, D2, and D3 limit the input current when the input exceeds the supply rail. The resistor should be selected to limit the amount of input current below the absolute maximum rating.
V+
medical equipment, and navigational instrumentation.
Many applications require the sensing of signals near the positive rail. OP282 and OP482 were tested and are guaranteed over a common-mode range (−11 V ≤ VCM ≤ +15 V) that includes the positive supply.
VIN
R1 10kΩ
D2 IN5711
D3 IN5711
D1 IN5711
OP282/ OP482
V+ V–
V–
VOUT
00301-042
One application where such sensing is commonly used is in the sensing of power supply currents. Therefore, the OP282/OP482 can be used in current sensing applications, such as the partial circuit shown in Figure 45. In this circuit, the voltage drop across a low value resistor, such as the 0.1 Ω shown here, is amplified and compared to 7.5 V. The output can then be used for current limiting.
Figure 46. Phase Reversal Solution Circuit
15V
0.1Ω
VOLTAGE (5V/DIV)
VS = ±15V | ||
VOUT | ||
VIN |
2
500kΩ
100kΩ
100kΩ RL
00301-044
1/2
OP282
500kΩ
Figure 45. High-Side Signal Conditioning
TIME (200µs/DIV)
00301-046
Figure 47. No Phase Reversal
Most JFET input amplifiers invert the phase of the input signal if either input exceeds the input common-mode range. For the OP282/OP482, a negative signal in excess of 11 V causes phase inversion. This is caused by saturation of the input stage, leading to the forward-biasing of a gate-drain diode. Phase reversal in the OP282/OP482 can be prevented by using Schottky diodes to clamp the input terminals to each other and to the supplies. In the simple buffer circuit shown in Figure 46, D1 protects the op
The wide bandwidth and high slew rates of the OP282/OP482 make either one an excellent choice for many filter applications.
There are many active filter configurations, but the four most popular configurations are Butterworth, elliptic, Bessel, and Chebyshev. Each type has a response that is optimized for a given characteristic, as shown in Table 4.
Table 4. Active Filter Configurations
Type | Selectivity | Overshoot | Phase | Amplitude (Pass Band) | Amplitude (Stop Band) |
Butterworth Chebyshev Elliptic Bessel (Thompson) | Moderate Good Best Poor | Good Moderate Poor Best | Nonlinear Linear | Maximum flat Equal ripple Equal ripple | Equal ripple |
C
The circuit shown in Figure 48 can be used to accurately program the Q, the cutoff frequency (f ), and the gain of a two- pole state variable filter. OP482 devices have been used in this design because of their high bandwidths, low power, and low noise. This circuit takes only three packages to build because of the quad configuration of the op amps and DACs.
This cutoff frequency can now be expressed as
f
1 D1
C 2πR1C1 256
where D1 is the digital code for the DAC.
The gain of this circuit is set by adjusting D3. The gain equation is
Gain R4 D3
R5 256
The DACs shown are used in the voltage mode; therefore, many
values are dependent on the accuracy of the DAC only and not on the absolute values of the DAC’s resistive ladders. This makes this circuit unusually accurate for a programmable filter.
Adjusting DAC 1 changes the signal amplitude across R1; therefore, the DAC attenuation times R1 determines the amount of signal current that charges the integrating capacitor, C1.
DAC 2 is used to set the Q of the circuit. Adjusting this DAC controls the amount of feedback from the band-pass node to the input summing node. Note that the digital value of the DAC is in the numerator; therefore, zero code is not a valid operating point.
Q R2 256
R3 D2
R7
2kΩ
VIN
1/4
DAC8408
1/4
OP482
R5
2kΩ
R4
2kΩ
1/4
OP482 R1
C1 1000pF
C1 1000pF
1/4
DAC8408
1/4
OP482
2kΩ
1/4
OP482 R1
HIGH PASS
1/4
DAC8408
1/4
OP482
2kΩ
1/4
OP482
LOW PASS
R6
2kΩ
BAND PASS
R3
2kΩ
1/4
OP482
R2
2kΩ
1/4
OP482
1/4
DAC8408
00301-047
Figure 48. Programmable State Variable Filter
3.20
3.00
2.80
3.20
3.00
2.80
5.15
8 | 5 |
1 | 4 |
4.90
4.65
PIN 1 IDENTIFIER
0.65 BSC
0.95
0.85
0.75
0.15
0.05
COPLANARITY 0.10
0.40
0.25
1.10 MAX
6°
0°
15° MAX
0.23
0.09
0.80
0.55
10-07-2009-B
0.40
COMPLIANT TO JEDEC STANDARDS MO-187-AA
Figure 49. 8-Lead Mini Small Outline Package [MSOP] (RM-8)
Dimensions shown in millimeters
5.00 (0.1968)
4.80 (0.1890)
4.00 (0.1574)
3.80 (0.1497)
8
5
6.20 (0.2441)
4
1
5.80 (0.2284)
1.27 (0.0500) 0.50 (0.0196)
45°
0.25 (0.0098)
0.10 (0.0040)
BSC
1.75 (0.0688)
1.35 (0.0532) 8°
0°
0.25 (0.0099)
COPLANARITY
0.51 (0.0201)
1.27 (0.0500)
0.10
SEATING PLANE
0.31 (0.0122)
0.25 (0.0098)
0.17 (0.0067)
0.40 (0.0157)
COMPLIANT TO JEDEC STANDARDS MS-012-AA
012407-A
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
Figure 50. 8-Lead Standard Small Outline Package [SOIC_N] Narrow Body
S-Suffix (R-8)
Dimensions shown in millimeters and (inches)
0.775 (19.69)
0.750 (19.05)
0.735 (18.67)
14 8
0.280 (7.11)
0.250 (6.35)
0.210 (5.33)
MAX
1 7
0.100 (2.54) BSC
0.240 (6.10)
0.325 (8.26)
0.310 (7.87)
0.300 (7.62)
0.060 (1.52)
MAX
0.195 (4.95)
0.130 (3.30)
0.115 (2.92)
0.150 (3.81)
0.015
(0.38) 0.015 (0.38)
0.130 (3.30) MIN
GAUGE
0.110 (2.79)
SEATING PLANE
PLANE 0.014 (0.36)
0.010 (0.25)
0.022 (0.56) 0.005 (0.13)
0.430 (10.92)
0.008 (0.20)
0.018 (0.46)
0.014 (0.36)
0.070 (1.78)
0.050 (1.27)
0.045 (1.14)
MIN
MAX
COMPLIANT TO JEDEC STANDARDS MS-001
070606-A
CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. CORNER LEADS MAY BE CONFIGURED AS WHOLE OR HALF LEADS.
Figure 51. 14-Lead Plastic Dual In-Line Package [PDIP] P-Suffix (N-14)
Dimension shown in inches and (millimeters)
8.75 (0.3445)
8.55 (0.3366)
4.00 (0.1575)
3.80 (0.1496)
6.20 (0.2441)
7
8
14
1
5.80 (0.2283)
0.25 (0.0098)
0.10 (0.0039) COPLANARITY
1.27 (0.0500) BSC
0.10 PLANE 0.25 (0.0098) | |||
0.31 (0.0122) | 0.17 (0.0067) |
0.51 (0.0201)
1.75 (0.0689)
1.35 (0.0531) SEATING
0.50 (0.0197)
0.25 (0.0098)
8°
0°
1.27 (0.0500)
0.40 (0.0157)
45°
060606-A
COMPLIANT TO JEDEC STANDARDS MS-012-AB CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
Figure 52. 14-Lead Standard Small Outline Package [SOIC_N] Narrow Body
S-Suffix (R-14)
Dimensions shown in millimeters and (inches)
1.165
1.128
1.090
0.347
BSC
3
0.347
BSC
2 1
BALL A1 IDENTIFIER
0.645
0.600
0.555
TOP VIEW
(BALL SIDE DOWN)
END VIEW
2.160
2.123
2.085
0.415
0.400
0.385
1.60
REF
0.20
BSC
0.40
BSC
0.694
REF
A B
C D E F G H J
BOTTOM VIEW (BALL SIDE UP)
SEATING PLANE
0.287
0.267
0.247
COPLANARITY 0.05
0.230
09-11-2012-B
0.200
0.170
Figure 53. 14-Ball Wafer Level Chip Scale Package [WLCSP] CB-14-2
Controlling dimensions are millimeters
Temperature Range | Package Description | Package Option | Branding | |
OP282ARMZ | −40°C to +85°C | 8-Lead MSOP | RM-8 | A0B |
OP282ARMZ-REEL | −40°C to +85°C | 8-Lead MSOP | RM-8 | A0B |
OP282GS | −40°C to +85°C | 8-Lead SOIC_N | S-Suffix (R-8) | |
OP282GS-REEL | −40°C to +85°C | 8-Lead SOIC_N | S-Suffix (R-8) | |
OP282GS-REEL7 | −40°C to +85°C | 8-Lead SOIC_N | S-Suffix (R-8) | |
OP282GSZ | −40°C to +85°C | 8-Lead SOIC_N | S-Suffix (R-8) | |
OP282GSZ-REEL | −40°C to +85°C | 8-Lead SOIC_N | S-Suffix (R-8) | |
OP282GSZ-REEL7 | −40°C to +85°C | 8-Lead SOIC_N | S-Suffix (R-8) | |
OP482ACBZ-RL | −40°C to +85°C | 14-Ball WLCSP | CB-14-2 | A2J |
OP482ACBZ-R7 | −40°C to +85°C | 14-Ball WLCSP | CB-14-2 | A2J |
OP482GPZ | −40°C to +85°C | 14-Lead PDIP | P-Suffix (N-14) | |
OP482GS | −40°C to +85°C | 14-Lead SOIC_N | S-Suffix (R-14) | |
OP482GS-REEL | −40°C to +85°C | 14-Lead SOIC_N | S-Suffix (R-14) | |
OP482GS-REEL7 | −40°C to +85°C | 14-Lead SOIC_N | S-Suffix (R-14) | |
OP482GSZ | −40°C to +85°C | 14-Lead SOIC_N | S-Suffix (R-14) | |
OP482GSZ-REEL | −40°C to +85°C | 14-Lead SOIC_N | S-Suffix (R-14) | |
OP482GSZ-REEL7 | −40°C to +85°C | 14-Lead SOIC_N | S-Suffix (R-14) |
1 Z = RoHS Compliant Part.
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OP282ARMZ-REEL OP482GSZ-REEL7 OP482GS-REEL7 OP482ACBZ-R7 OP282GSZ-REEL OP282GSZ-REEL7 OP282GS-REEL7 OP482GPZ OP282GS-REEL OP282ARMZ OP482GSZ-REEL OP282GS OP282GSZ