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  1. Features

    LM158, LM158A, LM258, LM258A LM358, LM358A, LM358B, LM358BA, LM2904, LM2904B, LM2904BA, LM2904V

    SLOS068W – JUNE 1976 – REVISED OCTOBER 2019

    Industry-Standard Dual Operational Amplifiers

    3 Description

  2. Applications

    1. Trademarks 29

    2. Electrostatic Discharge Caution 29

    3. Glossary 29

  1. Mechanical, Packaging, and Orderable Information 30


  1. Revision History

    NOTE: Page numbers for previous revisions may differ from page numbers in the current version.


    Changes from Revision V (September 2018) to Revision W Page


  2. Device Comparison Table


    PART NUMBER

    SUPPLY VOLTAGE

    TEMPERATURE RANGE

    VOS (MAXIMUM AT 25°C)

    IQ / CH (TYPICAL AT 25°C)

    INTEGRATED EMI FILTER

    PACKAGE

    LM358B

    3 V–36 V

    –40°C to 85°C

    3 mV

    300 µA

    Yes

    D, DGK, PW

    LM2904B

    3 V–36 V

    –40°C to 125°C

    3 mV

    300 µA

    Yes

    D, DGK, PW

    LM358

    3 V–32 V

    0°C to 70°C

    7 mV

    350 µA

    No

    D, PW, DGK, P, PS

    LM2904

    3 V–26 V

    –40°C to 125°C

    7 mV

    350 µA

    No

    D, PW, DGK, P, PS

    LM358A

    3 V–32 V

    0°C to 70°C

    3 mV

    350 µA

    No

    D, PW, DGK, P

    LM2904V

    3 V–32 V

    –40°C to 125°C

    7 mV

    350 µA

    No

    D, PW

    LM158

    3 V–32 V

    –55°C to 125°C

    5 mV

    350 µA

    No

    JG, FK

    LM158A

    3 V–32 V

    –55°C to 125°C

    3 mV

    350 µA

    No

    JG, FK

    LM258

    3 V–32 V

    –25°C to 85°C

    5 mV

    350 µA

    No

    D, DGK, P

    LM258A

    3 V–32 V

    –25°C to 85°C

    3 mV

    350 µA

    No

    D, DGK, P

  3. Pin Configuration and Functions


    D, DGK, P, PS, PW, and JG Packages

    8-Pin SOIC, VSSOP, PDIP, SO, TSSOP, and CDIP

    Top View


    FK Package 20-Pin LCCC

    Top View



    NC

    OUT1

    NC

    V+

    NC

    OUT1 1 8 V+


    3

    2

    1

    20

    19

    IN1- 2

  4. OUT2

IN1+ 3

V- 4

6 IN2-

5 IN2+

NC 4

IN1- 5

18 NC

17 OUT2

Not to scale

NC 6

IN1+ 7

16 NC

15 IN2-

9

10

11

12

13

NC 8 14 NC

NC

V-

NC

IN2+

NC

Not to scale


Pin Functions


NC - No internal connection


PIN

I/O

DESCRIPTION

NAME

LCCC (1)

SOIC, SSOP, CDIP, PDIP, SO, TSSOP, CFP(1)



IN1–

5

2

I

Negative input

IN1+

7

3

I

Positive input

IN2–

15

6

I

Negative input

IN2+

12

5

I

Positive input

OUT1

2

1

O

Output

OUT2

17

7

O

Output

V–

10

4

Negative (lowest) supply or ground (for single- supply operation)

NC

1, 3, 4, 6, 8, 9, 11,

13, 14, 16, 18, 19

No internal connection

V+

20

8

Positive (highest) supply

(1) For a listing of which devices are available in what packages, see Device Comparison Table.

  1. Specifications

    1. Absolute Maximum Ratings

      over operating ambient temperature range (unless otherwise noted)(1)



      MIN


      MAX

      UNIT


      Supply voltage, VS = ([V+] – [V–])

      LM358B, LM358BA, LM2904B, LM2904BA

      ±20 or 40


      V

      LM158, LM258, LM358, LM158A, LM258A, LM358A, LM2904V


      ±16 or 32

      LM2904

      ±13 or 26


      Differential input voltage, VID(2)

      LM358B, LM358BA, LM2904B, LM2904BA,LM158, LM258, LM358, LM158A, LM258A, LM358A, LM2904V


      –32



      32


      V

      LM2904

      –26


      26


      Input voltage, VI


      Either input

      LM358B, LM358BA, LM2904B, LM2904BA

      –0.3


      40


      V

      LM158, LM258, LM358, LM158A, LM258A, LM358A, LM2904V


      –0.3



      32

      LM2904

      –0.3


      26

      Duration of output short circuit (one amplifier) to ground at (or below) TA = 25°C, VS ≤ 15 V(3)

      Unlimited

      s


      Operating ambient temperature, TA

      LM158, LM158A

      –55


      125


      °C

      LM258, LM258A

      –25


      85

      LM358B, LM358BA

      –40


      85

      LM358, LM358A

      0


      70

      LM2904B, LM2904BA, LM2904, LM2904V

      –40


      125

      Operating virtual-junction temperature, TJ

      150

      °C

      Storage temperature, Tstg

      –65


      150

      °C

      1. Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

      2. Differential voltages are at IN+, with respect to IN−.

      3. Short circuits from outputs to VS can cause excessive heating and eventual destruction.


    2. ESD Ratings


      VALUE

      UNIT

      LM358B, LM358BA, LM2904B, AND LM2904BA

      V(ESD) Electrostatic discharge

      Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)

      ±2000


      V

      Charged-device model (CDM), per JEDEC specification JESD22-C101(2)

      ±1000

      LM158, LM258, LM358, LM158, LM258A, LM358A, LM2904, AND LM2904V

      V(ESD) Electrostatic discharge

      Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)

      ±500


      V

      Charged-device model (CDM), per JEDEC specification JESD22-C101(2)

      ±1000

      1. JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

      2. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

    3. Recommended Operating Conditions

      over operating ambient temperature range (unless otherwise noted)


      MIN

      MAX

      UNIT


      VS


      Supply voltage, VS= ([V+] – [V–])

      LM358B, LM358BA, LM2904B, LM2904BA

      3

      36


      V

      LM158, LM258, LM358, LM158A, LM258A, LM358A, LM2904V

      3

      30

      LM2904

      3

      26

      VCM

      Common-mode voltage


      V–

      V+ – 2

      V


      TA


      Operating ambient temperature

      LM358B, LM358BA

      –40

      85


      °C

      LM2904B, LM2904BA, LM2904, LM2904V

      –40

      125

      LM358, LM358A

      0

      70

      LM258, LM258A

      –20

      85

      LM158, LM158A

      –55

      125


    4. Thermal Information


      THERMAL METRIC(1)

      LM258, LM258A, LM358, LM358A, LM358B, LM358BA, LM2904, LM2904B, LM2904BA, LM2904V (2)

      LM158, LM158A


      UNIT

      D (SOIC)

      DGK (VSSOP)

      P (PDIP)

      PS (SO)

      PW (TSSOP)

      FK (LCCC)

      JG (CDIP)

      8 PINS

      8 PINS

      8 PINS

      8 PINS

      8 PINS

      20 PINS

      8 PINS

      RθJA

      Junction-to-ambient thermal resistance

      124.7

      181.4

      80.9

      116.9

      171.7

      84.0

      112.4

      °C/W

      RθJC(top)

      Junction-to-case (top) thermal resistance

      66.9

      69.4

      70.4

      62.5

      68.8

      56.9

      63.6

      °C/W

      RθJB

      Junction-to-board thermal resistance

      67.9

      102.9

      57.4

      68.6

      99.2

      57.5

      100.3

      °C/W

      ψJT

      Junction-to-top characterization parameter

      19.2

      11.8

      40

      21.9

      11.5

      51.7

      35.7

      °C/W

      ψJB

      Junction-to-board characterization parameter

      67.2

      101.2

      56.9

      67.6

      97.9

      57.1

      93.3

      °C/W

      RθJC(bot)

      Junction-to-case (bottom) thermal resistance

      10.6

      22.3

      °C/W

      1. For more information about traditional and new thermal metrics, see Semiconductor and IC Package Thermal Metrics.

      2. For a listing of which devices are available in what packages, see Device Comparison Table.

    5. Electrical Characteristics: LM358B and LM358BA

      VS = (V+) – (V–) = 5 V - 36 V (±2.5 V - ±18 V), TA = 25°C, VCM = VOUT = VS/2, RL = 10k connected to VS/2

      (unless otherwise noted)

      PARAMETER

      TEST CONDITIONS

      MIN

      TYP

      MAX

      UNIT

      OFFSET VOLTAGE


      VOS


      Input offset voltage


      LM358B



      ±0.3

      ±3.0

      mV

      TA = –40°C to +85°C

      ±4

      mV


      LM358BA


      ±2.0

      mV

      TA = –40°C to +85°C

      ±2.5

      mV

      dVOS/dT

      Input offset voltage drift


      TA = -40°C to +85°C(1)


      ±3.5

      11

      µV/°C

      PSRR

      Power Supply Rejection Ratio



      ±2

      15

      µV/V


      Channel separation, dc

      f = 1 kHz to 20 kHz

      ±1

      µV/V

      INPUT VOLTAGE RANGE


      VCM


      Common-mode voltage range

      VS = 3 V to 36 V


      (V–)


      (V+) – 1.5

      V

      VS = 5 V to 36 V

      TA = –40°C to +85°C

      (V–)


      (V+) – 2

      V


      CMRR


      Common-mode rejection ratio

      (V–) ≤ VCM ≤ (V+) – 1.5 V

      VS = 3 V to 36 V



      20

      100


      µV/V

      (V–) ≤ VCM ≤ (V+) – 2.0 V

      VS = 5 V to 36 V

      TA = –40°C to +85°C


      25

      316

      INPUT BIAS CURRENT


      IB


      Input bias current




      ±10

      ±35

      nA

      TA = –40°C to +85°C(1)

      ±50

      nA


      IOS


      Input offset current



      0.5 4

      nA

      TA = –40°C to +85°C(1)

      5

      nA

      dIOS/dT

      Input offset current drift


      TA = –40°C to +85°C

      10

      pA/

      NOISE

      En

      Input voltage noise

      f = 0.1 to 10 Hz

      3

      µVPP

      en

      Input voltage noise density

      f = 1 kHz

      40

      nV/√/Hz

      INPUT IMPEDANCE

      ZID

      Differential


      10 || 0.1

      MΩ|| pF

      ZIC

      Common-mode


      4 || 1.5

      GΩ|| pF

      OPEN-LOOP GAIN


      AOL


      Open-loop voltage gain


      VS = 15 V; VO = 1 V to 11 V; RL ≥ 10 kΩ, connected to (V-)


      70

      140


      V/mV

      TA = –40°C to +85°C

      35

      V/mV

      FREQUENCY RESPONSE

      GBW

      Gain bandwidth product


      1.2

      MHz

      SR

      Slew rate

      G = + 1

      0.5

      V/µs

      Θm

      Phase margin

      G = + 1, RL = 10kΩ, CL = 20 pF

      56

      °

      tOR

      Overload recovery time

      VIN × gain > VS

      10

      µs

      ts

      Settling time

      To 0.1%, VS = 5 V, 2-V Step , G = +1, CL = 100 pF

      4

      µs

      THD+N

      Total harmonic distortion + noise

      G = + 1, f = 1 kHz, VO = 3.53 VRMS, VS = 36V, RL = 100k, IOUT ≤ ±50µA, BW = 80 kHz

      0.001

      %

      OUTPUT


      VO


      Voltage output swing from rail


      Positive Rail (V+)

      IOUT = 50 µA


      1.35

      1.42

      V

      IOUT = 1 mA


      1.4

      1.48

      V

      IOUT = 5 mA(1)


      1.5

      1.61

      V


      Negative Rail (V-)


      IOUT = 50 µA


      100

      150

      mV


      IOUT = 1 mA

      0.75 1

      V

      VS = 5 V, RL ≤ 10 kΩ connected to (V–)

      TA = –40°C to +85°C


      5

      20

      mV


      IO


      Output current

      VS = 15 V; VO = V-; VID = 1 V


      Source(1)


      -20

      -30



      mA

      TA = –40°C to +85°C

      -10

      VS = 15 V; VO = V+; VID = -1 V


      Sink(1)


      10

      20


      TA = –40°C to +85°C

      5

      VID = -1 V; VO = (V-) + 200 mV

      60

      100


      μA

      ISC

      Short-circuit current

      VS = 20 V, (V+) = 10 V, (V-) = -10 V, VO = 0 V


      ±40

      ±60

      mA

      CLOAD

      Capacitive load drive


      100

      pF

      RO

      Open-loop output resistance

      f = 1 MHz, IO = 0 A

      300

      Ω

      POWER SUPPLY

      IQ

      Quiescent current per amplifier

      VS = 5 V; IO = 0 A


      TA = –40°C to +85°C


      300

      460

      µA

      IQ

      Quiescent current per amplifier

      VS = 36 V; IO = 0 A

      800

      µA

      (1) Specified by characterization only

    6. Electrical Characteristics: LM2904B and LM2904B

      VS = (V+) – (V–) = 5 V - 36 V (±2.5 V - ±18 V), TA = 25°C, VCM = VOUT = VS/2, RL = 10k connected to VS/2

      (unless otherwise noted)

      PARAMETER

      TEST CONDITIONS

      MIN

      TYP

      MAX

      UNIT

      OFFSET VOLTAGE


      VOS


      Input offset voltage


      LM2904B



      ±0.3

      ±3.0

      mV

      TA = –40°C to +125°C

      ±4

      mV


      LM2904BA


      ±2.0

      mV

      TA = –40°C to +125°C

      ±2.5

      mV

      dVOS/dT

      Input offset voltage drift


      TA = –40°C to +125°C(1)


      ±3.5

      12

      µV/°C

      PSRR

      Power Supply Rejection Ratio



      ±2

      15

      µV/V


      Channel separation, dc

      f = 1 kHz to 20 kHz

      ±1

      µV/V

      INPUT VOLTAGE RANGE


      VCM


      Common-mode voltage range

      VS = 3 V to 36 V


      (V–)


      (V+) – 1.5

      V

      VS = 5 V to 36 V

      TA = –40°C to +125°C

      (V–)


      (V+) – 2

      V


      CMRR


      Common-mode rejection ratio

      (V–) ≤ VCM ≤ (V+) – 1.5 V

      VS = 3 V to 36 V



      20

      100


      µV/V

      (V–) ≤ VCM ≤ (V+) – 2.0 V

      VS = 5 V to 36 V

      TA = –40°C to +125°C


      25

      316

      INPUT BIAS CURRENT


      IB


      Input bias current




      ±10

      ±35

      nA

      TA = –40°C to +125°C(1)

      ±50

      nA


      IOS


      Input offset current



      0.5 4

      nA

      TA = –40°C to +125°C(1)

      5

      nA

      dIOS/dT

      Input offset current drift


      TA = –40°C to +125°C

      10

      pA/

      NOISE

      En

      Input voltage noise

      f = 0.1 to 10 Hz

      3

      µVPP

      en

      Input voltage noise density

      f = 1 kHz

      40

      nV/√/Hz

      INPUT IMPEDANCE

      ZID

      Differential


      10 || 0.1

      MΩ|| pF

      ZIC

      Common-mode


      4 || 1.5

      GΩ|| pF

      OPEN-LOOP GAIN


      AOL


      Open-loop voltage gain


      VS = 15 V; VO = 1 V to 11 V; RL ≥ 10 kΩ, connected to (V-)


      70

      140


      V/mV

      TA = –40°C to +125°C

      35

      V/mV

      FREQUENCY RESPONSE

      GBW

      Gain bandwidth product


      1.2

      MHz

      SR

      Slew rate

      G = + 1

      0.5

      V/µs

      Θm

      Phase margin

      G = + 1, RL = 10kΩ, CL = 20 pF

      56

      °

      tOR

      Overload recovery time

      VIN × gain > VS

      10

      µs

      ts

      Settling time

      To 0.1%, VS = 5 V, 2-V Step , G = +1, CL = 100 pF

      4

      µs

      THD+N

      Total harmonic distortion + noise

      G = + 1, f = 1 kHz, VO = 3.53 VRMS, VS = 36V, RL = 100k, IOUT ≤ ±50µA, BW = 80 kHz

      0.001

      %

      OUTPUT


      VO


      Voltage output swing from rail


      Positive Rail (V+)

      IOUT = 50 µA


      1.35

      1.42

      V

      IOUT = 1 mA


      1.4

      1.48

      V

      IOUT = 5 mA(1)


      1.5

      1.61

      V


      Negative Rail (V-)


      IOUT = 50 µA


      100

      150

      mV


      IOUT = 1 mA

      0.75 1

      V

      VS = 5 V, RL ≤ 10 kΩ connected to (V–)

      TA = –40°C to +125°C


      5

      20

      mV


      IO


      Output current

      VS = 15 V; VO = V-; VID = 1 V


      Source(1)


      -20

      -30



      mA

      TA = –40°C to +125°C

      -10

      VS = 15 V; VO = V+; VID

      = -1 V


      Sink(1)


      10

      20


      TA = –40°C to +125°C

      5

      VID = -1 V; VO = (V-) + 200 mV

      60

      100


      μA

      ISC

      Short-circuit current

      VS = 20 V, (V+) = 10 V, (V-) = -10 V, VO = 0 V


      ±40

      ±60

      mA

      CLOAD

      Capacitive load drive


      100

      pF

      RO

      Open-loop output resistance

      f = 1 MHz, IO = 0 A

      300

      Ω

      POWER SUPPLY

      IQ

      Quiescent current per amplifier

      VS = 5 V; IO = 0 A


      TA = –40°C to +125°C


      300

      460

      µA

      IQ

      Quiescent current per amplifier

      VS = 36 V; IO = 0 A

      800

      µA

      (1) Specified by characterization only

    7. Electrical Characteristics: LM358, LM358A

      For VS = (V+) – (V–) = 5 V, TA = 25 °C, (unless otherwise noted)

      PARAMETER

      TEST CONDITIONS(1)

      MIN

      TYP(2)

      MAX

      UNIT

      OFFSET VOLTAGE


      VOS


      Input offset voltage


      VS = 5 V to 30 V; VCM = 0 V; VO = 1.4 V


      LM358



      3

      7


      mV

      TA = 0°C to 70°C

      9

      LM358A



      2

      3

      TA = 0°C to 70°C

      5


      dVOS/dT


      Input offset voltage drift


      LM358

      TA = 0°C to 70°C

      7


      µV/°C

      LM358A

      TA = 0°C to 70°C


      7

      20

      PSRR

      Input offset voltage vs power supply (ΔVIO/ΔVS)

      VS = 5 V to 30 V

      65

      100


      dB

      VO1/ VO2

      Channel separation

      f = 1 kHz to 20 kHz

      120

      dB

      INPUT VOLTAGE RANGE


      VCM


      Common-mode voltage range

      VS = 5 V to 30 V

      LM358


      (V–)



      (V+) – 1.5


      V

      VS = 30 V

      LM358A

      VS = 5 V to 30 V

      LM358


      TA = 0°C to 70°C


      (V–)



      (V+) – 2

      VS = 30 V

      LM358A

      CMRR

      Common-mode rejection ratio

      VS = 5 V to 30 V; VCM = 0 V

      65

      80


      dB

      INPUT BIAS CURRENT


      IB


      Input bias current


      VO = 1.4 V


      LM358



      –20

      –250


      nA

      TA = 0°C to 70°C

      –500


      LM358A



      –15

      –100

      TA = 0°C to 70°C

      –200


      IOS


      Input offset current


      VO = 1.4 V


      LM358



      2

      50


      nA

      TA = 0°C to 70°C

      150


      LM358A



      2

      30

      TA = 0°C to 70°C

      75


      dIOS/dT


      Input offset current drift




      10


      pA/°C

      LM358A

      TA = 0°C to 70°C

      300

      NOISE

      en

      Input voltage noise density

      f = 1 kHz

      40

      nV/√Hz

      OPEN-LOOP GAIN


      AOL


      Open-loop voltage gain


      VS = 15 V; VO = 1 V to 11 V; RL ≥ 2 kΩ


      25

      100



      V/mV

      TA = 0°C to 70°C

      15

      FREQUENCY RESPONSE

      GBW

      Gain bandwidth product


      0.7

      MHz

      SR

      Slew rate

      G = +1

      0.3

      V/µs

      OUTPUT


      VO


      Voltage output swing from rail


      Positive rail

      VS = 30 V; RL = 2 kΩ

      TA = 0°C to 70°C

      4


      V

      VS = 30 V; RL ≥ 10 kΩ


      2

      3

      VS = 5 V; RL ≥ 2 kΩ

      1.5

      Negative rail

      VS = 5 V; RL ≤ 10 kΩ

      TA = 0°C to 70°C


      5

      20

      mV


      IO


      Output current


      VS = 15 V; VO = 0 V; VID

      = 1 V


      Source


      –20

      –30



      mA

      LM358A

      –60


      TA = 0°C to 70°C

      –10

      VS = 15 V; VO = 15 V; VID = –1 V


      Sink


      10

      20



      TA = 0°C to 70°C

      5

      VID = –1 V; VO = 200 mV

      12

      30


      µA

      ISC

      Short-circuit current

      VS = 10 V; VO = VS / 2


      ±40

      ±60

      mA

      POWER SUPPLY


      IQ

      Quiescent current per amplifier

      VO = 2.5 V; IO = 0 A


      TA = 0°C to 70°C


      350

      600


      µA

      VS = 30 V; VO = 15 V; IO = 0 A


      500

      1000

      1. All characteristics are measured under open-loop conditions, with zero common-mode input voltage, unless otherwise specified. Maximum VS for testing purposes is 30 V for LM358 and LM358A.

      2. All typical values are TA = 25°C.

    8. Electrical Characteristics: LM2904, LM2904V

      For VS = (V+) – (V–) = 5 V, TA = 25 °C, (unless otherwise noted)

      PARAMETER

      TEST CONDITIONS(1)

      MIN

      TYP (2)

      MAX

      UNIT

      OFFSET VOLTAGE


      VOS


      Input offset voltage


      VS = 5 V to maximum; VCM = 0 V; VO = 1.4 V

      Non-A suffix devices



      3

      7


      mV

      TA = –40°C to 125°C

      10

      A-suffix devices



      1

      2

      TA = –40°C to 125°C

      4

      dVOS/dT

      Input offset voltage drift


      TA = –40°C to 125°C

      7

      µV/°C

      PSRR

      Input offset voltage vs power supply (ΔVIO/ΔVS)

      VS = 5 V to 30 V

      65

      100


      dB

      VO1/ VO2 Channel separation

      f = 1 kHz to 20 kHz

      120

      dB

      INPUT VOLTAGE RANGE


      VCM


      Common-mode voltage range


      VS = 5 V to maximum


      (V–)


      (V+) – 1.5


      V

      TA = –40°C to 125°C

      (V–)


      (V+) – 2

      CMRR

      Common-mode rejection ratio

      VS = 5 V to maximum; VCM = 0 V

      65

      80


      dB

      INPUT BIAS CURRENT


      IB


      Input bias current


      VO = 1.4 V



      –20

      –250


      nA

      TA = –40°C to 125°C

      –500


      IOS


      Input offset current


      VO = 1.4 V

      Non-V suffix device



      2

      50


      nA

      TA = –40°C to 125°C

      300

      V-suffix device



      2

      50

      TA = –40°C to 125°C

      150

      dIOS/dT

      Input offset current drift


      TA = –40°C to 125°C

      10

      pA/°C

      NOISE

      en

      Input voltage noise density

      f = 1 kHz

      40

      nV/√Hz

      OPEN-LOOP GAIN


      AOL


      Open-loop voltage gain


      VS = 15 V; VO = 1 V to 11 V; RL ≥ 2 kΩ


      25

      100



      V/mV

      TA = –40°C to 125°C

      15

      FREQUENCY RESPONSE

      GBW

      Gain bandwidth product


      0.7

      MHz

      SR

      Slew rate

      G = +1

      0.3

      V/µs

      OUTPUT


      VO


      Voltage output swing from rail


      Positive rail

      RL ≥ 10 kΩ

      VS – 1.5


      V


      Non-V suffix device

      VS = maximum; RL = 2 kΩ


      TA = –40°C to 125°C

      4

      VS = maximum; RL ≥

      10 kΩ


      2

      3


      V-suffix device

      VS = maximum; RL = 2 kΩ

      6

      VS = maximum; RL ≥

      10 kΩ


      4

      5

      Negative rail

      VS = 5 V; RL ≤ 10 kΩ

      TA = –40°C to 125°C


      5

      20

      mV


      IO


      Output current


      VS = 15 V; VO = 0 V; VID = 1 V


      Source


      –20

      –30



      mA

      TA = –40°C to 125°C

      –10


      VS = 15 V; VO = 15 V; VID = –1 V


      Sink


      10

      20


      TA = –40°C to 125°C

      5


      VID = -1 V; VO = 200 mV

      Non-V suffix device

      30


      µA

      V-suffix device

      12

      40


      ISC

      Short-circuit current

      VS = 10 V; VO = VS / 2


      ±40

      ±60

      mA

      POWER SUPPLY


      IQ


      Quiescent current per amplifier

      VO = 2.5 V; IO = 0 A


      TA = –40°C to 125°C


      350

      600


      µA

      VS = maximum; VO = maximum / 2; IO = 0 A


      500

      1000

      1. All characteristics are measured under open-loop conditions, with zero common-mode input voltage, unless otherwise specified. Maximum VS for testing purposes is 26 V for LM2904 and 32 V for LM2904V.

      2. All typical values are TA = 25°C.

    9. Electrical Characteristics: LM158, LM158A

      For VS = (V+) – (V–) = 5 V, TA = 25 °C, (unless otherwise noted)

      PARAMETER

      TEST CONDITIONS(1)

      MIN

      TYP(2)

      MAX

      UNIT

      OFFSET VOLTAGE


      VOS


      Input offset voltage


      VS = 5 V to 30 V; VCM = 0 V; VO = 1.4 V


      LM158



      3

      5


      mV

      TA = –55°C to 125°C

      7


      LM158A


      2

      TA = –55°C to 125°C

      4


      dVOS/dT Input offset voltage drift


      LM158

      TA = –55°C to 125°C

      7


      µV/°C

      LM158A

      TA = –55°C to 125°C


      7

      15(3)

      PSRR

      Input offset voltage vs power supply (ΔVIO/ΔVS)

      VS = 5 V to 30 V

      65

      100


      dB

      VO1/ VO2 Channel separation

      f = 1 kHz to 20 kHz

      120

      dB

      INPUT VOLTAGE RANGE


      VCM


      Common-mode voltage range

      VS = 5 V to 30 V

      LM158


      (V–)



      (V+) – 1.5


      V

      VS = 30 V

      LM158A

      VS = 5 V to 30 V

      LM158


      TA = –55°C to 125°C


      (V–)



      (V+) – 2

      VS = 30 V

      LM158A

      CMRR

      Common-mode rejection ratio

      VS = 5 V to 30 V; VCM = 0 V

      70

      80


      dB

      INPUT BIAS CURRENT


      IB


      Input bias current


      VO = 1.4 V


      LM158



      –20

      –150


      nA

      TA = –55°C to 125°C

      –300


      LM158A



      –15

      –50

      TA = –55°C to 125°C

      –100


      IOS


      Input offset current


      VO = 1.4 V


      LM158



      2

      30


      nA

      TA = –55°C to 125°C

      100


      LM158A



      2

      10

      TA = –55°C to 125°C

      30


      dIOS/dT


      Input offset current drift



      10


      pA/°C

      LM158A

      TA = –55°C to 125°C

      200

      NOISE

      en

      Input voltage noise density

      f = 1 kHz

      40

      nV/√Hz

      OPEN-LOOP GAIN


      AOL


      Open-loop voltage gain


      VS = 15 V; VO = 1 V to 11 V; RL ≥ 2 kΩ


      50

      100



      V/mV

      TA = –55°C to 125°C

      25

      FREQUENCY RESPONSE

      GBW

      Gain bandwidth product


      0.7

      MHz

      SR

      Slew rate

      G = +1

      0.3

      V/µs

      OUTPUT


      VO


      Voltage output swing from rail


      Positive rail

      VS = 30 V; RL = 2 kΩ

      TA = –55°C to 125°C

      4


      V

      VS = 30 V; RL ≥ 10 kΩ


      2

      3

      VS = 5 V; RL ≥ 2 kΩ

      1.5

      Negative rail

      VS = 5 V; RL ≤ 10 kΩ

      TA = –55°C to 125°C


      5

      20

      mV


      IO


      Output current


      VS = 15 V; VO = 0 V; VID = 1 V


      Source


      –20

      –30



      mA

      LM158A

      –60


      TA = –55°C to 125°C

      –10

      VS = 15 V; VO = 15 V; VID = –1 V


      Sink


      10

      20


      TA = –55°C to 125°C

      5

      VID = –1 V; VO = 200 mV

      12

      30


      µA

      ISC

      Short-circuit current

      VS = 10 V; VO = VS / 2


      ±40

      ±60

      mA

      POWER SUPPLY


      IQ


      Quiescent current per amplifier

      VO = 2.5 V; IO = 0 A


      TA = –55°C to 125°C


      350

      600


      µA

      VS = 30 V; VO = 15 V; IO = 0 A


      500

      1000

      1. All characteristics are measured under open-loop conditions, with zero common-mode input voltage, unless otherwise specified. Maximum VS for testing purposes is 30 V for LM158 and LM158A.

      2. All typical values are TA = 25°C.

      3. On products compliant to MIL-PRF-38535, this parameter is not production tested.

    10. Electrical Characteristics: LM258, LM258A

      For VS = (V+) – (V–) = 5 V, TA = 25 °C, (unless otherwise noted)

      PARAMETER

      TEST CONDITIONS(1)

      MIN

      TYP(2)

      MAX

      UNIT

      OFFSET VOLTAGE


      VOS


      Input offset voltage


      VS = 5 V to 30 V; VCM = 0 V; VO = 1.4 V


      LM258



      3

      5


      mV

      TA = –25°C to 85°C

      7


      LM258A



      2

      3

      TA = –25°C to 85°C

      4


      dVOS/dT Input offset voltage drift


      LM258


      TA = –25°C to 85°C

      7


      µV/°C

      LM258A


      7

      15

      PSRR

      Input offset voltage vs power supply (ΔVIO/ΔVS)

      VS = 5 V to 30 V

      65

      100


      dB

      VO1/ VO2 Channel separation

      f = 1 kHz to 20 kHz

      120

      dB

      INPUT VOLTAGE RANGE


      VCM


      Common-mode voltage range

      VS = 5 V to 30 V

      LM258


      (V–)



      (V+) – 1.5


      V

      VS = 30 V

      LM258A

      VS = 5 V to 30 V

      LM258


      TA = –25°C to 85°C


      (V–)



      (V+) – 2

      VS = 30 V

      LM258A

      CMRR

      Common-mode rejection ratio

      VS = 5 V to 30 V; VCM = 0 V

      70

      80


      dB

      INPUT BIAS CURRENT


      IB


      Input bias current


      VO = 1.4 V


      LM258



      –20

      –150


      nA

      TA = –25°C to 85°C

      –300


      LM258A



      –15

      –80

      TA = –25°C to 85°C

      –100


      IOS


      Input offset current


      VO = 1.4 V


      LM258



      2

      30


      nA

      TA = –25°C to 85°C

      100


      LM258A



      2

      15

      TA = –25°C to 85°C

      30


      dIOS/dT


      Input offset current drift



      10


      pA/°C

      LM258A

      TA = –25°C to 85°C

      200

      NOISE

      en

      Input voltage noise density

      f = 1 kHz

      40

      nV/√Hz

      OPEN-LOOP GAIN


      AOL


      Open-loop voltage gain


      VS = 15 V; VO = 1 V to 11 V; RL ≥ 2 kΩ


      50

      100



      V/mV

      TA = –25°C to 85°C

      25

      FREQUENCY RESPONSE

      GBW

      Gain bandwidth product


      0.7

      MHz

      SR

      Slew rate

      G = +1

      0.3

      V/µs

      OUTPUT


      VO


      Voltage output swing from rail


      Positive rail

      VS = 30 V; RL = 2 kΩ

      TA = –25°C to 85°C

      4


      V

      VS = 30 V; RL ≥ 10 kΩ


      2

      3

      VS = 5 V; RL ≥ 2 kΩ

      1.5

      Negative rail

      VS = 5 V; RL ≤ 10 kΩ

      TA = –25°C to 85°C


      5

      20

      mV


      IO


      Output current


      VS = 15 V; VO = 0 V; VID = 1 V


      Source


      –20

      –30



      mA

      LM258A

      –60


      TA = –25°C to 85°C

      –10

      VS = 15 V; VO = 15 V; VID = –1 V


      Sink


      10

      20


      TA = –25°C to 85°C

      5

      VID = –1 V; VO = 200 mV

      12

      30


      µA

      ISC

      Short-circuit current

      VS = 10 V; VO = VS / 2


      ±40

      ±60

      mA

      POWER SUPPLY


      IQ


      Quiescent current per amplifier

      VO = 2.5 V; IO = 0 A


      TA = –25°C to 85°C


      350

      600


      µA

      VS = 30 V; VO = 15 V; IO = 0 A


      500

      1000

      1. All characteristics are measured under open-loop conditions, with zero common-mode input voltage, unless otherwise specified. Maximum VS for testing purposes is 30 V for LM258 and LM258A.

      2. All typical values are TA = 25°C.

    11. Typical Characteristics

      Typical characteristics section is applicable for LM358B and LM2904B. The typical characteristics data section was taken with TA = 25°C, VS = 36 V (±18 V), VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2 (unless otherwise noted).


      20

      18

      16

      Amplifiers (%)

      14

      12

      10

      8

      6

      4

      2

      0

      -1800 -1200 -600 0 600 1200 1800

      30

      27

      24

      Amplifiers (%)

      21

      18

      15

      12

      9

      6

      3

      0

      0 0.25 0.5 0.75 1 1.25 1.5 1.75 2 2.25 2.5 2.75

      Offset Voltage (µV)

      DC11 Offset Voltage Drift (µV/°C)

      DC12


      Figure 1. Offset Voltage Production Distribution Figure 2. Offset Voltage Drift Distribution

      750 500


      450 300


      Offset Voltage (µV)

      Offset Voltage (µV)

      150 100


      -150 -100


      -450 -300


      -750

      -40 -20 0 20 40 60 80 100 120

      -500

      -18 -12 -6 0 6 12 17

      Temperature (°C)

      DC10 Common-Mode Voltage (V)


      DC10


      Figure 3. Offset Voltage vs Temperature Figure 4. Offset Voltage vs Common-Mode Voltage

      Open Loop Voltage Gain (dB)


      80










      90

      70









      80

      60









      70

      50









      60

      40









      50

      30









      40

      20









      30

      90 100


      Phase ()

      10 20

      0 10

      70

      G = 1

      G = 10

      G = 100

      Closed Lopp Voltage Gain (dB)

      60

      G = 1000

      50

      G = –1

      40

      30

      20

      10

      0

      -10

      -10 Gain (dB)

      Phase (°)

      0 -20

      -20 -10

      1k 10k 100k 1M

      -30


      1k 10k 100k 1M

      Frequency (Hz)

      D012

      Frequency (Hz)

      D017


      Figure 5. Open-Loop Gain and Phase vs Frequency Figure 6. Closed-Loop Gain vs Frequency

      Typical Characteristics (continued)

      Typical characteristics section is applicable for LM358B and LM2904B. The typical characteristics data section was taken with TA = 25°C, VS = 36 V (±18 V), VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2 (unless otherwise noted).

      IB+ IB–

      -5


      Input Bias Current (nA)

      -7.5


      -10


      -12.5


      -15

      -20 -15 -10 -5 0 5 10 15 20

      120


































































      100


      Input Offset Current (pA)

      80


      60


      40


      20


      0


      -20


      -40

      -20 -15 -10 -5 0 5 10 15 20

      Common-Mode Voltage (V)

      DC3I

      Common-Mode Voltage (V)

      DC3I



      -6


      Input Bias Current (nA)

      -7


      -8


      -9


      -10


      -11

      Figure 7. Input Bias Current vs Common-Mode Voltage Figure 8. Input Offset Current vs Common-Mode Voltage

























      IB+ IB

















































      0.06


      Input Offset Current (nA)

      0.045


      0.03


      0.015


      0


      -0.015


      -12

      -40 -10 20 50 80 110 130

      -0.03

      -40 -10 20 50 80 110 130

      Temperature (°C)

      DCIB

      Temperature (°C)

      DCIO



      V+


      Output Voltage (V)

      (V+) – 3 V


      (V+) – 6 V


      (V+) – 9 V

      Figure 9. Input Bias Current vs Temperature Figure 10. Input Offset Current vs Temperature

      –40C 25C

      125C

















































      (V–) + 18 V


      (V–) + 15 V


      Output Voltage (V)

      (V–) + 12 V


      (V–) + 9 V


      (V–) + 6 V


      –40C 25C

      125C

      (V–) + 3 V


      (V+) – 12 V


      0 10 20 30 40 50

      V–

      0 5 10 15 20 25 30 35 40

      Output Current (mA)


      DC13

      Output Current (mA)

      DC1-


      Figure 11. Output Voltage Swing vs Output Current (Sourcing)

      Figure 12. Output Voltage Swing vs Output Current (Sinking)

      Typical Characteristics (continued)

      PSRR+

      PSRR-

      CMRR

      Typical characteristics section is applicable for LM358B and LM2904B. The typical characteristics data section was taken with TA = 25°C, VS = 36 V (±18 V), VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2 (unless otherwise noted).

      100

      90

      PSRR and CMRR (dB)

      80

      70

      60

      50

      40

      30

      20

      10

      0


      1k 10k 100k 1M

      120


      Common-Mode Rejection Ratio (dB)





































      VS = 36V

      VS = 5V







      115


      110


      105


      100


      95


      90


      85

      -40 -10 20 50 80 110 130

      Frequency (Hz)


      D00

      Temperature (°C)

      DC2_

      Figure 13. CMRR and PSRR vs Frequency Figure 14. Common-Mode Rejection Ratio vs Temperature (dB)

      Power Supply Rejection Ratio (dB)














































      -118


      -119


      -120


      -121


      -122


      -123

      -40 -20 0 20 40 60 80 100 120 140

      1.6

      1.2

      0.8

      Voltage (µV)

      0.4

      0

      -0.4

      -0.8

      -1.2

      -1.6

      -2






















      0 1 2 3 4 5 6 7 8 9 10


      Voltage Noise Spectral Density (nV/Hz)

      100

      Temperature (°C)

      VS = 5 V to 36 V

      Figure 15. Power Supply Rejection Ratio vs Temperature (dB)

      DC8_ Time (s)


      Figure 16. 0.1-Hz to 10-Hz Noise


      -32

      D011

      90

      80

      70

      60

      50

      40

      30

      20

      10

      0

      10 100 1k 10k 100k

      10 k

      -40 2 k

      -48

      THD+N (dB)

      -56

      -64

      -72

      -80

      -88

      -96

      -104

      -112

      100 1k 10k

      Frequency (Hz)

      Frequency (Hz)

      D010

      G = 1, f = 1 kHz, BW = 80 kHz,

      VOUT = 10 VPP, RL connected to V–

      D013


      Figure 17. Input Voltage Noise Spectral Density vs Frequency


      Figure 18. THD+N Ratio vs Frequency, G = 1

      Typical Characteristics (continued)

      10 k

      2 k

      Typical characteristics section is applicable for LM358B and LM2904B. The typical characteristics data section was taken with TA = 25°C, VS = 36 V (±18 V), VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2 (unless otherwise noted).

      -32


      -40


      -48


      THD+N (dB)

      -56


      -64


      -72


      -80


      -88


      -96


      -104


      100 1k 10k

      -30


      -40


      -50


      THD+N (dB)

      -60


      -70


      -80


      -90


      10 k

      2 k

      -100


      -110


      -120

      0.001 0.01 0.1 1 10 20


      -20

      Frequency (Hz)

      G = –1, f = 1 kHz, BW = 80 kHz,

      VOUT = 10 VPP, RL connected to V–

      Figure 19. THD+N Ratio vs Frequency, G = –1

      D014


      460

      Amplitude (VPP)

      G = 1, f = 1 kHz, BW = 80 kHz,

      RL connected to V–

      Figure 20. THD+N vs Output Amplitude, G = 1

      D015


      -35


      THD+N (dB)

      -50


      -65


      -80


      -95

      430


      Quiescent Current (µA)





































      400


      370


      340


      310


      10 k

      2 k

      -110

      0.001 0.01 0.1 1 10 20

      280


      3 9 15 21 27 33 36

      Amplitude (VPP)

      G = –1, f = 1 kHz, BW = 80 kHz,

      RL connected to V–

      D016

      Supply Voltage (V)

      DC_S

      Figure 21. THD+N vs Output Amplitude, G = –1 Figure 22. Quiescent Current vs Supply Voltage

      Quiescent Current per Amplifier (µA)

      VS = 36V VS = 5V

































































































































      600 500


      Open Loop Output Impedance ()

      540

      400

      480


      420 300


      360

      200

      300


      240

      -40 -20 0 20 40 60 80 100 120

      100

      1k 10k 100k 1M

      Temperature (°C)

      DC4_

      Frequency (Hz)

      D006


      Figure 23. Quiescent Current vs Temperature Figure 24. Open-Loop Output Impedance vs Frequency

      Typical Characteristics (continued)

      Typical characteristics section is applicable for LM358B and LM2904B. The typical characteristics data section was taken with TA = 25°C, VS = 36 V (±18 V), VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2 (unless otherwise noted).

      Overshoot (+)

      Overshoot (-)















































































      44


      40


      36


      Overshoot (%)

      32


      28


      24


      20


      16


      12


      8

      0 40 80 120 160 200 240 280 320 360

      18


      Overshoot (+)

      Overshoot (–)

      16


      14


      Overshoot (%)

      12


      10


      8


      6


      4


      2


      0

      40 80 120 160 200 240 280 320 360

      Capacitance load (pF)

      G = 1, 100-mV output step, RL = open

      D019

      Capacitance load (pF)

      G = –1, 100-mV output step, RL = open

      D020


      Figure 25. Small-Signal Overshoot vs Capacitive Load

      60

      57

      54

      Phase Margin (°)

      51

      48

      45

      42

      39

      36

      33

      30

      0 40 80 120 160 200 240 280 320 360


      20


      Voltage (V)

      10


      0


      -10


      -20


      Figure 26. Small-Signal Overshoot vs Capacitive Load


      Input Output


      0 200 400 600 800 1000

      Capacitance Load (pF)


      Figure 27. Phase Margin vs Capacitive Load













































      Input Output





      10

      Time (s)

      D018

      G = –10


      Figure 28. Overload Recovery









































      Input Output





      10


      D021


      7.5


      5


      Voltage (mV)

      2.5


      0


      -2.5


      -5


      -7.5


      7.5


      5


      Voltage (mV)

      2.5


      0


      -2.5


      -5


      -7.5


      -10


      0 20 40 60 80 100


      -10


      0 20 40 60 80 100

      Time (s)

      G = 1, RL = open

      Figure 29. Small-Signal Step Response, G = 1


      D022

      Time (s)

      G = –1, RL = open, RFB = 10K

      Figure 30. Small-Signal Step Response, G = –1


      D023

      Typical Characteristics (continued)

      Typical characteristics section is applicable for LM358B and LM2904B. The typical characteristics data section was taken with TA = 25°C, VS = 36 V (±18 V), VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2 (unless otherwise noted).

      20

      Output Delta from Final Value (mV)

      16

      12

      8

      4

      0

      -4

      -8

      -12

      -16

      -20






















      0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5

      40

      Output Delta from Final Value (mV)

      32

      24

      16

      8

      0

      -8

      -16

      -24

      -32

      -40






















      0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5

      Time (s)

      G = 1, RL = open

      D003 Time (s)

      G = 1, RL = open

      D004


      2.5

      2

      1.5

      1

      Votlage (V)

      0.5

      0

      -0.5

      -1

      -1.5

      -2

      -2.5


      Figure 31. Large-Signal Step Response (Rising)






      Output

      Input





























































      0.675


      0.625


      Slew Rate(V/s)

      0.575


      0.525


      0.475


      0.425


      Figure 32. Large-Signal Step Response (Falling)


      Positive Negative

      0 20 40 60 80 100 -40 -25 -10 5 20 35 50 65 80 95 110 125

      Time (µs)

      G = 1, RL = open

      AC_S

      Temp(C)

      D009


      60


      Short-Circuit Current (mA)

      40


      20


      0


      -20


      -40


      -60

      Figure 33. Large-Signal Step Response Figure 34. Slew Rate vs Temperature


































      Sinking

      Sourcing


































      15

      14

      Maximum Output Voltage (VPP)

      13

      12

      11

      10

      9

      8

      7

      6

      5

      4

      3

      2

      1

      0

      -40 -25 -10 5 20 35 50 65 80 95 110 125

      1k 10k 100k 1M

      Temperature (°C)

      DC7_

      Frequency (Hz)

      VS = 15 V


      D005


      Figure 35. Short-Circuit Current vs Temperature Figure 36. Maximum Output Voltage vs Frequency

      Typical Characteristics (continued)

      D007

      90

      84

      78

      72

      66

      60

      54

      48

      42

      36

      30

      24

      1M

      D008

      -135

      1k

      -125

      -115

      -105

      -95

      -85

      -75

      Channel Separation (dB)

      EMIRR (dB)










































































































































































































































































































































      Typical characteristics section is applicable for LM358B and LM2904B. The typical characteristics data section was taken with TA = 25°C, VS = 36 V (±18 V), VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2 (unless otherwise noted).


      10k

      100k

      Frequency (Hz)

      1M

      10M

      100M

      Frequency (Hz)

      1G


      Figure 37. Channel Separation vs Frequency

      Figure 38. EMIRR (Electromagnetic Interference Rejection Ratio) vs Frequency

    12. Typical Characteristics

      Typical characteristics section is applicable for LM158, LM158A, LM258, LM258A, LM358, LM358A, LM2904, and LM2904V.


































































      5Vdc 15Vdc

      30Vdc






























      20

      18

      Input Current (nAdc)

      16

      14

      12

      10

      8

      6

      4

      2

      0

      –55 –35 –15 5 25 45 65 85 105 125

      Temperature (°C)

      0.36


      0.34


      Supply Current (mA)

      0.32


      0.3


      0.28


      0.26


      0.24


      0.22


      0.2









      –55C

      0C

      125C














































      0 5 10 15 20 25 30

      Supply Voltage (Vdc)



      160


      140


      Avol Voltage Gain (dB)

      120


      100


      80


      60


      40


      20


      0

      Figure 39. Input Current vs Temperature Figure 40. Supply Current vs Supply Voltage










      RL=20K

      RL=2K
































































      CMRR




































      100

      90

      80

      70

      CMRR (dB)

      60

      50

      40

      30

      20

      10

      0

      0 5 10 15 20 25 30 35 40 0.1 1 10 100 1000

      V+ Supply Voltage (Vdc)

      Frequency (kHz)


      C001



      3.5


      3.0


      Voltage (V)

      2.5


      2.0


      1.5


      1.0


      0.5

      Figure 41. Voltage Gain vs Supply Voltage Figure 42. Common-Mode Rejection Ratio vs Frequency









      VOUT



























































































      VOUT

      0.50


      0.45


      Voltage (V)

      0.40


      0.35


      0.30


      0.25


      0.0


      0 4 8 12 16 20 24 28 32 36 40

      0.20


      0 2 4 6 8 10

      Time (µs)


      C001

      Time (µs)


      C001


      Figure 43. Voltage Follower Large Signal Response (50 pF) Figure 44. Voltage Follower Small Signal Response (50 pF)

      Typical Characteristics (continued)

      85 105 125

      65

      45

      25

      5

      –55 –35 –15

      90

      80

      70

      60

      50

      40

      30

      20

      10

      0

      100

      10

      1

      0.1

      0.01

      0.001 0.01

      0.1

      1

      5Vdc

      15Vdc 30Vdc

      10

      Output Sink Current (mAdc)

      10

      Output Voltage (Vdc)

      Output Swing (Vp-p)

      Output Current (mAdc)

      Output Voltage (Vdc) relative to Vcc

      Typical characteristics section is applicable for LM158, LM158A, LM258, LM258A, LM358, LM358A, LM2904, and LM2904V.

      20


      17.5


      15


      12.5


      10


      7.5


      5


      2.5


      0

      1

      100

      Frequency (kHz)

      1k

      8


      7


      6


      5


      4


      3


      2


      1

      0.001

      0.01

      0.1

      1

      10

      100



      Figure 45. Maximum Output Swing vs Frequency (VCC = 15 V)

      Figure 46. Output Sourcing Characteristics




















































































      Output Sink Current (mAdc)

      Temperature (°C)



      Figure 47. Output Sinking Characteristics

      Figure 48. Source Current Limiting

  2. Parameter Measurement Information


VCC+



100


900


VCC+

VI +


VCC− CL

VO VI = 0 V

RS

RL

VO

+

VCC−



Figure 49. Unity-Gain Amplifier Figure 50. Noise-Test Circuit

10 k



VIN

+18V

+

RL

-18V


GND GND

Figure 51. Test Circuit, G = –1, for THD+N and Small-Signal Step Response

  1. Detailed Description


    1. Overview

      These devices consist of two independent, high-gain frequency-compensated operational amplifiers designed to operate from a single supply over a wide range of voltages. Operation from split supplies also is possible if the difference between the two supplies is within the supply voltage range specified in the Recommended Operating Conditions section, and VS is at least 1.5 V more positive than the input common-mode voltage. The low supply- current drain is independent of the magnitude of the supply voltage.

      Applications include transducer amplifiers, dc amplification blocks, and all the conventional operational amplifier circuits that now can be implemented more easily in single-supply-voltage systems. For example, these devices can be operated directly from the standard 5-V supply used in digital systems and easily can provide the required interface electronics without additional ±5-V supplies.


    2. Functional Block Diagram - LM358B, LM358BA, LM2904B, LM2904BA


      VCC+


      ~6 µA Curren t Regula tor

      ~6 µA Curren t Regula tor

      ~100 µA Curren t Regula tor


      IN-


      IN+


      ~120 µA Curren t Regula tor

      OUT

    3. Feature Description

      1. Unity-Gain Bandwidth

        The unity-gain bandwidth is the frequency up to which an amplifier with a unity gain may be operated without greatly distorting the signal. These devices have a 1.2-MHz unity-gain bandwidth (B Version).


      2. Slew Rate

        The slew rate is the rate at which an operational amplifier can change its output when there is a change on the input. These devices have a 0.5-V/µs slew rate (B Version).


      3. Input Common Mode Range

        The valid common mode range is from device ground to VS – 1.5 V (VS – 2 V across temperature). Inputs may exceed VS up to the maximum VS without device damage. At least one input must be in the valid input common- mode range for the output to be the correct phase. If both inputs exceed the valid range, then the output phase is undefined. If either input more than 0.3 V below V– then input current should be limited to 1 mA and the output phase is undefined.


    4. Device Functional Modes

      These devices are powered on when the supply is connected. This device can be operated as a single-supply operational amplifier or dual-supply amplifier, depending on the application.

  2. Application and Implementation


    NOTE

    Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.


    1. Application Information

      The LMx58 and LM2904 operational amplifiers are useful in a wide range of signal conditioning applications. Inputs can be powered before VS for flexibility in multiple supply circuits.

    2. Typical Application

      A typical application for an operational amplifier is an inverting amplifier. This amplifier takes a positive voltage on the input, and makes it a negative voltage of the same magnitude. In the same manner, it also makes negative voltages positive.

      RF



      VIN

      RI Vsup+


      +

      Vsup-


      VOUT



      Figure 52. Application Schematic


      1. Design Requirements

        The supply voltage must be chosen such that it is larger than the input voltage range and output range. For instance, this application scales a signal of ±0.5 V to ±1.8 V. Setting the supply at ±12 V is sufficient to accommodate this application.


      2. Detailed Design Procedure

        Determine the gain required by the inverting amplifier using Equation 1 and Equation 2:

        VOUT

        A V

        VIN


        (1)

        A V

        1.8

        0.5

        3.6


        (2)

        Once the desired gain is determined, choose a value for RI or RF. [Subscripts should be fixed in the accompanying figures and equations also.] Choosing a value in the kilohm range is desirable because the amplifier circuit uses currents in the milliampere range. This ensures the part does not draw too much current. This example uses 10 kΩ for RI which means 36 kΩ is used for RF. This was determined by Equation 3.

        RF

        A V RI



        Typical Application (continued)

      3. Application Curve


        2

        VIN

        1.5

        VOUT

        1


        0.5


        Volts

        0


        -0.5


        -1


        -1.5


        -2

        0 0.5 1 1.5 2

        Time (ms)

        Figure 53. Input and Output Voltages of the Inverting Amplifier


  3. Power Supply Recommendations


    CAUTION

    Supply voltages larger than specified in the recommended operating region can permanently damage the device (see the Absolute Maximum Ratings).


    Place 0.1-µF bypass capacitors close to the power-supply pins to reduce errors coupling in from noisy or high- impedance power supplies. For more detailed information on bypass capacitor placement, see the Layout section.


  4. Layout


    1. Layout Guidelines

      For best operational performance of the device, use good PCB layout practices, including:

      • Noise can propagate into analog circuitry through the power pins of the circuit as a whole, as well as the operational amplifier. Bypass capacitors are used to reduce the coupled noise by providing low-impedance power sources local to the analog circuitry.

        – Connect low-ESR, 0.1-µF ceramic bypass capacitors between each supply pin and ground, placed as close to the device as possible. A single bypass capacitor from V+ to ground is applicable for single- supply applications.

      • Separate grounding for analog and digital portions of circuitry is one of the simplest and most-effective methods of noise suppression. One or more layers on multilayer PCBs are usually devoted to ground planes. A ground plane helps distribute heat and reduces EMI noise pickup. Make sure to physically separate digital and analog grounds, paying attention to the flow of the ground current.

      • To reduce parasitic coupling, run the input traces as far away from the supply or output traces as possible. If it is not possible to keep them separate, it is much better to cross the sensitive trace perpendicular as opposed to in parallel with the noisy trace. [Things in parallel never cross, by definition]

      • Place the external components as close to the device as possible. Keeping RF and RG close to the inverting input minimizes parasitic capacitance, as shown in Layout Examples.

      • Keep the length of input traces as short as possible. Always remember that the input traces are the most sensitive part of the circuit.

      • Consider a driven, low-impedance guard ring around the critical traces. A guard ring can significantly reduce leakage currents from nearby traces that are at different potentials.

        RF

    2. Layout Examples



      Run the input traces as far

      away from the supply lines as possible

      Place components close to

      device and to each other to reduce parasitic errors

      VS+


      OUT1

      V+


      RG


      GND

      IN1-

      OUT2


      VIN

      IN1+

      IN2-

      GND


      RIN


      V-

      IN2+

      Only needed for

      dual-supply operation

      Use low-ESR, ceramic

      bypass capacitor

      GND

      Ground (GND) plane on another layer


      VS-

      (or GND for single supply)

      Figure 54. Operational Amplifier Board Layout for Noninverting Configuration



      VIN

      RIN

      +


      RG

      RF


      VOUT


      Figure 55. Operational Amplifier Schematic for Noninverting Configuration

  5. Device and Documentation Support


    1. Documentation Support

      1. Related Documentation

    2. Related Links

      The table below lists quick access links. Categories include technical documents, support and community resources, tools and software, and quick access to order now.


      Table 1. Related Links


      PARTS

      PRODUCT FOLDER

      ORDER NOW

      TECHNICAL DOCUMENTS

      TOOLS & SOFTWARE

      SUPPORT & COMMUNITY

      LM158

      Click here

      Click here

      Click here

      Click here

      Click here

      LM158A

      Click here

      Click here

      Click here

      Click here

      Click here

      LM258

      Click here

      Click here

      Click here

      Click here

      Click here

      LM258A

      Click here

      Click here

      Click here

      Click here

      Click here

      LM358

      Click here

      Click here

      Click here

      Click here

      Click here

      LM358A

      Click here

      Click here

      Click here

      Click here

      Click here

      LM358B

      Click here

      Click here

      Click here

      Click here

      Click here

      LM2904

      Click here

      Click here

      Click here

      Click here

      Click here

      LM2904B

      Click here

      Click here

      Click here

      Click here

      Click here

      LM2904V

      Click here

      Click here

      Click here

      Click here

      Click here


    3. Receiving Notification of Documentation Updates

      To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper right corner, click on Alert me to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document.


    4. Community Resources

      TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight from the experts. Search existing answers or ask your own question to get the quick design help you need.

      Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use.

    5. Trademarks

      E2E is a trademark of Texas Instruments.

      All other trademarks are the property of their respective owners.

    6. Electrostatic Discharge Caution

      This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

      ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.


    7. Glossary

      SLYZ022 TI Glossary.

      This glossary lists and explains terms, acronyms and definitions.

  6. Mechanical, Packaging, and Orderable Information

The following pages include mechanical packaging and orderable information. This information is the most- current data available for the designated devices. This data is subject to change without notice and without revision of this document. For browser based versions of this data sheet, see the left-hand navigation pane.

PACKAGING INFORMATION


Orderable Device

Status

(1)

Package Type

Package Drawing

Pins

Package Qty

Eco Plan

(2)

Lead/Ball Finish

(6)

MSL Peak Temp

(3)

Op Temp (°C)

Device Marking

(4/5)

Samples

5962-87710012A

ACTIVE

LCCC

FK

20

1

TBD

POST-PLATE

N / A for Pkg Type

-55 to 125

5962-

87710012A LM158FKB


5962-8771001PA

ACTIVE

CDIP

JG

8

1

TBD

Call TI

N / A for Pkg Type

-55 to 125

8771001PA LM158


5962-87710022A

ACTIVE

LCCC

FK

20

1

TBD

POST-PLATE

N / A for Pkg Type

-55 to 125

5962-

87710022A LM158AFKB


5962-8771002PA

ACTIVE

CDIP

JG

8

1

TBD

Call TI

N / A for Pkg Type

-55 to 125

8771002PA LM158A


LM158 MW8

ACTIVE

WAFERSALE

YS

0

1

Green (RoHS & no Sb/Br)

Call TI

Level-1-NA-UNLIM

-55 to 125



LM158AFKB

ACTIVE

LCCC

FK

20

1

TBD

POST-PLATE

N / A for Pkg Type

-55 to 125

5962-

87710022A LM158AFKB


LM158AJG

ACTIVE

CDIP

JG

8

1

TBD

Call TI

N / A for Pkg Type

-55 to 125

LM158AJG


LM158AJGB

ACTIVE

CDIP

JG

8

1

TBD

Call TI

N / A for Pkg Type

-55 to 125

8771002PA LM158A


LM158FKB

ACTIVE

LCCC

FK

20

1

TBD

POST-PLATE

N / A for Pkg Type

-55 to 125

5962-

87710012A LM158FKB


LM158JG

ACTIVE

CDIP

JG

8

1

TBD

Call TI

N / A for Pkg Type

-55 to 125

LM158JG


LM158JGB

ACTIVE

CDIP

JG

8

1

TBD

Call TI

N / A for Pkg Type

-55 to 125

8771001PA LM158


LM258AD

ACTIVE

SOIC

D

8

75

Green (RoHS & no Sb/Br)

NIPDAU

Level-1-260C-UNLIM

-25 to 85

LM258A


LM258ADGKR

ACTIVE

VSSOP

DGK

8

2500

Green (RoHS & no Sb/Br)

NIPDAU | NIPDAUAG

Level-1-260C-UNLIM

-25 to 85

(M3L, M3P, M3S, M3 U)


LM258ADR

ACTIVE

SOIC

D

8

2500

Green (RoHS & no Sb/Br)

NIPDAU | SN

Level-1-260C-UNLIM

-25 to 85

LM258A


LM258ADRE4

ACTIVE

SOIC

D

8

2500

Green (RoHS & no Sb/Br)

NIPDAU

Level-1-260C-UNLIM

-25 to 85

LM258A


LM258ADRG4

ACTIVE

SOIC

D

8

2500

Green (RoHS & no Sb/Br)

NIPDAU

Level-1-260C-UNLIM

-25 to 85

LM258A



Orderable Device

Status

(1)

Package Type

Package Drawing

Pins

Package Qty

Eco Plan

(2)

Lead/Ball Finish

(6)

MSL Peak Temp

(3)

Op Temp (°C)

Device Marking

(4/5)

Samples

LM258AP

ACTIVE

PDIP

P

8

50

Green (RoHS & no Sb/Br)

NIPDAU | SN

N / A for Pkg Type

-25 to 85

LM258AP


LM258APE4

ACTIVE

PDIP

P

8

50

Pb-Free (RoHS)

NIPDAU

N / A for Pkg Type

-25 to 85

LM258AP


LM258D

ACTIVE

SOIC

D

8

75

Green (RoHS & no Sb/Br)

NIPDAU

Level-1-260C-UNLIM

-25 to 85

LM258


LM258DG4

ACTIVE

SOIC

D

8

75

Green (RoHS & no Sb/Br)

NIPDAU

Level-1-260C-UNLIM

-25 to 85

LM258


LM258DGKR

ACTIVE

VSSOP

DGK

8

2500

Green (RoHS & no Sb/Br)

NIPDAU | NIPDAUAG

Level-1-260C-UNLIM

-25 to 85

(M2L, M2P, M2S, M2 U)


LM258DGKRG4

ACTIVE

VSSOP

DGK

8

2500

Green (RoHS & no Sb/Br)

NIPDAUAG

Level-1-260C-UNLIM

-25 to 85

(M2L, M2P, M2S, M2 U)


LM258DR

ACTIVE

SOIC

D

8

2500

Green (RoHS & no Sb/Br)

NIPDAU | SN

Level-1-260C-UNLIM

-25 to 85

LM258


LM258DRG3

ACTIVE

SOIC

D

8

2500

Green (RoHS & no Sb/Br)

SN

Level-1-260C-UNLIM

-25 to 85

LM258


LM258DRG4

ACTIVE

SOIC

D

8

2500

Green (RoHS & no Sb/Br)

NIPDAU

Level-1-260C-UNLIM

-25 to 85

LM258


LM258P

ACTIVE

PDIP

P

8

50

Green (RoHS & no Sb/Br)

NIPDAU | SN

N / A for Pkg Type

-25 to 85

LM258P


LM258PE4

ACTIVE

PDIP

P

8

50

Pb-Free (RoHS)

NIPDAU

N / A for Pkg Type

-25 to 85

LM258P


LM2904AVQDR

ACTIVE

SOIC

D

8

2500

Green (RoHS & no Sb/Br)

NIPDAU

Level-1-260C-UNLIM

-40 to 125

L2904AV


LM2904AVQDRG4

ACTIVE

SOIC

D

8

2500

Green (RoHS & no Sb/Br)

NIPDAU

Level-1-260C-UNLIM

-40 to 125

L2904AV


LM2904AVQPWR

ACTIVE

TSSOP

PW

8

2000

Green (RoHS & no Sb/Br)

NIPDAU

Level-1-260C-UNLIM

-40 to 125

L2904AV


LM2904AVQPWRG4

ACTIVE

TSSOP

PW

8

2000

Green (RoHS & no Sb/Br)

NIPDAU

Level-1-260C-UNLIM

-40 to 125

L2904AV


LM2904BAIDR

ACTIVE

SOIC

D

8

2500

Green (RoHS & no Sb/Br)

NIPDAU

Level-2-260C-1 YEAR

-40 to 125

2904BA


LM2904BIDR

ACTIVE

SOIC

D

8

2500

Green (RoHS & no Sb/Br)

NIPDAU

Level-2-260C-1 YEAR

-40 to 125

L2904B


LM2904BIPWR

PREVIEW

TSSOP

PW

8

2000

TBD

Call TI

Call TI

-40 to 125




Orderable Device

Status

(1)

Package Type

Package Drawing

Pins

Package Qty

Eco Plan

(2)

Lead/Ball Finish

(6)

MSL Peak Temp

(3)

Op Temp (°C)

Device Marking

(4/5)

Samples

LM2904D

ACTIVE

SOIC

D

8

75

Green (RoHS & no Sb/Br)

NIPDAU

Level-1-260C-UNLIM

-40 to 125

LM2904


LM2904DE4

ACTIVE

SOIC

D

8

75

Green (RoHS & no Sb/Br)

NIPDAU

Level-1-260C-UNLIM

-40 to 125

LM2904


LM2904DG4

ACTIVE

SOIC

D

8

75

Green (RoHS & no Sb/Br)

NIPDAU

Level-1-260C-UNLIM

-40 to 125

LM2904


LM2904DGKR

ACTIVE

VSSOP

DGK

8

2500

Green (RoHS & no Sb/Br)

NIPDAU | NIPDAUAG

Level-1-260C-UNLIM

-40 to 125

(MBL, MBP, MBS, MB U)


LM2904DGKRG4

ACTIVE

VSSOP

DGK

8

2500

Green (RoHS & no Sb/Br)

NIPDAUAG

Level-1-260C-UNLIM

-40 to 125

(MBL, MBP, MBS, MB U)


LM2904DR

ACTIVE

SOIC

D

8

2500

Green (RoHS & no Sb/Br)

NIPDAU | SN

Level-1-260C-UNLIM

-40 to 125

LM2904


LM2904DRE4

ACTIVE

SOIC

D

8

2500

Green (RoHS & no Sb/Br)

NIPDAU

Level-1-260C-UNLIM

-40 to 125

LM2904


LM2904DRG3

ACTIVE

SOIC

D

8

2500

Green (RoHS & no Sb/Br)

SN

Level-1-260C-UNLIM

-40 to 125

LM2904


LM2904DRG4

ACTIVE

SOIC

D

8

2500

Green (RoHS & no Sb/Br)

NIPDAU

Level-1-260C-UNLIM

-40 to 125

LM2904


LM2904P

ACTIVE

PDIP

P

8

50

Green (RoHS & no Sb/Br)

NIPDAU | SN

N / A for Pkg Type

-40 to 125

LM2904P


LM2904PE4

ACTIVE

PDIP

P

8

50

Pb-Free (RoHS)

NIPDAU

N / A for Pkg Type

-40 to 125

LM2904P


LM2904PSR

ACTIVE

SO

PS

8

2000

Green (RoHS & no Sb/Br)

NIPDAU

Level-1-260C-UNLIM

-40 to 125

L2904


LM2904PW

ACTIVE

TSSOP

PW

8

150

Green (RoHS & no Sb/Br)

NIPDAU

Level-1-260C-UNLIM

-40 to 125

L2904


LM2904PWR

ACTIVE

TSSOP

PW

8

2000

Green (RoHS & no Sb/Br)

NIPDAU | SN

Level-1-260C-UNLIM

-40 to 125

L2904


LM2904PWRG3

ACTIVE

TSSOP

PW

8

2000

Green (RoHS & no Sb/Br)

SN

Level-1-260C-UNLIM

-40 to 125

L2904


LM2904PWRG4-JF

ACTIVE

TSSOP

PW

8

2000

Green (RoHS & no Sb/Br)

NIPDAU

Level-1-260C-UNLIM

-40 to 125

L2904


LM2904QDR

ACTIVE

SOIC

D

8

2500

Green (RoHS & no Sb/Br)

NIPDAU

Level-1-260C-UNLIM

-40 to 125

2904Q1


LM2904QDRG4

ACTIVE

SOIC

D

8

2500

Green (RoHS & no Sb/Br)

NIPDAU

Level-1-260C-UNLIM

-40 to 125

2904Q1



Orderable Device

Status

(1)

Package Type

Package Drawing

Pins

Package Qty

Eco Plan

(2)

Lead/Ball Finish

(6)

MSL Peak Temp

(3)

Op Temp (°C)

Device Marking

(4/5)

Samples

LM2904VQDR

ACTIVE

SOIC

D

8

2500

Green (RoHS & no Sb/Br)

NIPDAU

Level-1-260C-UNLIM

-40 to 125

L2904V


LM2904VQDRG4

ACTIVE

SOIC

D

8

2500

Green (RoHS & no Sb/Br)

NIPDAU

Level-1-260C-UNLIM

-40 to 125

L2904V


LM2904VQPWR

ACTIVE

TSSOP

PW

8

2000

Green (RoHS & no Sb/Br)

NIPDAU

Level-1-260C-UNLIM

-40 to 125

L2904V


LM2904VQPWRG4

ACTIVE

TSSOP

PW

8

2000

Green (RoHS & no Sb/Br)

NIPDAU

Level-1-260C-UNLIM

-40 to 125

L2904V


LM358AD

ACTIVE

SOIC

D

8

75

Green (RoHS & no Sb/Br)

NIPDAU

Level-1-260C-UNLIM

0 to 70

LM358A


LM358ADE4

ACTIVE

SOIC

D

8

75

Green (RoHS & no Sb/Br)

NIPDAU

Level-1-260C-UNLIM

0 to 70

LM358A


LM358ADG4

ACTIVE

SOIC

D

8

75

Green (RoHS & no Sb/Br)

NIPDAU

Level-1-260C-UNLIM

0 to 70

LM358A


LM358ADGKR

ACTIVE

VSSOP

DGK

8

2500

Green (RoHS & no Sb/Br)

NIPDAU | NIPDAUAG

Level-1-260C-UNLIM

0 to 70

(M6L, M6P, M6S, M6 U)


LM358ADGKRG4

ACTIVE

VSSOP

DGK

8

2500

Green (RoHS & no Sb/Br)

NIPDAUAG

Level-1-260C-UNLIM

0 to 70

(M6L, M6P, M6S, M6 U)


LM358ADR

ACTIVE

SOIC

D

8

2500

Green (RoHS & no Sb/Br)

NIPDAU | SN

Level-1-260C-UNLIM

0 to 70

LM358A


LM358ADRE4

ACTIVE

SOIC

D

8

2500

Green (RoHS & no Sb/Br)

NIPDAU

Level-1-260C-UNLIM

0 to 70

LM358A


LM358ADRG4

ACTIVE

SOIC

D

8

2500

Green (RoHS & no Sb/Br)

NIPDAU

Level-1-260C-UNLIM

0 to 70

LM358A


LM358AP

ACTIVE

PDIP

P

8

50

Green (RoHS & no Sb/Br)

NIPDAU | SN

N / A for Pkg Type

0 to 70

LM358AP


LM358APE4

ACTIVE

PDIP

P

8

50

Pb-Free (RoHS)

NIPDAU

N / A for Pkg Type

0 to 70

LM358AP


LM358APW

ACTIVE

TSSOP

PW

8

150

Green (RoHS & no Sb/Br)

NIPDAU

Level-1-260C-UNLIM

0 to 70

L358A


LM358APWR

ACTIVE

TSSOP

PW

8

2000

Green (RoHS & no Sb/Br)

NIPDAU | SN

Level-1-260C-UNLIM

0 to 70

L358A


LM358APWRG4

ACTIVE

TSSOP

PW

8

2000

Green (RoHS & no Sb/Br)

NIPDAU

Level-1-260C-UNLIM

0 to 70

L358A


LM358BAIDR

ACTIVE

SOIC

D

8

2500

Green (RoHS & no Sb/Br)

NIPDAU

Level-2-260C-1 YEAR

-40 to 125

L358BA



Orderable Device

Status

(1)

Package Type

Package Drawing

Pins

Package Qty

Eco Plan

(2)

Lead/Ball Finish

(6)

MSL Peak Temp

(3)

Op Temp (°C)

Device Marking

(4/5)

Samples

LM358BIDR

ACTIVE

SOIC

D

8

2500

Green (RoHS & no Sb/Br)

NIPDAU

Level-2-260C-1 YEAR

-40 to 85

LM358B


LM358BIPWR

PREVIEW

TSSOP

PW

8

2000

TBD

Call TI

Call TI

-40 to 85



LM358D

ACTIVE

SOIC

D

8

75

Green (RoHS & no Sb/Br)

NIPDAU

Level-1-260C-UNLIM

0 to 70

LM358


LM358DG4

ACTIVE

SOIC

D

8

75

Green (RoHS & no Sb/Br)

NIPDAU

Level-1-260C-UNLIM

0 to 70

LM358


LM358DGKR

ACTIVE

VSSOP

DGK

8

2500

Green (RoHS & no Sb/Br)

NIPDAU | NIPDAUAG

Level-1-260C-UNLIM

0 to 70

(M5L, M5P, M5S, M5 U)


LM358DGKRG4

ACTIVE

VSSOP

DGK

8

2500

Green (RoHS & no Sb/Br)

NIPDAUAG

Level-1-260C-UNLIM

0 to 70

(M5L, M5P, M5S, M5 U)


LM358DR

ACTIVE

SOIC

D

8

2500

Green (RoHS & no Sb/Br)

NIPDAU | SN

Level-1-260C-UNLIM

0 to 70

LM358


LM358DRE4

ACTIVE

SOIC

D

8

2500

Green (RoHS & no Sb/Br)

NIPDAU

Level-1-260C-UNLIM

0 to 70

LM358


LM358DRG3

ACTIVE

SOIC

D

8

2500

Green (RoHS & no Sb/Br)

SN

Level-1-260C-UNLIM

0 to 70

LM358


LM358DRG4

ACTIVE

SOIC

D

8

2500

Green (RoHS & no Sb/Br)

NIPDAU

Level-1-260C-UNLIM

0 to 70

LM358


LM358P

ACTIVE

PDIP

P

8

50

Green (RoHS & no Sb/Br)

NIPDAU | SN

N / A for Pkg Type

0 to 70

LM358P


LM358PE3

ACTIVE

PDIP

P

8

50

Pb-Free (RoHS)

SN

N / A for Pkg Type

0 to 70

LM358P


LM358PE4

ACTIVE

PDIP

P

8

50

Green (RoHS & no Sb/Br)

NIPDAU

N / A for Pkg Type

0 to 70

LM358P


LM358PSR

ACTIVE

SO

PS

8

2000

Green (RoHS & no Sb/Br)

NIPDAU

Level-1-260C-UNLIM

0 to 70

L358


LM358PW

ACTIVE

TSSOP

PW

8

150

Green (RoHS & no Sb/Br)

NIPDAU

Level-1-260C-UNLIM

0 to 70

L358


LM358PWR

ACTIVE

TSSOP

PW

8

2000

Green (RoHS & no Sb/Br)

NIPDAU | SN

Level-1-260C-UNLIM

0 to 70

L358


LM358PWRG3

ACTIVE

TSSOP

PW

8

2000

Green (RoHS & no Sb/Br)

SN

Level-1-260C-UNLIM

0 to 70

L358


LM358PWRG4

ACTIVE

TSSOP

PW

8

2000

Green (RoHS & no Sb/Br)

NIPDAU

Level-1-260C-UNLIM

0 to 70

L358



Orderable Device

Status

(1)

Package Type

Package Drawing

Pins

Package Qty

Eco Plan

(2)

Lead/Ball Finish

(6)

MSL Peak Temp

(3)

Op Temp (°C)

Device Marking

(4/5)

Samples

LM358PWRG4-JF

ACTIVE

TSSOP

PW

8

2000

Green (RoHS & no Sb/Br)

NIPDAU

Level-1-260C-UNLIM

0 to 70

L358


PLM2904BIPWR

ACTIVE

TSSOP

PW

8

2000

TBD

Call TI

Call TI

-40 to 125



PLM358BIPWR

ACTIVE

TSSOP

PW

8

2000

TBD

Call TI

Call TI

-40 to 85




(1) The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.


(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free".

RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.

Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement.


(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.


(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.


(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device.


(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width.


Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.


In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.


OTHER QUALIFIED VERSIONS OF LM258A, LM2904, LM2904B :

TAPE AND REEL INFORMATION


*All dimensions are nominal

Device

Package Type

Package Drawing

Pins

SPQ

Reel Diameter (mm)

Reel Width W1 (mm)

A0

(mm)

B0

(mm)

K0

(mm)

P1

(mm)

W

(mm)

Pin1 Quadrant

LM258ADGKR

VSSOP

DGK

8

2500

330.0

12.4

5.3

3.4

1.4

8.0

12.0

Q1

LM258ADR

SOIC

D

8

2500

330.0

12.4

6.4

5.2

2.1

8.0

12.0

Q1

LM258ADR

SOIC

D

8

2500

330.0

15.4

6.4

5.2

2.1

8.0

12.0

Q1

LM258ADR

SOIC

D

8

2500

330.0

12.8

6.4

5.2

2.1

8.0

12.0

Q1

LM258ADR

SOIC

D

8

2500

330.0

12.4

6.4

5.2

2.1

8.0

12.0

Q1

LM258ADRG4

SOIC

D

8

2500

330.0

12.4

6.4

5.2

2.1

8.0

12.0

Q1

LM258ADRG4

SOIC

D

8

2500

330.0

12.4

6.4

5.2

2.1

8.0

12.0

Q1

LM258DGKR

VSSOP

DGK

8

2500

330.0

12.4

5.3

3.4

1.4

8.0

12.0

Q1

LM258DR

SOIC

D

8

2500

330.0

12.4

6.4

5.2

2.1

8.0

12.0

Q1

LM258DR

SOIC

D

8

2500

330.0

12.4

6.4

5.2

2.1

8.0

12.0

Q1

LM258DR

SOIC

D

8

2500

330.0

15.4

6.4

5.2

2.1

8.0

12.0

Q1

LM258DR

SOIC

D

8

2500

330.0

12.8

6.4

5.2

2.1

8.0

12.0

Q1

LM258DRG3

SOIC

D

8

2500

330.0

12.8

6.4

5.2

2.1

8.0

12.0

Q1

LM258DRG3

SOIC

D

8

2500

330.0

15.4

6.4

5.2

2.1

8.0

12.0

Q1

LM258DRG4

SOIC

D

8

2500

330.0

12.4

6.4

5.2

2.1

8.0

12.0

Q1

LM258DRG4

SOIC

D

8

2500

330.0

12.4

6.4

5.2

2.1

8.0

12.0

Q1

LM2904AVQDR

SOIC

D

8

2500

330.0

12.5

6.4

5.2

2.1

8.0

12.0

Q1

LM2904AVQDRG4

SOIC

D

8

2500

330.0

12.5

6.4

5.2

2.1

8.0

12.0

Q1


Device

Package Type

Package Drawing

Pins

SPQ

Reel Diameter (mm)

Reel Width W1 (mm)

A0

(mm)

B0

(mm)

K0

(mm)

P1

(mm)

W

(mm)

Pin1 Quadrant

LM2904AVQPWR

TSSOP

PW

8

2000

330.0

12.4

7.0

3.6

1.6

8.0

12.0

Q1

LM2904AVQPWRG4

TSSOP

PW

8

2000

330.0

12.4

7.0

3.6

1.6

8.0

12.0

Q1

LM2904BAIDR

SOIC

D

8

2500

330.0

12.4

6.4

5.2

2.1

8.0

12.0

Q1

LM2904BIDR

SOIC

D

8

2500

330.0

12.4

6.4

5.2

2.1

8.0

12.0

Q1

LM2904DGKR

VSSOP

DGK

8

2500

330.0

12.4

5.3

3.4

1.4

8.0

12.0

Q1

LM2904DGKR

VSSOP

DGK

8

2500

330.0

12.4

5.3

3.4

1.4

8.0

12.0

Q1

LM2904DR

SOIC

D

8

2500

330.0

12.4

6.4

5.2

2.1

8.0

12.0

Q1

LM2904DR

SOIC

D

8

2500

330.0

15.4

6.4

5.2

2.1

8.0

12.0

Q1

LM2904DR

SOIC

D

8

2500

330.0

12.8

6.4

5.2

2.1

8.0

12.0

Q1

LM2904DR

SOIC

D

8

2500

330.0

12.4

6.4

5.2

2.1

8.0

12.0

Q1

LM2904DRG3

SOIC

D

8

2500

330.0

15.4

6.4

5.2

2.1

8.0

12.0

Q1

LM2904DRG3

SOIC

D

8

2500

330.0

12.8

6.4

5.2

2.1

8.0

12.0

Q1

LM2904DRG4

SOIC

D

8

2500

330.0

12.4

6.4

5.2

2.1

8.0

12.0

Q1

LM2904DRG4

SOIC

D

8

2500

330.0

12.4

6.4

5.2

2.1

8.0

12.0

Q1

LM2904PWR

TSSOP

PW

8

2000

330.0

12.4

7.0

3.6

1.6

8.0

12.0

Q1

LM2904PWR

TSSOP

PW

8

2000

330.0

12.4

7.0

3.6

1.6

8.0

12.0

Q1

LM2904PWRG3

TSSOP

PW

8

2000

330.0

12.4

7.0

3.6

1.6

8.0

12.0

Q1

LM2904PWRG4-JF

TSSOP

PW

8

2000

330.0

12.4

7.0

3.6

1.6

8.0

12.0

Q1

LM2904QDR

SOIC

D

8

2500

330.0

12.4

6.4

5.2

2.1

8.0

12.0

Q1

LM2904VQDR

SOIC

D

8

2500

330.0

12.5

6.4

5.2

2.1

8.0

12.0

Q1

LM2904VQPWR

TSSOP

PW

8

2000

330.0

12.4

7.0

3.6

1.6

8.0

12.0

Q1

LM2904VQPWRG4

TSSOP

PW

8

2000

330.0

12.4

7.0

3.6

1.6

8.0

12.0

Q1

LM358ADGKR

VSSOP

DGK

8

2500

330.0

12.4

5.3

3.4

1.4

8.0

12.0

Q1

LM358ADR

SOIC

D

8

2500

330.0

12.4

6.4

5.2

2.1

8.0

12.0

Q1

LM358ADR

SOIC

D

8

2500

330.0

15.4

6.4

5.2

2.1

8.0

12.0

Q1

LM358ADR

SOIC

D

8

2500

330.0

12.4

6.4

5.2

2.1

8.0

12.0

Q1

LM358ADR

SOIC

D

8

2500

330.0

12.8

6.4

5.2

2.1

8.0

12.0

Q1

LM358ADRG4

SOIC

D

8

2500

330.0

12.4

6.4

5.2

2.1

8.0

12.0

Q1

LM358ADRG4

SOIC

D

8

2500

330.0

12.4

6.4

5.2

2.1

8.0

12.0

Q1

LM358APWR

TSSOP

PW

8

2000

330.0

12.4

7.0

3.6

1.6

8.0

12.0

Q1

LM358APWR

TSSOP

PW

8

2000

330.0

12.4

7.0

3.6

1.6

8.0

12.0

Q1

LM358APWRG4

TSSOP

PW

8

2000

330.0

12.4

7.0

3.6

1.6

8.0

12.0

Q1

LM358BAIDR

SOIC

D

8

2500

330.0

12.4

6.4

5.2

2.1

8.0

12.0

Q1

LM358BIDR

SOIC

D

8

2500

330.0

12.4

6.4

5.2

2.1

8.0

12.0

Q1

LM358DGKR

VSSOP

DGK

8

2500

330.0

12.4

5.3

3.4

1.4

8.0

12.0

Q1

LM358DGKR

VSSOP

DGK

8

2500

330.0

12.4

5.3

3.4

1.4

8.0

12.0

Q1

LM358DR

SOIC

D

8

2500

330.0

12.8

6.4

5.2

2.1

8.0

12.0

Q1

LM358DR

SOIC

D

8

2500

330.0

12.4

6.4

5.2

2.1

8.0

12.0

Q1

LM358DR

SOIC

D

8

2500

330.0

15.4

6.4

5.2

2.1

8.0

12.0

Q1

LM358DR

SOIC

D

8

2500

330.0

12.4

6.4

5.2

2.1

8.0

12.0

Q1

LM358DRG3

SOIC

D

8

2500

330.0

15.4

6.4

5.2

2.1

8.0

12.0

Q1

LM358DRG3

SOIC

D

8

2500

330.0

12.8

6.4

5.2

2.1

8.0

12.0

Q1

LM358DRG4

SOIC

D

8

2500

330.0

12.4

6.4

5.2

2.1

8.0

12.0

Q1


Device

Package Type

Package Drawing

Pins

SPQ

Reel Diameter (mm)

Reel Width W1 (mm)

A0

(mm)

B0

(mm)

K0

(mm)

P1

(mm)

W

(mm)

Pin1 Quadrant

LM358DRG4

SOIC

D

8

2500

330.0

12.4

6.4

5.2

2.1

8.0

12.0

Q1

LM358PWR

TSSOP

PW

8

2000

330.0

12.4

7.0

3.6

1.6

8.0

12.0

Q1

LM358PWR

TSSOP

PW

8

2000

330.0

12.4

7.0

3.6

1.6

8.0

12.0

Q1

LM358PWRG3

TSSOP

PW

8

2000

330.0

12.4

7.0

3.6

1.6

8.0

12.0

Q1

LM358PWRG4

TSSOP

PW

8

2000

330.0

12.4

7.0

3.6

1.6

8.0

12.0

Q1

LM358PWRG4-JF

TSSOP

PW

8

2000

330.0

12.4

7.0

3.6

1.6

8.0

12.0

Q1


*All dimensions are nominal

Device

Package Type

Package Drawing

Pins

SPQ

Length (mm)

Width (mm)

Height (mm)

LM258ADGKR

VSSOP

DGK

8

2500

364.0

364.0

27.0

LM258ADR

SOIC

D

8

2500

340.5

338.1

20.6

LM258ADR

SOIC

D

8

2500

333.2

345.9

28.6

LM258ADR

SOIC

D

8

2500

364.0

364.0

27.0

LM258ADR

SOIC

D

8

2500

367.0

367.0

35.0

LM258ADRG4

SOIC

D

8

2500

340.5

338.1

20.6

LM258ADRG4

SOIC

D

8

2500

367.0

367.0

35.0

LM258DGKR

VSSOP

DGK

8

2500

364.0

364.0

27.0

LM258DR

SOIC

D

8

2500

340.5

338.1

20.6

LM258DR

SOIC

D

8

2500

367.0

367.0

35.0

LM258DR

SOIC

D

8

2500

333.2

345.9

28.6


Device

Package Type

Package Drawing

Pins

SPQ

Length (mm)

Width (mm)

Height (mm)

LM258DR

SOIC

D

8

2500

364.0

364.0

27.0

LM258DRG3

SOIC

D

8

2500

364.0

364.0

27.0

LM258DRG3

SOIC

D

8

2500

333.2

345.9

28.6

LM258DRG4

SOIC

D

8

2500

340.5

338.1

20.6

LM258DRG4

SOIC

D

8

2500

367.0

367.0

35.0

LM2904AVQDR

SOIC

D

8

2500

340.5

338.1

20.6

LM2904AVQDRG4

SOIC

D

8

2500

340.5

338.1

20.6

LM2904AVQPWR

TSSOP

PW

8

2000

367.0

367.0

35.0

LM2904AVQPWRG4

TSSOP

PW

8

2000

367.0

367.0

35.0

LM2904BAIDR

SOIC

D

8

2500

340.5

338.1

20.6

LM2904BIDR

SOIC

D

8

2500

340.5

338.1

20.6

LM2904DGKR

VSSOP

DGK

8

2500

364.0

364.0

27.0

LM2904DGKR

VSSOP

DGK

8

2500

358.0

335.0

35.0

LM2904DR

SOIC

D

8

2500

340.5

338.1

20.6

LM2904DR

SOIC

D

8

2500

333.2

345.9

28.6

LM2904DR

SOIC

D

8

2500

364.0

364.0

27.0

LM2904DR

SOIC

D

8

2500

367.0

367.0

35.0

LM2904DRG3

SOIC

D

8

2500

333.2

345.9

28.6

LM2904DRG3

SOIC

D

8

2500

364.0

364.0

27.0

LM2904DRG4

SOIC

D

8

2500

367.0

367.0

35.0

LM2904DRG4

SOIC

D

8

2500

340.5

338.1

20.6

LM2904PWR

TSSOP

PW

8

2000

364.0

364.0

27.0

LM2904PWR

TSSOP

PW

8

2000

367.0

367.0

35.0

LM2904PWRG3

TSSOP

PW

8

2000

364.0

364.0

27.0

LM2904PWRG4-JF

TSSOP

PW

8

2000

367.0

367.0

35.0

LM2904QDR

SOIC

D

8

2500

350.0

350.0

43.0

LM2904VQDR

SOIC

D

8

2500

340.5

338.1

20.6

LM2904VQPWR

TSSOP

PW

8

2000

367.0

367.0

35.0

LM2904VQPWRG4

TSSOP

PW

8

2000

367.0

367.0

35.0

LM358ADGKR

VSSOP

DGK

8

2500

364.0

364.0

27.0

LM358ADR

SOIC

D

8

2500

367.0

367.0

35.0

LM358ADR

SOIC

D

8

2500

333.2

345.9

28.6

LM358ADR

SOIC

D

8

2500

340.5

338.1

20.6

LM358ADR

SOIC

D

8

2500

364.0

364.0

27.0

LM358ADRG4

SOIC

D

8

2500

367.0

367.0

35.0

LM358ADRG4

SOIC

D

8

2500

340.5

338.1

20.6

LM358APWR

TSSOP

PW

8

2000

367.0

367.0

35.0

LM358APWR

TSSOP

PW

8

2000

364.0

364.0

27.0

LM358APWRG4

TSSOP

PW

8

2000

367.0

367.0

35.0

LM358BAIDR

SOIC

D

8

2500

340.5

338.1

20.6

LM358BIDR

SOIC

D

8

2500

340.5

338.1

20.6

LM358DGKR

VSSOP

DGK

8

2500

358.0

335.0

35.0

LM358DGKR

VSSOP

DGK

8

2500

364.0

364.0

27.0

LM358DR

SOIC

D

8

2500

364.0

364.0

27.0


Device

Package Type

Package Drawing

Pins

SPQ

Length (mm)

Width (mm)

Height (mm)

LM358DR

SOIC

D

8

2500

367.0

367.0

35.0

LM358DR

SOIC

D

8

2500

333.2

345.9

28.6

LM358DR

SOIC

D

8

2500

340.5

338.1

20.6

LM358DRG3

SOIC

D

8

2500

333.2

345.9

28.6

LM358DRG3

SOIC

D

8

2500

364.0

364.0

27.0

LM358DRG4

SOIC

D

8

2500

340.5

338.1

20.6

LM358DRG4

SOIC

D

8

2500

367.0

367.0

35.0

LM358PWR

TSSOP

PW

8

2000

364.0

364.0

27.0

LM358PWR

TSSOP

PW

8

2000

367.0

367.0

35.0

LM358PWRG3

TSSOP

PW

8

2000

364.0

364.0

27.0

LM358PWRG4

TSSOP

PW

8

2000

367.0

367.0

35.0

LM358PWRG4-JF

TSSOP

PW

8

2000

367.0

367.0

35.0

MECHANICAL DATA


FK ( S - CQCC - N * * ) LE ADLESS CERA M I C CH IP CARRIER

28 TERMINAL SHOWN



NO. OF TERMINALS

**

A

B

MIN

MAX

MIN

MAX


20

0.342

(8,69)

0.358

(9,09)

0.307

(7,80)

0.358

(9,09)


28

0.442

(11,23)

0.458

(11,63)

0.406

(10,31)

0.458

(11,63)


44

0640

(16,26)

0.660

(16,76)

0.495

(12,58)

0.560

(14,22)


52

0.740

(18,78)

0.761

(19,32)

0.495

(12,58)

0.560

(14,22)


68

0.938

(23,83)

0.962

(24,43)

0.850

(21,6)

0.858

(21,8)


84

1.1 41

(28,99)

1.165

(29,59)

1.047

(26,6)

1.063

(27,0)

18 1 7 16 15 1 4 13 12


(


B SO


A SO

19 11


20 10


21 9


22 8


23 7


24 6


25 5

\


26 27 28 2 3 4

0.020 (0,51) , I I 0.080 (2,03)

'T

---r

0.010 (0,25)- - I


0.020 (0,51)

0.010 (0,25)

0.06 4 (1,63)


0.055 (1,40)

0.045 (1,14)


0.028 (0,71)- -

0.022 (0,54)


----.I-


0.045 (1,14)

0.035 (0,89)


0 050 (1,27)

: 045 (1,14:

0.035 (0,89)


4040 1 40 /D 01 /11


NOTES: A. All linear dimensions are in inches (millimeters).

  1. This drawing is subject to change without notice.

  2. This package can be hermetically sealed with a metal lid.

  3. Falls wi thin JEDEC MS-004


.Ii:& TEY""

INS n UM EN-

www.ti.com


D0008A

PACKAGE OUTLINE

SOIC - 1.75 mm max height


SCALE 2.800


SMALL OUTLINE INTEGRATED CIRCUIT



C



A


.189-.197

[4.81-5.00]

NOTE 3


.228-.244 TYP

[5.80-6.19]

.050

[1.27]

PIN 1 ID AREA

6X


1 8


2X

.150

[3.81]

C

SEATING PLANE


.004 [0.1]



4


B .150-.157

[3.81-3.98]

NOTE 4


5

8X .012-.020


.010 [0.25]

C

A

B

[0.31-0.51]

4X (0 -15 )


  1. MAX

    [1.75]


    .005-.010 TYP

    [0.13-0.25]


    4X (0 -15 )


    SEE DETAIL A

    .010

    [0.25]


    0 - 8

    .004-.010

    [0.11-0.25]

    .016-.050

    [0.41-1.27]


    (.041)

    [1.04]


    DETAIL A

    TYPICAL


    4214825/C 02/2019

    NOTES:


    1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches. Dimensioning and tolerancing per ASME Y14.5M.

    2. This drawing is subject to change without notice.

    3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed .006 [0.15] per side.

    4. This dimension does not include interlead flash.

    5. Reference JEDEC registration MS-012, variation AA.


      D0008A

      EXAMPLE BOARD LAYOUT

      SOIC - 1.75 mm max height

      SMALL OUTLINE INTEGRATED CIRCUIT


      8X (.061 )

      [1.55]


      1


      8X (.024)

      [0.6]


      4

      6X (.050 )

      [1.27]


      SYMM


      (.213)

      [5.4]


      LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:8X


      SEE DETAILS


      8


      SYMM


      (R.002 ) TYP

      5 [0.05]


      METAL SOLDER MASK

      SOLDER MASK METAL UNDER

      OPENING

      OPENING

      SOLDER MASK



      EXPOSED METAL

      .0028 MAX

      [0.07]

      ALL AROUND


      EXPOSED

      METAL


      .0028 MIN

      [0.07]

      ALL AROUND


      NON SOLDER MASK DEFINED

      SOLDER MASK DEFINED


      SOLDER MASK DETAILS


      4214825/C 02/2019


      NOTES: (continued)


    6. Publication IPC-7351 may have alternate designs.

    7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.


      www.ti.com


      D0008A

      EXAMPLE STENCIL DESIGN

      SOIC - 1.75 mm max height

      SMALL OUTLINE INTEGRATED CIRCUIT


      8X (.061 )

      [1.55]


      1


      SYMM


      8


      8X (.024)

      [0.6]


      SYMM



      4

      6X (.050 )

      [1.27]


      (.213)

      [5.4]

      (R.002 ) TYP

      5 [0.05]


      SOLDER PASTE EXAMPLE

      BASED ON .005 INCH [0.125 MM] THICK STENCIL SCALE:8X


      4214825/C 02/2019


      NOTES: (continued)


    8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations.

    9. Board assembly site may have different recommendations for stencil design.


MECHANICAL DATA

7,40


ge Pld J

_J

l0!!}

5,00

5,60 8,20

R7l

PS (R-PDSO-G8) PLASTIC SMALL-OUTLINE PACKAGE


hI, i:;; l , lo 2s@I



0,15

0 05


Seating Plane


- 2,00 MAX

0010


4040063/C 03/03

t

- '

\

I I

I I

I I

I I

.-----

0,95

+- 0,55

--+

o·-B·

5,90

NOTES: A. All linear dimensions ore in millimeters.

  1. This drawing is subject to change without notice.

  2. Body dimensions do not include mold flash or protrusion, not to exceed 0,15.


    "li>TEXAS INSTRUMENTS

    www.ti.com

    LAN D PATTERN DATA


    ------- l

    ,--- -) ---- _l

    I : ', -- ,/

    //--,_

    6 x1,27

    17,40

    r - s , xo 55

    -I ---1 --1

    Stencil Open ings

    7- (Note D)

    L

    r Rxl,

    Example Board Layout (Note C)

    7 r - 6x1,27

    ------7

    7,40

    PS (R-PDSO-G8) PLASTIC SM AL L OU TLI NE


    Example


    1,80


    \

    - -1

    -

    0,07

    I


    - ---,,, _

    /,

    /



    4212 188/ A 09/11


    Around /

    All

    \

    I:

    L

    Example

    Non-Solder Mask Opening (See Note E)

    ' \

    /,

    I

    \

    -

    ',

    Example Pad Geometry (See Note C)

    -,

    ',,,

    '

    0,60

    /

    // 1

    ' 1

    t, , /

    Non Soldermask Defined Pad

    , :- ------ --- --------"-

    NOTES: A. All linear dimensions are in millimeters.

    1. This drawing is subjec t to change without not ice.

    2. Publi cation IPC- 7351 is recommended for alternate designs.

    3. Laser cutting apertures with trapezoidal walls and also rounding corners will offer better paste release. Custome rs should contact their board assembly site for stencil design recommendations. Re fer to IPC- 7525 for other stencil recommenda tions.

    4. Customers should contact their board fabrica tion site for solder mask tolerances between and around signal pads.



T XA"'

I' S-T


MENS

www.ti.cor,

MECHANICALDATA


MCER001A – JANUARY 1995 – REVISED JANUARY 1997


JG (R-GDIP-T8) CERAMIC DUAL-IN-LINE


0.400 (10,16)

0.355 (9,00)


8 5


0.280 (7,11)

0.245 (6,22)


1 4

0.065 (1,65)

0.045 (1,14)


0.063 (1,60)

0.015 (0,38)


0.020 (0,51) MIN


0.200 (5,08) MAX


0.130 (3,30) MIN


Seating Plane

0.310 (7,87)

0.290 (7,37)







0.023 (0,58)

0.015 (0,38)

0.100 (2,54)


0.014 (0,36)

0.008 (0,20)


0–15


4040107/C 08/96


NOTES: A. All linear dimensions are in inches (millimeters).

  1. This drawing is subject to change without notice.

  2. This package can be hermetically sealed with a ceramic lid using glass frit.

  3. Index point is provided on cap for terminal identification.

  4. Falls within MIL STD 1835 GDIP1-T8


POST OFFICE BOX 655303 DALLAS, TEXAS 75265


0.045 (1,1 4)

i

i

P (R-PDIP-T8) PL AS TIC DUAL-IN-LINE PACKAGE



0.400 (10,16)

+- 0.355 (9,02) .

8 5


0.260 (6,60)

0.240 (6,10)


0


L007: (1. 78)



0.045 (1,1 4)

0.030 (0,76)

0.020 (0,51) MIN

0.325 (8,26)

._ 0.300 (7,62) _.


0.021 (0,53)

._ 0.015 (0,38)

!410 010 (0,25)@



4040082/ E 04/ 2010


MAX

I

k-0.430 (10,92)

0.010 (0,25) NOM

Gauge Plane

-f

0.200 (5,08) MAX

t

y_ i Sea ting Plane

t 0.125 (3,18) MIN

t

0 100 (2,54) 1

NOTES: A. All linear dimensions are in inches (mi llimeters) .

  1. This drawing is subject to change without notice.

  2. Falls wit hin JEDEC MS-001 variation BA.


.., A

MECHANICAL DATA


0,328

DGK (S-PDSO-GB) PLASTIC SMALL-OUTLINE PACKAGE


r- 1 ls5

0, 5

-$- 0,13 @


0,23

0,13

5,05

4,75


\


0,70

0,40


t,

j

Seating Plane


4073329/E 05/06


10,1

0,05

'

NOTES: A. All linear dimensions ore in millimeters.

B. This drawing is subject to change wi thout notice.

Body length does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 per end.

[Q:> Body width does not include interleod flash. lnter leod flash shall not exceed 0.50 per side.

E. Falls within JEDEC M0-187 variation A/\ except inter leod flash.


.. I\


www.ti.com


,l

'

', i

f

J_

)


1

DGK (S-PDSO-G8) PLASTIC SMALL OUTLINE PACKAGE


Example Board Layout

Example Stencil Openings Based on a stencil thickness

of .127mm (.005inch).

(See Note D)


H(0,65)TYP. 8X(0,457)

j-

H(0,65)TYP.



8


5

--------r

8X(1,45

------!


PKG-------t-------

1

I'

(4,4)

PKG-------+-------

(4,4)

/

/

1

4

_l

_l


I

I



4221236/A 11/13

/

,,,,,.

"'-- /

',

I

/

--11-- (0,05)

All Around I

I

\

I

I

Pad Geometry

(See Note C)

\

I

(1,45)

l

\

Example Solder Mask Opening

(See Note E)


I I

' ,

- I I - (0,45) \

t

I

I

I

I

I

Example

, Non Soldermask Defined Pad


I --------

y -l [

/

PKG

G

I ,, "---- --./ Pi

NOTES: A. All linear dimensions are in millimeters.

  1. This drawing is subject to change without notice.

  2. Publication IPC-7351 is recommended for alternate designs.

  3. Laser cutting apertures with trapezoidal walls and also rounding corners will offer better paste release. Customers should contact their board assembly site for stencil design recommendations. Refer to IPC-7525 for other stencil recommendations.

  4. Customers should contact their board fabrication site for solder mask tolerances between and around signal pads.


TEXAS

IN STRUMEN


PW0008A

PACKAGE OUTLINE

TSSOP - 1.2 mm max height


SCALE 2.800


SMALL OUTLINE PACKAGE



A


3.1

2.9

NOTE 3


6.6

TYP

6.2

PIN 1 ID AREA


1 8


C

6X


0.65

2X

1.95


C

SEATING PLANE


0.1


4


B

4.5

4.3

NOTE 4


5

8X

0.30


0.1

C

A

B

0.19


1.2 MAX



SEE DETAIL A


(0.15) TYP


0.25

GAGE PLANE



0 - 8

0.75

0.50


DETAIL A

TYPICAL

0.15

0.05


4221848/A 02/2015

NOTES:


  1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M.

  2. This drawing is subject to change without notice.

  3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side.

  4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.

  5. Reference JEDEC registration MO-153, variation AA.


    PW0008A

    EXAMPLE BOARD LAYOUT

    TSSOP - 1.2 mm max height

    (R0.05) TYP

    1

    SMALL OUTLINE PACKAGE



    8X (0.45)

    8X (1.5)

    SYMM


    8


    SYMM



    6X (0.65)

    4

    5



    (5.8)


    LAND PATTERN EXAMPLE

    SCALE:10X


    SOLDER MASK OPENING

    METAL

    METAL UNDER SOLDER MASK

    SOLDER MASK OPENING


    0.05 MAX ALL AROUND

    0.05 MIN

    ALL AROUND


    NON SOLDER MASK DEFINED

    SOLDER MASK DEFINED


    SOLDER MASK DETAILS

    NOT TO SCALE


    4221848/A 02/2015

    NOTES: (continued)


  6. Publication IPC-7351 may have alternate designs.

  7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.



    www.ti.com


    PW0008A

    EXAMPLE STENCIL DESIGN

    TSSOP - 1.2 mm max height

    1

    SMALL OUTLINE PACKAGE


    8X (0.45)

    8X (1.5)

    SYMM

    (R0.05) TYP


    8


    SYMM



    6X (0.65)

    4

    5


    (5.8)


    SOLDER PASTE EXAMPLE

    BASED ON 0.125 mm THICK STENCIL SCALE:10X


    4221848/A 02/2015

    NOTES: (continued)


  8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations.

  9. Board assembly site may have different recommendations for stencil design.

IMPORTANT NOTICE AND DISCLAIMER


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