19-1424; Rev 0; 1/99


Low-Voltage, High-Isolation, Dual 2-Channel RF/Video Multiplexer

MAX4589

General Description Features

The MAX4589 low-voltage, dual 2-channel multiplexer is designed for RF and video signal processing at frequen- cies up to 200MHz in 50 and 75 systems. On-chip functions are controlled through either a parallel interface or an SPI™/QSPI™/MICROWIRE™ serial interface.

Each channel of the MAX4589 is designed using a “T” switch configuration, ensuring excellent high-frequency off-isolation. The MAX4589 has low on-resistance of 60 max, with an on-resistance match across all chan- nels of 4 max. Additionally, on-resistance is flat across the specified signal range (2 max). The off- leakage current is under 1nA at TA = +25°C, and less than 10nA at TA = +85°C.

The MAX4589 operates from single +2.7V to +12V or dual ±2.7V to ±6V supplies. When operating with a positive supply of +5V, the inputs maintain TTL/CMOS- level compatibility. The MAX4589 is available in 20-pin DIP, wide SO, and SSOP packages.


Applications

RF Switching

Video Signal Routing

High-Speed Data Acquisition Automatic Test Equipment Networking

MAX4589

PART

TEMP. RANGE

PIN-PACKAGE

MAX4589CAP

0°C to

+70°C

20 SSOP

MAX4589CWP

0°C to

+70°C

20 Wide SO

MAX4589CPP

0°C to

+70°C

20 Plastic DIP

MAX4589EAP

-40°C to

+85°C

20 SSOP

MAX4589EWP

-40°C to

+85°C

20 Wide SO

MAX4589EPP

-40°C to

+85°C

20 Plastic DIP

Pin Configuration Ordering Information


TOPVIEW

GND 1

20 SER/PAR


COM1 2

V+ 3

NO1 4

GND 5

NO2 6

2/4 7

RS 8

LE/CS 9

A1/SCLK 10

19 COM2

18 V-

17 NO3

16 GND

15 NO4

14 VL

13 DIN

CONTROLLOGIC

12 EN

11 A0/DOUT

SSOP/SO/DIP

SPI and QSPI are trademarks of Motorola, Inc.

MICROWIRE is a trademark of National Semiconductor Corp. Rail-to-Rail is a registered trademark of Nippon Motorola, Ltd.



Maxim Integrated Products 1

For free samples & the latest literature: http://www.maxim-ic.com, or phone 1-800-998-8800. For small orders, phone 1-800-835-8769.


MAX4589

ABSOLUTE MAXIMUM RATINGS

(Voltages referenced to GND)

V+ ...........................................................................-0.3V to +13V

VL ......................-0.3V to (V+ + 0.3V) or 7V (whichever is lower) V- ...........................................................................-13V to +0.3V

V+ to V-...................................................................-0.3V to +13V VNO_, VCOM_ to GND (Note 1)..............(V- - 0.3V) to (V+ + 0.3V) 2/4, RS, LE, CS, A1/SCLK,

A0/DOUT, EN, DIN, SER/PAR to GND ......-0.3V to (V+ + 0.3V)

Continuous Current into Any Terminal..............................±20mA Peak Current into Any Terminal

(pulsed at 1ms, 10% duty cycle)...................................±40mA


ESD per Method 3015.7.......................................................±2kV

Continuous Power Dissipation (TA = +70°C)

SSOP (derate 9.1mW/°C above +70°C)............................727mW

Wide SO (derate 10mW/°C above +70°C)........................800mW

Plastic DIP (derate 11.1mW/°C above +70°C) .................889mW Operating Temperature Ranges

MAX4589C_ P ......................................................0°C to +70°C

MAX4589E_ P ...................................................-40°C to +85°C

Storage Temperature Range .............................-65°C to +150°C

Lead Temperature (soldering, 10sec) .............................+300°C


Note 1: Voltages on these pins exceeding V+ or V- are clamped by internal diodes. Limit forward diode current to maximum current rating.


Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.


ELECTRICAL CHARACTERISTICS—Dual Supplies

±

±

(V+ = VL = +4.5V to +5.5V, V- = -4.5V to -5.5V, VINH = +2.4V, VINL = +0.8V, TA = TMIN to TMAX, unless otherwise noted. Typical val- ues are at TA = +25°C, V+ = VL = +5V, V- = -5V.) (Note 2)

PARAMETER

SYMBOL

CONDITIONS

TA

MIN

TYP

MAX

UNITS

ANALOG SWITCH

Analog Signal Range (Note 3)

VCOM_, VNO_



V-


V+

V

On-Resistance

RON

V+ = 5V, V- = -5V,

VNO_ = ±2V, ICOM_ = 4mA

+25°C


40

60

C, E

75

On-Resistance Match Between Channels (Note 4)

RON

V+ = 5V, V- = 5V,

VNO_ = ±2V, ICOM_ = 4mA

+25°C


1

4

C, E

5


On-Resistance Flatness (Note 5)


RFLAT(ON)

V+ = 5V; V- = -5V; VNO_= 1V, 0, -1V; ICOM_ = 4mA

+25°C


0.5

2.5


C, E

3


NO_ Off-Leakage Current (Note 6)


INO_ (OFF)

V+ = 5.5V, V- = -5.5V, VCOM_ = ±4.5V, VNO_ = 4.5V

+25°C

-1

0.01

1


nA

C, E

-10


10


COM_ Off-Leakage Current (Note 6)


ICOM_ (OFF)

V+ = 5.5V, V- = -5.5V, VCOM_ = ±4.5V, VNO_ = 4.5V

+25°C

-2

0.01

2


nA

C, E

-20


20


COM_ On-Leakage Current (Note 6)


ICOM_ (ON)

V+ = 5.5V, V- = -5.5V, VCOM_ = ±4.5V,

VNO_ = floating

+25°C

-2

0.01

2


nA

C, E

-20


20

LOGIC INPUTS (2/4, RS, LE/CS, A1/SCLK, AO/DOUT, EN, DIN, SER/PAR)

Input Logic Threshold High

VINH


C, E

2.4

1.7


V

Input Logic Threshold Low

VINL


C, E


1.5

0.8

V

Input Threshold Hysteresis




0.2

V

Input Current

IIN

VIN_ = 0 or VL

C, E

-1

0.03

1

µA


MAX4589

ELECTRICAL CHARACTERISTICS—Dual Supplies (continued)

(V+ = VL = +4.5V to +5.5V, V- = -4.5V to -5.5V, VINH = +2.4V, VINL = +0.8V, TA = TMIN to TMAX, unless otherwise noted. Typical val- ues are at TA = +25°C, V+ = VL = +5V, V- = -5V.) (Note 2)


PARAMETER

SYMBOL

CONDITIONS

TA

MIN TYP MAX

UNITS

LOGIC OUTPUT (SERIAL INTERFACE)

DOUT Logic Low Output

VOL

ISINK = 3.2mA

C, E

0.4

V

DOUT Logic High Output

VOH

ISOURCE = -1mA

C, E

VL - 1

V

SWITCH DYNAMIC CHARACTERISTICS

Turn-On Time

tON

VNO_ = 3V, V+ = 4.5V,

V- = -4.5V, Figure 1

+25°C

380 550

ns

C, E

600

Turn-Off Time

tOFF

VNO_ = 3V, V+ = 4.5V,

V- = -4.5V, Figure 1

+25°C

150 300

ns

C, E

350

Break-Before-Make Time Delay (Note 3)

tBBM

VNO_ = 3V, V+ = 5.5V,

V- = -5.5V, Figure 2

C, E

10 180

ns

Charge Injection

Q

CL = 1.0nF, VNO_ = 0,

RS = 0, Figure 3

+25°C

15

pC

NO_ Off-Capacitance

CNO_(OFF)

VNO_ = 0, fIN = 1MHz, Figure 4

+25°C

2

pF

COM_ Off-Capacitance

CCOM_(OFF)

VCOM_ = 0, fIN = 1MHz, Figure 4

+25°C

4

pF

COM_ On-Capacitance

CCOM_(ON)

VCOM_ = 0, fIN = 1MHz, Figure 4

+25°C

6

pF

Off-Isolation (Note 7)

VISO

VNO_ = 1VRMS, f = 10MHz,

all channels off, Figure 5

+25°C

-74

dB

Channel-to-Channel Crosstalk

VCT

VNO_ = 1VRMS, f = 10MHz,

Figure 5

+25°C

-70

dB

-3dB Bandwidth

BW

Figure 5

2-channel mode

+25°C

200

MHz

4-channel mode

150

-0.1dB Bandwidth

BW

Figure 5

2-channel mode

+25°C

20

MHz

4-channel mode

15

PARALLEL-INTERFACE TIMING

A_, EN to LE Rise Setup Time

tDS

Figure 6

C, E

80

ns

A_, EN to LE Rise Hold Time

tDH

Figure 6

C, E

0

ns

LE Low Pulse Width

tL

Figure 6

C, E

80

ns

RS Low Pulse Width

tRS

Figure 6

C, E

80

ns

SERIAL-INTERFACE TIMING

Operating Frequency

fCLK

Figure 7

C, E

6.25

MHz

SCLK Pulse Width High

tCH

Figure 7

C, E

80

ns

SCLK Pulse Width Low

tCL

Figure 7

C, E

80

ns

DIN to SCLK Rise Setup Time

tDS

Figure 7

C, E

60

ns

DIN to SCLK Rise Hold Time

tDH

Figure 7

C, E

0

ns


MAX4589

ELECTRICAL CHARACTERISTICS—Dual Supplies (continued)

(V+ = VL = +4.5V to +5.5V, V- = -4.5V to -5.5V, VINH = +2.4V, VINL = +0.8V, TA = TMIN to TMAX, unless otherwise noted. Typical val- ues are at TA = +25°C, V+ = VL = +5V, V- = -5V.) (Note 2)


PARAMETER

SYMBOL

CONDITIONS

TA

MIN

TYP

MAX

UNITS

CS Fall to SCLK Rise Setup Time

tCSS0

Figure 7

C, E

50

ns

CS Fall to SCLK Rise Hold Time

tCSS1

Figure 7

C, E

80

ns

CS Rise to SCLK Rise Hold Time

tCSH1

Figure 7

C, E

0

ns

CS Rise to SCLK Rise Setup Time

tCSS1

Figure 7

C, E

80

ns

SCLK Rise to DOUT Valid

tDO

CL = 50pF, Figure 7

C, E

150

ns

RS Low Pulse Width

tRS

Figure 6

C, E

80

ns

POWER SUPPLY

Power-Supply Range

V+, V-



±2.7


±6

V

VL



+2.7


V+

V+ Supply Current

I+

V- = -5.5V, V+ = 5.5V

+25°C

-1

0.0001

1

µA

C, E

-10


10

V- Supply Current

I-

V- = -5.5V, V+ = 5.5V

+25°C

-1

0.0001

1

µA

C, E

-10


10

VL Supply Current

IL

VL = 5.5V, all VIN_= 0 or VL

C, E

-10

2

10

µA


ELECTRICAL CHARACTERISTICS—Single +5V Supply

(V+ = VL = +4.5V to +5.5V, V- = 0, VINH = +2.4V, VINL = +0.8V, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA

= +25°C, V+ = VL = +5V.) (Note 2)


PARAMETER

SYMBOL

CONDITIONS

TA

MIN

TYP

MAX

UNITS

ANALOG SWITCH

Analog Signal Range (Note 3)

VCOM_, VNO



0


V+

V

On-Resistance

RON

V+ = 5V, VNO_ = 3V, ICOM_ = 4mA

+25°C


80

120

C, E

150

On-Resistance Match Between Channels (Note 4)

RON

V+ = 5V, VNO_ = 3V, ICOM_ = 4mA

+25°C


1

8

C, E

10

On-Resistance Flatness (Note 5)

RFLAT(ON)

V+ = 5V; ICOM_ = 4mA; VNO_ = 2V, 3V, 4V

+25°C


4

10

C, E

12

NO_ Off-Leakage Current (Notes 6, 8)

INO_ (OFF)

V+ = 5.5V; VCOM_ = 4.5V, 1V; VNO_ = 1V, 4.5V

+25°C

-1

0.005

1

nA

C, E

-10


10

COM_ Off-Leakage Current (Notes 6, 8)

ICOM_ (OFF)

V+ = 5.5V; VCOM_ = 4.5V, 1V; VNO_ = 1V, 4.5V

+25°C

-2

0.005

2

nA

C, E

-20


20

COM_ On-Leakage Current (Notes 6, 8)

ICOM_ (ON)

V+ = 5.5V; VCOM_ = 4.5V 1V;

VNO_ = 4.5V, 1V, or floating

+25°C

-2

0.005

2

nA

C, E

-20


20


MAX4589

ELECTRICAL CHARACTERISTICS—Single +5V Supply (continued)

(V+ = VL = +4.5V to +5.5V, V- = 0, VINH = +2.4V, VINL = +0.8V, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA

= +25°C, V+ = VL = +5V.) (Note 2)


PARAMETER

SYMBOL

CONDITIONS

TA

MIN TYP MAX

UNITS

LOGIC INPUTS (2/4, RS, LE/CS, A1/SCLK, AO/DOUT, EN, DIN, SER/PAR

Input Logic Threshold High

VINH


C, E

2.4 1.7

V

Input Logic Threshold Low

VINL


C, E

1.5 0.8

V

Input Threshold Hysteresis




0.2

V

Input Current

IIN

VIN = 0 or VL

C, E

-1 1

µA

LOGIC OUTPUT (SERIAL INTERFACE)

DOUT Logic Low Output

VOL

ISINK = 3.2mA

C, E

0.4

V

DOUT Logic High Output

VOH

ISOURCE = -1mA

C, E

VL - 1

V

SWITCH DYNAMIC CHARACTERISTICS

Turn-On Time

tON

VNO = 3V, V+ = 4.5V,

Figure 1

+25°C

550 800

ns

C, E

900

Turn-Off Time

tOFF

VNO = 3V, V+ = 4.5V,

Figure 1

+25°C

150 300

ns

C, E

350

Break-Before-Make Time Delay (Note 3)

tBBM

VNO = 3V, V+ = 5.5V,

Figure 2

C, E

10 200

ns

Charge Injection

Q

CL = 1.0nF, VNO_ = 2.5V,

RS = 0, Figure 3

+25°C

5

pC

Off-Isolation

VISO

VNO_ = 1VRMS, f = 10MHz,

all channels off, Figure 5

+25°C

-65

dB

Channel-to-Channel Crosstalk

VCT

VNO_ = 1VRMS, f = 10MHz,

Figure 5

+25°C

-70

dB

-3dB Bandwidth

BW

Figure 5

2-channel mode

+25°C

100

MHz

4-channel mode

75

-0.1dB Bandwidth

BW

Figure 5

2-channel mode

+25°C

10

MHz

4-channel mode

7

PARALLEL-INTERFACE TIMING

A_, EN to LE Rise Setup Time

tDS

Figure 6

C, E

80

ns

A_, EN to LE Rise Hold Time

tDH

Figure 6

C, E

0

ns

LE Low Pulse Width

tL

Figure 6

C, E

80

ns

RS Low Pulse Width

tRS

Figure 6

C, E

80

ns


MAX4589

ELECTRICAL CHARACTERISTICS—Single +5V Supply (continued)

(V+ = VL = +4.5V to +5.5V, V- = 0, VINH = +2.4V, VINL = +0.8V, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA

= +25°C, V+ = VL = +5V.) (Note 2)

PARAMETER

SYMBOL

CONDITIONS

TA

MIN

TYP

MAX

UNITS

SERIAL-INTERFACE TIMING

Operating Frequency

fCLK

Figure 7

C, E

6.25

ns

SCLK Pulse Width High

tCH

Figure 7

C, E

80

ns

SCLK Pulse Width Low

tCL

Figure 7

C, E

80

ns

DIN to SCLK Rise Setup Time

tDS

Figure 7

C, E

60

ns

DIN to SCLK Rise Hold Time

tDH

Figure 7

C, E

0

ns

CS Fall to SCLK Rise Setup Time

tCSS0

Figure 7

C, E

50

ns

CS Rise to SCLK Rise Hold Time

tCSH1

Figure 7

C, E

0

ns

CS Rise to SCLK Rise Setup Time

tCSS1

Figure 7

C, E

80

ns

CS Fall to SCLK Rise Hold Time

tCSS1

Figure 7

C, E

80

ns

SCLK Rise to DOUT Valid

tDO

CL = 50pF, Figure 7

C, E

150

ns

RS Low Pulse Width

tRS

Figure 6

C, E

80

ns

POWER SUPPLY


Power-Supply Range

V+



2.7


12

V

VL

V+ 6.5V


2.7 V+

V

V+ > 6.5V


2.7


6.5

V+ Supply Current

I+

V+= 5.5V, VIN = 0 or VL

+25°C

-1


1

µA

C, E

-10


10

VL Supply Current

IL

VL = 5.5V, all VIN_ = 0 or VL

C, E

-10

2

10

µA


ELECTRICAL CHARACTERISTICS—Single +3V Supply

(V+ = VL = +2.7V to +3.6V, V- = 0, VINH = +2V, VINL = +0.5V, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA =

+25°C, V+ = VL = +3V.)

PARAMETER

SYMBOL

CONDITIONS

TA

MIN TYP MAX

UNITS

ANALOG SWITCH

Analog Signal Range (Note 3)

VCOM_,VNO



0 V+

V

On-Resistance

RON

V+ = 2.7V, VNO_ = 1V, ICOM_ = 1mA

+25°C

240 350

C, E

450

LOGIC INPUT (2/4, RS, LE/CS, A1/SCLK, AO/DOUT, EN, DIN, SER/PAR

Input Logic Threshold High

VINH


C, E

2.0

V

Input Logic Threshold Low

VINL


C, E

0.5

V

Input Current

IIN

VIN_ = 0 or VL

C, E

-1 1

µA

SWITCH DYNAMIC CHARACTERISTICS µA

Turn-On Time

tON

VNO = 1.5V, V+ = 2.7V,

Figure 1

+25°C

700 1000

ns

C, E

1200

Turn-Off Time

tOFF

VNO = 1.5V, V+ = 2.7V,

Figure 1

+25°C

250 400

ns

C, E

500

Break-Before-Make Time Delay (Note 3)

tBBM

VNO = 1.5V, V+ = 3.6V,

Figure 2

C, E

10 350

ns


MAX4589

ELECTRICAL CHARACTERISTICS—Single +3V Supply (continued)

(V+ = VL = +2.7V to +3.6V, V- = 0, VINH = +2V, VINL = +0.5V, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA =

+25°C, V+ = VL = +3V.)


PARAMETER

SYMBOL

CONDITIONS

TA

MIN TYP MAX

UNITS

PARALLEL-INTERFACE TIMING

A_, EN to LE Rise Setup Time

tDS

Figure 6

C, E

200

ns

A_, EN to LE Rise Hold Time

tDH

Figure 6

C, E

0

ns

LE Low Pulse Width

tL

Figure 6

C, E

200

ns

RS Low Pulse Width

tRS

Figure 6

C, E

80

ns

SERIAL-INTERFACE TIMING

Operating Frequency

fCLK

Figure 7

C, E

2.1

MHz

SCLK Pulse Width High

tCH

Figure 7

C, E

200

ns

SCLK Pulse Width Low

tCL

Figure 7

C, E

200

ns

DIN to SCLK Rise Setup Time

tDS

Figure 7

C, E

100

ns

DIN to SCLK Rise Hold Time

tDH

Figure 7

C, E

0

ns

CS Fall to SCLK Rise Setup Time

tCSS0

Figure 7

C, E

100

ns

CS Rise to SCLK Rise Hold Time

tCSH1

Figure 7

C, E

0

ns

CS Rise to SCLK Rise Setup Time

tCSS1

Figure 7

C, E

200

ns

CS Fall to SCLK Rise Hold Time

tCSS1

Figure 7

C, E

200

ns

SCLK Rise to DOUT Valid

tDO

CL = 50pF, Figure 7

C, E

250

ns

RS Low Pulse Width

tRS

Figure 6

C, E

80

ns

POWER SUPPLY

V+ Supply Current

I+

V+ = 3.6V, VIN = 0 or VL

+25°C

-1 1

µA

C, E

-10 10

VL Supply Current

IL

VL = 3.6V, all VIN = 0 or VL

C, E

-10 1 10

µA

Note 2: The algebraic convention is used in this data sheet; the most negative value is shown in the minimum column.

Note 3: Guaranteed by design.

Note 4: RON = RON(MAX) - RON(MIN).

Note 5: Resistance flatness is defined as the difference between the maximum and the minimum value of on-resistance as measured over the specified analog-signal range.

Note 6: Leakage parameters are 100% tested at maximum rated hot temperature and guaranteed by correlation at TA = +25°C.

Note 7: Off-isolation = 20log10 [VCOM_ / VNO_], VCOM_ = output, VNO_ = input to off switch.

Note 8: Leakage testing for single-supply operation is guaranteed by testing with dual supplies.


MAX4589

Typical Operating Characteristics

(V+ = VL = +5V, V- = -5V, TA = +25°C, unless otherwise specified.)



100

90

80

70

RON()

60

50

40

30

20

ON-RESISTANCE vs. VCOM (DUALSUPPLIES)


V±=±2.5V


V±=±3V


V±=±4V V±=±5V


250


MAX4589toc01

200


RON()

150


100


50

ON-RESISTANCE vs. VCOM (SINGLESUPPLY)


V-=0

V

V

+=+2.5


V+=+3.0V


V+=+3.6V

V+=+5V

V+=+9V

ON-RESISTANCE vs. VCOM AND TEMPERATURE (DUALSUPPLIES)

MAX4589toc02

MAX4589toc03















TA=+85°C











TA=+25°C




























TA= -40°C

















55


50


45


RON()

40


35


30


10

0

-5 -4


-3 -2 -1


0 1 2 3 4 5

V+=+12V


0

0 2 4 6 8 10 12

25


20

-5 -4


-3 -2 -1 0 1 2


3 4 5

VCOM (V)

VCOM (V)

VCOM (V)



120


100


RON()

80


60


40


20

ON-RESISTANCE vs. VCOM AND TEMPERATURE (SINGLESUPPLY)


TA=+85°C


TA=+25°C TA= -40°C


100


MAX4589toc04

LEAKAGECURRENT(pA)

10

ON/OFF-LEAKAGECURRENT vs. TEMPERATURE


ON-LEAKAGE


OFF-LEAKAGE

CHARGE INJECTION vs. VCOM

MAX4589toc05

MAX4589toc06































DUALSUPPLIES































SINGLESUPPLY











35


CHARGEINJECTION(pC)

30


25


20


15


10


5


0

0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0


1

-40


-20 0


20 40 60 80


0

-5 -4


-3 -2 -1 0


1 2 3 4 5


600


500


TIME(ns)

400


300


200


100


0

VCOM (V)


tON, tOFFvs. SUPPLY VOLTAGE


MAX4589toc07

















tON












tOFF








450

400


350

TIME(ns)

300


250

200

150


100

50

0

TEMPERATURE(°C)


tON, tOFFvs. TEMPERATURE


MAX4589toc08











tON





























tOFF
























10

1


100n


CURRENT(A)

10n 1n 100p

10p

1p 0.1p

VCOM (V)

MAX4589toc09

POWER-SUPPLY CURRENT vs. TEMPERATURE




















IL






















I+, I-
























2.0

2.5

3.0 3.5

4.0 4.5 5.0

-40 -20 0 20 40 60 80

-40 -20 0 20 40 60 80

DUALSUPPLYVOLTAGE(±V)

TEMPERATURE(°C)

TEMPERATURE(°C)


MAX4589

Typical Operating Characteristics (continued)

(V+ = VL = +5V, V- = -5V, TA = +25°C, unless otherwise specified.)



10

0

-10

AMPLITUDE(dB)

-20

-30

-40

-50

-60

-70

-80

-90

INSERTIONLOSS, OFF-ISOLATION, ANDCROSSTALK vs. FREQUENCY

(DUALSUPPLIES)


MAX4589toc11






ONLOSS








RS=75




RL=600













OFF-ISOLATION

CROSSTALK







10

0

-10

AMPLITUDE(dB)

-20

-30

-40

-50

-60

-70

-80

-90

INSERTIONLOSS, OFF-ISOLATION, ANDCROSSTALK vs. FREQUENCY

MAX4589toc12

(SINGLESUPPLY)







INSERTIONLOSS


RS=75 RL=600















CROSSTALK








OFF-ISOLATION





100k 1M 10M 100M 1G FREQUENCY(Hz)

100k 1M 10M 100M 1G FREQUENCY(MHz)


MAX4589

Pin Description


PIN

NAME

FUNCTION

1, 5, 16

GND

Ground. Connect to ground plane. See Grounding section.

2

COM1

Analog Switch Common Terminal. See Truth Tables.

3

V+

Analog Positive Supply Voltage Input

4

NO1

Normally Open Analog Input Terminal. See Truth Tables.

6

NO2

Normally Open Analog Input Terminal. See Truth Tables.

7

2/4

Multiplexer Configuration Control. Connect to VL to select dual 2-channel mode. Connect to GND for single 4-channel multiplexer operation. See Truth Tables.


8


RS

Active-Low Reset Input. In serial mode, drive RS low to force the latches and shift registers to the power-on reset state and force all switches open. In parallel mode, drive RS low to force the latches to the power-on reset state and force switches open. See Truth Tables.

9

LE/CS

In parallel mode this pin is the transparent Latch Enable. In the serial mode, this pin is the Chip-Select input. See Truth Tables.

10

A1/SCLK

In parallel mode, A1/SCLK is the most significant address bit. If 2/4 is high, A1/SCLK is ignored. In the serial mode, A1/SCLK is the serial shift clock input. Data is loaded on the rising edge of SCLK. See Truth Tables.


11


A0/DOUT

In parallel mode, this pin is the least significant address bit. In serial mode, DOUT is the output from the internal 4-bit shift register. DOUT is intended for daisy-chain cascading. DOUT is not three-stated by CS. See Serial Operation.

12

EN

Switch Enable. Drive EN low to force all channels off. Drive high to allow normal multiplexer operation. Operates asynchronously in serial mode. In parallel mode, EN is latched when the LE signal is high.

13

DIN

Serial Data Input. In serial mode, data is loaded on the rising edge of SCLK. Connect to VL or GND in parallel mode.

14

VL

Logic Supply Input. Powers the DOUT driver and other digital circuitry. VL sets both the input threshold levels and the output logic levels.

15

NO4

Normally Open Analog Input Terminal. See Truth Tables.

17

NO3

Normally Open Analog Input Terminal. See Truth Tables.

18

V-

Analog Negative Supply Voltage Input. Connect to GND for single-supply operation.

19

COM2

Analog Switch Common Terminal. See Truth Tables.

20

SER/PAR

Interface Select Input. Drive low for parallel data interface operation. Drive high for serial data interface operation and to enable the DOUT driver.


LE/CS

V+



V-

GND

tOFF

tON


V-

SWITCHISTIMEDFROM50% LEVELOFDIGITALSIGNAL.

VOUT

30pF

300

90%

90%

VOUT

COM_

EN

MAX4589

EN

VNO_

50%

50%

NO_

V+

MAX4589

Figure 1. Turn-On/Turn-Off Time


V+


LE/CS V+ SER/PAR

NO_

NO_

A0


VNO_

MAX4589

VOUT

90%

90%


A0

COM_

300


V-


EN

10F

1nF

tBBM

GND

V-

GND

VOUT

30pF

Figure 2. Break-Before-Make Time Delay


V+


LE/CS

SER/PAR

V+ NO_

VNO_



MAX4589


EN

COM_

VOUT

VOUT


V-

GND

Q= VOUT· CL


V-

VOUTISTHEMEASUREDVOLTAGEDUETOCHARGETRANSFER ERRORQWHENTHECHANNELTURNSOFF.


VOUT

CL

Figure 3. Charge Injection


V-

V-


+

-

V-

GND

1MHz CAPACITANCE ANALYZER

V-

GND

FLOATING

COM_

1MHz CAPACITANCE ANALYZER


COM_

GND

MAX4589

MAX4589

V+ NO_

FLOATING

V+ NO_

V+

V+

MAX4589

Figure 4. NO_, COM_ Capacitance



V+


V+


NO_

MAX4589

49.9

56

50


NO_

24.9

MEASURE NODE



V-

COM_

560

MEASURE NODE



ALLSIGNALSNORMALIZEDTOVCOM=0dB.

.


50

V-

50

Figure 5. Off-Isolation, Crosstalk, and Bandwidth



tL


LE


tDS

tDH



A0,A1,EN

MAX4589


tRS


RS

NOTE:ALL INPUTSIGNALSARESPECIFIEDWITHRtAND tF<10ns. TIMINGISMEASUREDFROM50%OFDIGITALSIGNAL.


Figure 6. Parallel Timing Diagram


CS

tCSS

tCH

tCL

tCSH

MAX4589


DIN

A0

A1

BIT3

DISABLE


tDO


DOUT



NOTE:ALL INPUTSIGNALSARESPECIFIEDWITHRtAND tF<10ns. TIMINGISMEASUREDFROM50%OFDIGITALSIGNAL.


tDH

tDS

SCLK

MAX4589

Figure 7. Serial Timing Diagram


Detailed Description

Logic-Level Translators The MAX4589 is constructed of high-frequency “T” switches, as shown in Figure 8. The logic-level inputs are translated by amplifier A1 into a V+ to V- logic sig- nal that drives the internal control logic. The internal control logic drives the gates of N-channel MOSFETs N1 and N2 from V+ to V-, turning them fully on or off. The same signal drives inverter A2 (which drives the P- channel MOSFETs P1 and P2, turning them fully on or off) from V+ to V-, and turns the N-channel MOSFET N3 on and off. The logic-level threshold is determined by VL and GND.

Switch On Condition When the switch is on, MOSFETs N1, N2, P1, and P2 are on and MOSFET N3 is off (Figure 8). The signal path is COM_ to NO_, and because both N-channel and P-channel MOSFETs act as pure resistances, it is symmetrical (i.e., signals pass in either direction). The off MOSFET, N3, has no DC conduction, but has a small amount of capacitance to GND. The MAX4589’s construction allows an exceptional 200MHz -3dB band- width.

Frequency response in 75 systems is reasonably flat up to 50MHz, with typically 2.5dB of insertion loss. Higher-impedance circuits show even lower attenuation (and vice versa), but slightly lower bandwidth due to the increased effect of the internal and external capaci- tance and the switch’s on-resistance.

The MAX4589 is optimized for ±5V operation. Using lower supply voltages or a single supply increases switching time, on-resistance (and therefore on-state attenuation), and nonlinearity.

Switch Off Condition When the switch is off, MOSFETs N1, N2, P1, and P2 are off and MOSFET N3 is on (Figure 8). The signal path is through the parasitic off-capacitances of N1, N2, P1, and P2, but it is shunted to ground by N3. This forms a highpass filter whose exact characteristics are dependent on the source and load impedances. In 75 systems, and below 1MHz, the attenuation exceeds 80dB. This value decreases with increasing frequency and increasing circuit impedances. External capaci- tance and board layout dominate overall performance.


NO_

N1

N2

COM_


N3


V+ VL

A_

A1

CONTROL LOGIC

A2


GND

V-


P2

P1

MAX4589

Figure 8. T-Switch Construction


Applications Information

Power-Supply Considerations

Overview The MAX4589 construction is typical of many CMOS analog switches. It has four supply pins: V+, V-, VL, and GND. V+ and V- are used to drive the internal CMOS switches and set the limits of the analog voltage on any switch. Reverse ESD-protection diodes are internally connected between each analog signal pin and both V+ and V-. If the voltage on any pin exceeds V+ or V-, one of these diodes conducts. During normal operation these reverse-biased ESD diodes leak, forming the only current drawn from V- and V+.

Virtually all the analog leakage current is through the ESD diodes. Although the ESD diodes on a given sig- nal pin are identical, and therefore fairly well balanced, they are reverse-biased differently. Each is biased by either V+ or V- and the analog signal. This means their leakages vary as the signal varies. The difference in the two diode leakages from the signal path to the V+ and V- pins constitutes the analog signal-path leakage cur- rent. All analog leakage current flows to the supply ter- minals, not to the other switch terminal. This explains how both sides of a given switch can show leakage currents of either the same or opposite polarity.

There is no connection between the analog signal paths and GND. The analog signal paths consist of an


N-channel and P-channel MOSFET with their sources and drains paralleled and their gates driven out of phase to V+ and V- by the logic-level translators.

VL and GND power the internal logic and logic-level translators, and set the input logic thresholds. The logic-level translators convert the logic levels to switched V+ and V- signals to drive the gates of the analog switches. Therefore, the gate-to-source and gate-to-drain impedances are the only connection between the logic supplies and the analog supplies.

Bipolar-Supply Operation

The MAX4589 operates with bipolar supplies between

± 2.7V and ± 6V. The V+ and V- supplies are not required to be symmetrical, but their sum cannot exceed the absolute maximum rating of 13.0V. Do not connect the MAX4589 V+ pin to +3V and connect the logic-level input pins to TTL logic-level signals. This exceeds the absolute maximum ratings, and may cause damage to the part and/or external circuits.

CAUTION: The absolute maximum V+ to V- differen- tial voltage is 13.0V. Typical “±6-Volt” or “12-Volt” supplies with ±10% tolerances can be as high as 13.2V. This voltage can damage the MAX4589. Even

±5% tolerance supplies may have overshoot or noise spikes that exceed 13.0V.


Single-Supply Operation

The MAX4589 operates from a single supply between

+ 2.7V and + 12V when V- is connected to GND. Observe all of the precautions listed in the Bipolar- Supply Operation section. Note, however, that these parts are optimized for ±5V operation, and AC and DC characteristics are degraded significantly when operat- ing at less than ± 5V. As the overall supply voltage (V+ to V-) is reduced, switching speed, on-resistance, off-isolation, and distortion are degraded (see Typical Operating Characteristics).

Single-supply operation also limits signal levels and interferes with grounded signals. When V- = GND, AC signals are limited to 300mV below GND. Voltages below this level are clipped by the internal ESD-protec- tion diodes, and the parts can be damaged if exces- sive current flows.

Power Off

When power to the MAX4589 is off (i.e., V+ = 0 and V-

= 0), the Absolute Maximum Ratings still apply. This means that none of the MAX4589 pins can exceed

±0.3V. Voltages beyond ±0.3V cause the internal ESD- protection diodes to conduct, with potentially cata- strophic consequences.

Power-Supply Sequencing When applying power to the MAX4589, follow this sequence: V+, V-, VL, then logic inputs. Apply signals on the analog NO_ and COM_ pins any time after V+ and V- are set. Turning on all pins simultaneously is acceptable only if the circuit design guarantees con- current power-up.

The power-down sequence is the opposite of the power-up sequence. That is, the VL and logic inputs must go to zero potential before (or simultaneously with) the V- then V+ supplies. Always observe the Absolute Maximum Ratings to ensure proper operation.

Grounding

DC Ground Considerations Satisfactory high-frequency operation requires that careful consideration be given to grounding. For most applications, a ground plane is strongly recom- mended and the GND pin must connect to it with solid copper. While the V+ and V- power-supply pins are common to all switches in a given package, each input pair is separated with ground pins that are not internally connected to each other. This contributes to the overall high-frequency performance by reducing channel-to-channel crosstalk.

The digital inputs have voltage thresholds determined by VL and GND. (V- does not influence the logic-level

threshold.) With VL = +5V and GND = 0, the threshold is about 1.6V, ensuring compatibility with TTL- and CMOS- logic drivers.

MAX4589

AC Ground and Bypassing A ground plane is mandatory for satisfactory high- frequency operation. Prototyping using hand wiring or wire-wrap boards is not recommended. Make the ground plane solid metal underneath the device, with- out interruptions. Avoid routing traces under the device itself. For DIP packages, this applies to both sides of a two-sided board. Failure to observe this has a minimal effect on the “on” characteristics of the switch at high frequencies, but it will degrade the off-isolation and crosstalk.

When using the SO package of the MAX4589 on PC boards with a buried ground plane, connect the GND pins to the ground plane with a separate via. Do not share this via with any other ground path. Providing a ground via on both sides of the SMT land further enhances the off-isolation by lowering the parasitic inductance. With the DIP package, connect the through-holes directly to the buried plane or thermally relieve them, as required, to meet manufacturability requirements. Again, do not use these through-hole pads as the current path for any other components.

Bypass the V+ and V- pins to the ground plane with sur- face-mount 0.1µF capacitors. Locate these capacitors as close as possible to the pins on the same side of the board as the device. Do not use feedthroughs or vias for bypass capacitors. If board layout dictates that the bypass capacitors are mounted on the opposite side of the PC board, use short feedthroughs or vias, directly under the V+ and V- pins. Use multiple vias if possible. If V- = GND, connect it directly to the ground plane with solid copper. Keep all traces short.

Signal Routing Keep all signal traces as short as possible. Separate all signal traces from each other, and keep them away from any other traces that could induce interference. Separating the signal traces with generously sized ground wires also helps minimize interference. Routing signals via coaxial cable, terminated as close to the MAX4589 as possible, provides the highest isolation.

Board Layout IC sockets degrade high-frequency performance and are not recommended if signal bandwidth exceeds 5MHz. Surface-mount parts, having shorter internal lead frames, provide the best high-frequency perfor- mance. Keep all bypass capacitors close to the device, and separate all signal leads with ground planes. Use


MAX4589

vias to connect the ground planes on each side of the board. Logic-level signal routing is not critical.

Impedance Matching The MAX4589 is intended for use in 75 systems, where the inputs are terminated external to the IC and the COM terminals are connected to an impedance of 600 or higher. The MAX4589 operates in 50 and 75 systems with terminations through the IC. However, variations in on-resistance and on-resistance flatness cause nonlinearities.

Crosstalk and Off-Isolation The graphs shown in the Typical Operating Character- istics for crosstalk and off-isolation are taken on adja- cent channels. The adjacent channel is the worst-case condition. For example, NO1 has the worst off-isolation to COM1 due to its close proximity. Choosing channels wisely necessitates separating the most sensitive chan- nels from the most offensive. Conversely, the above information also applies to the NO3 and NO4 inputs to the COM2 pin.

Power-On Reset (POR) The MAX4589 has internal circuitry to guarantee that all switches are off on power-up (POR). This is equivalent to the state resulting from asserting RS during normal operation.

Serial Operation The serial mode is activated by driving the SER/PAR input pin to a logic high. The data is then entered using

a 4-bit SPI/MICROWIRE write operation. Systems that must write longer data streams can ignore all but the last four bits. Refer to Figure 7 for a detailed diagram of the serial-interface logic. The first bit loaded is A0, then A1, then an unused bit, followed by the disable bit.

There are four flip-flops in the input shift register. The output of the 4th shift register is output on DOUT on the rising edge of A1/SCLK. This allows cascading of multi- ple MAX4589s using only one chip-select line. For example, one 16-bit write programs the shift registers of four cascaded MAX4589s. The data from the shift register is moved to the internal control latches only upon the rising edge of CS, so all four MAX4589s change state simultaneously. RS has the same effect as the internal power-on reset (POR) signal. The POR state is A0 = A1 = 0 and disable = 1.

In serial mode, 2/4 is not used. Connect it to GND or VL; do not leave 2/4 unconnected.

Parallel Operation The parallel mode is activated by driving SER/PAR to a logic low. The MAX4589 is then programmed by a latched parallel bus scheme. Refer to Figure 6 for a detailed diagram of the parallel-interface logic. If 2/4 is high, A1 is disabled and the MAX4589 is configured as a dual 1-of-2 multiplexer. If 2/4 is low, the MAX4589 is configured as a 1-of-4 multiplexer. It is best to hard-wire 2/4 to a known state for the desired mode of operation, or to use a dedicated microcontroller port pin.


MAX4589

Truth Tables

Parallel Operation


SER/PAR

A1

A0

EN

LE

RS

2/4

SWITCH STATES

0

x

x

x

1

1

x

Maintain previous state.

x

x

x

x

x

0

x

All switches off, latches are cleared.

1

x

x

x

x

1

x

Serial Mode. Refer to Serial Operation Truth Table.

0

x

x

0

0

1

x

All switches off.

0

0

0

1

0

1

0

Connect NO1 to COM1

0

0

1

1

0

1

0

Connect NO2 to COM1

0

1

0

1

0

1

0

Connect NO3 to COM2

0

1

1

1

0

1

0

Connect NO4 to COM2

0

x

0

1

0

1

1

Connect NO1 to COM1and NO3 to COM2

0

x

1

1

0

1

1

Connect NO2 to COM1and NO4 to COM2

x = Don’t Care.

Note: 2/4 is not latched when LE is high. When LE is low, all latches are transparent. A1, A0 and EN are latched.

Connect COM1 to COM2 externally for 1-of-4 single-ended operation.


Serial Operation


SER/PAR

CS

SCLK

DIN

EN

RS

DOUT

SWITCH STATES

1

x

x

x

x

0

0

All switches off, latches and shift register are cleared. This is the Power-On Reset (POR) state.

0

x

x

x

x

x

High-Z

Parallel Mode. Refer to Parallel Operation Truth Table.

1

x

x

x

0

1

*

All switches off.

1

1

x

x

1

1

*

Chip unselected.

1

0


x

1

1

*

Input shift register loads one bit from DIN. DOUT updates on rising edge of SCLK.

1


x

x

1

1

*

Contents of shift register transferred to control latches.

x = Don’t Care.

*DOUT is delayed by 4 clock cycles from DIN.


MAX4589

Truth Tables ( continued)

Control Bit and 2/4 Logic


DISABLE BIT

BIT 3

A1 BIT

A0 BIT

2/4

PIN

SWITCH STATES

1

x

x

x

x

All switches off.

0

x

0

0

0

Connects NO1 to COM1

0

x

0

1

0

Connects NO2 to COM1

0

x

1

0

0

Connects NO3 to COM2

0

x

1

1

0

Connects NO4 to COM2

0

x

x

0

1

Connects NO1 to COM1 and NO3 to COM2

0

x

x

1

1

Connects NO2 to COM1 and NO4 to COM2

x = Don't Care.

Note: A0, A1, BIT 3, and DISABLE are the 4 bits latched into the MAX4589 with a MICROWIRE/SPI write, respectively. A0 is the LSB (first bit clocked in), BIT 3 is not used, and DISABLE is the MSB (last bit clocked in).


Chip Information


TRANSISTOR COUNT: 853


MAX4589

PDIPN.EPS

SSOP.EPS

Package Information











MAX4589

SOICW.EPS

Package Information (continued)







































































Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.

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