Low supply current: 4 μA/amplifier maximum
8
1
OUT A V+
Single-supply operation: 2.7 V to 12 V Wide input voltage range
Rail-to-rail output swing Low offset voltage: 1.5 mV No phase reversal
–IN A
+IN A V–
2 OP281
6
7
TOP VIEW
5
3 (Not to Scale)
4
Figure 1. 8-Lead
OUT B
–IN B
00291-001
+IN B
Comparator
OUT A
Narrow-Body SOIC
(R Suffix)
1 8 V+
Battery-powered instrumentation Safety monitoring
Remote sensors
Low voltage strain gage amplifiers
–IN A 2
+IN A 3
V– 4
OP281
TOP VIEW
(Not to Scale)
7 OUT B
00291-002
6 –IN B
5 +IN B
The OP281 and OP481 are dual and quad ultralow power single-supply amplifiers featuring rail-to-rail outputs. Each operates from supplies as low as 2.0 V and is specified at +3 V and +5 V single supplies as well as ±5 V dual supplies.
Fabricated on Analog Devices’ CBCMOS process, the OP281/OP481 feature a precision bipolar input and an output that swings to within millivolts of the supplies, continuing to sink or source current up to a voltage equal to the supply voltage.
Applications for these amplifiers include safety monitoring, portable equipment, battery and power supply control, and
OUT A
–IN A
+IN A V+
+IN B
–IN B OUT B
Figure 2. 8-Lead TSSOP (RU Suffix)
1 | OP481 TOP VIEW (Not to Scale) | 14 |
2 | 13 | |
3 | 12 | |
4 | 11 | |
5 | 10 | |
6 | 9 | |
7 | 8 |
OUT D
–IN D
+IN D V–
+IN C
00291-003
–IN C OUT C
Figure 3. 14-Lead Narrow-Body SOIC (R Suffix)
signal conditioning and interfacing for transducers in very low power systems.
The output’s ability to swing rail-to-rail and not increase supply current when the output is driven to a supply voltage enables
OUT A 1
–IN A 2
+IN A 3
V+ 4
+IN B 5
OP481
TOP VIEW
(Not to Scale)
14 OUT D
13 –IN D
12 +IN D
11 V–
10 +IN C
the OP281/OP481 to be used as comparators in very low power systems. This is enhanced by their fast saturation recovery time. Propagation delays are 250 μs.
–IN B 6
OUT B 7
9 –IN C
00291-004
8 OUT C
The OP281/OP481 are specified over the extended industrial temperature range (−40°C to +85°C). The OP281 dual amplifier is available in 8-lead SOIC surface-mount and TSSOP packages. The OP481 quad amplifier is available in narrow 14-lead SOIC and TSSOP packages.
Figure 4. 14-Lead TSSOP
(RU Suffix)
Rev. D
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibilityis assumedby Analog Devicesforitsuse, norforanyinfringements ofpatents orother rightsofthirdpartiesthatmayresultfromitsuse.Specificationssubjecttochangewithoutnotice.No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com
Fax: 781.461.3113 ©1996–2008 Analog Devices, Inc. All rights reserved.
Typical Performance Characteristics 7
Input Overvoltage Protection 13
Input Common-Mode Voltage Range 13
Micropower Reference Voltage Generator 14
Low Voltage Half-Wave and Full-Wave Rectifiers 15
Battery-Powered Telephone Headset Amplifier 15
9/08—Rev. C to Rev. D
Changes to Figure 40 14
Changes to Low-Side Current Monitor Section 15
Changes to Figure 42 15
10/07—Rev. B to Rev. C
Updated Format..................................................................Universal
Changes to Offset Voltage Drift Condition 3
Changes to Slew Rate Symbol 5
Changes to Figure 8 7
Deleted SPICE Macro-Model Section 13
Updated Outline Dimensions 17
Changes to Ordering Guide 18
3/03—Rev. A to Rev. B
Changes to Features 1
2/03—Rev. 0 to Rev. A
Updated Format.................................................................. Universal
Deleted OP181 .................................................................... Universal
Updated Package Options ................................................. Universal
Deleted OP181 Pin Configurations 1
Deleted Epoxy DIP Pin Configurations 1
Changes to Absolute Maximum Ratings 5
Changes to Ordering Guide 5
Changes to Input Offset Voltage 10
Deleted Former Figure 33 10
Deleted Overdrive Recovery Time Section 11
Deleted Former Figure 36 11
Deleted 8-Lead and 14-Lead Plastic DIP (N-8 and N-14) Outline Dimensions 14
Updated Outline Dimensions 14
VS = 3.0 V, VCM = 1.5 V, TA = 25°C, unless otherwise noted.
Table 1.
Parameter | Symbol | Condition | Min | Typ Max | Unit |
INPUT CHARACTERISTICS | |||||
VOS | 1.5 | mV | |||
−40°C ≤ TA ≤ +85°C | 2.5 | mV | |||
Input Bias Current | IB | −40°C ≤ TA ≤ +85°C | 3 10 | nA | |
Input Offset Current | IOS | −40°C ≤ TA ≤ +85°C | 0.1 7 | nA | |
Input Voltage Range | 0 | 2 | V | ||
Common-Mode Rejection Ratio | CMRR | VCM = 0 V to 2.0 V, −40°C ≤ TA ≤ +85°C | 65 | 95 | dB |
Large-Signal Voltage Gain | AVO | RL = 1 MΩ, VO = 0.3 V to 2.7 V | 5 | 13 | V/mV |
−40°C ≤ TA ≤ +85°C | 2 | V/mV | |||
Offset Voltage Drift | ΔVOS/∆T | −40°C to +85°C | 10 | μV/°C | |
Bias Current Drift | ΔIB/ΔT | 20 | pA/°C | ||
Offset Current Drift | ΔIOS/ΔT | 2 | pA/°C | ||
OUTPUT CHARACTERISTICS | |||||
Output Voltage High | VOH | RL = 100 kΩ to GND, −40°C ≤TA ≤ +85°C | 2.925 | 2.96 | V |
Output Voltage Low | VOL | RL = 100 kΩ to V+, −40°C ≤ TA ≤ +85°C | 25 75 | mV | |
Short-Circuit Limit | ISC | ±1.1 | mA | ||
POWER SUPPLY | |||||
Power Supply Rejection Ratio | PSRR | VS = 2.7 V to 12 V, −40°C ≤ TA ≤ +85°C | 76 | 95 | dB |
Supply Current/Amplifier | ISY | VO = 0 V | 3 4 | μA | |
−40°C ≤ TA ≤ +85°C | 5 | μA | |||
DYNAMIC PERFORMANCE | |||||
Slew Rate | SR | RL = 100 kΩ, CL = 50 pF | 25 | V/ms | |
Turn-On Time | AV = 1, VO = 1 V | 40 | μs | ||
AV = 20, VO = 1 V | 50 | μs | |||
Saturation Recovery Time | 65 | μs | |||
Gain Bandwidth Product | GBP | 95 | kHz | ||
Phase Margin | φM | 70 | Degrees | ||
NOISE PERFORMANCE | |||||
Voltage Noise | en p-p | 0.1 Hz to 10 Hz | 10 | μV p-p | |
Voltage Noise Density | en | f = 1 kHz | 75 | nV/√Hz | |
Current Noise Density | in | <1 | pA/√Hz |
1 VOS is tested under a no load condition.
VS = 5.0 V, VCM = 2.5 V, TA = 25°C, unless otherwise noted.
Table 2.
Parameter | Symbol | Condition | Min | Typ Max | Unit |
INPUT CHARACTERISTICS | |||||
VOS | 0.1 1.5 | mV | |||
−40°C ≤ TA ≤ +85°C | 2.5 | mV | |||
Input Bias Current | IB | −40°C ≤ TA ≤ +85°C | 3 10 | nA | |
Input Offset Current | IOS | −40°C ≤ TA ≤ +85°C | 0.1 7 | nA | |
Input Voltage Range | 0 | 4 | V | ||
Common-Mode Rejection Ratio | CMRR | VCM = 0 V to 4.0 V, −40°C ≤ TA ≤ +85°C | 65 | 90 | dB |
Large-Signal Voltage Gain | AVO | RL = 1 MΩ, VO = 0.5 V to 4.5 V | 5 | 15 | V/mV |
−40°C ≤ TA ≤ +85°C | 2 | V/mV | |||
Offset Voltage Drift | ΔVOS/ΔT | −40°C to +85°C | 10 | μV/°C | |
Bias Current Drift | ΔIB/ΔT | 20 | pA/°C | ||
Offset Current Drift | ΔIOS/ΔT | 2 | pA/°C | ||
OUTPUT CHARACTERISTICS | |||||
Output Voltage High | VOH | RL = 100 kΩ to GND, −40°C ≤TA ≤ +85°C | 4.925 | 4.96 | V |
Output Voltage Low | VOL | RL = 100 kΩ to V+, −40°C ≤ TA ≤ +85°C | 25 75 | mV | |
Short-Circuit Limit | ISC | ±3.5 | mA | ||
POWER SUPPLY | VS = 2.7 V to 12 V, −40°C ≤ TA ≤ +85°C VO = 0 V −40°C ≤ TA ≤ +85°C | dB μA μA | |||
Power Supply Rejection Ratio Supply Current/Amplifier | PSRR ISY | 76 | 95 3.2 4 5 | ||
DYNAMIC PERFORMANCE Slew Rate Saturation Recovery Time Gain Bandwidth Product Phase Margin | SR GBP φM | RL = 100 kΩ, CL = 50 pF | 27 120 100 74 | V/ms μs kHz Degrees | |
NOISE PERFORMANCE | |||||
Voltage Noise | en p-p | 0.1 Hz to 10 Hz | 10 | μV p-p | |
Voltage Noise Density | en | f = 1 kHz | 75 | nV/√Hz | |
Current Noise Density | in | <1 | pA/√Hz |
1 VOS is tested under a no load condition.
VS = ±5.0 V, TA = +25°C, unless otherwise noted.
Table 3.
Parameter | Symbol | Condition | Min | Typ Max | Unit |
INPUT CHARACTERISTICS | |||||
VOS | 0.1 1.5 | mV | |||
–40°C ≤ TA ≤ +85°C | 2.5 | mV | |||
Input Bias Current | IB | –40°C ≤ TA ≤ +85°C | 3 10 | nA | |
Input Offset Current | IOS | –40°C ≤ TA ≤ +85°C | 0.1 7 | nA | |
Input Voltage Range | –5 | +4 | V | ||
Common-Mode Rejection | CMRR | VCM = –5.0 V to +4.0 V, –40°C ≤TA ≤ +85°C | 65 | 95 | dB |
Large-Signal Voltage Gain | AVO | RL = 1 MΩ, VO = ±4.0 V, | 5 | 13 | V/mV |
–40°C ≤ TA ≤ +85°C | 2 | V/mV | |||
Offset Voltage Drift | ΔVOS/ΔT | –40°C to +85°C | 10 | μV/°C | |
Bias Current Drift | ΔIB/ΔT | 20 | pA/°C | ||
Offset Current Drift | ΔIOS/ΔT | 2 | pA/°C | ||
OUTPUT CHARACTERISTICS | |||||
Output Voltage Swing | VO | RL = 100 kΩ to GND, –40°C ≤ TA ≤ +85°C | ±4.925 | ±4.98 | V |
Short-Circuit Limit | ISC | 12 | mA | ||
POWER SUPPLY | |||||
Power Supply Rejection Ratio | PSRR | VS = ±1.35 V to ±6 V, –40°C ≤ TA ≤ +85°C | 76 | 95 | dB |
Supply Current/Amplifier | ISY | VO = 0 V | 3.3 5 | μA | |
–40°C ≤ TA ≤ +85°C | 6 | μA | |||
DYNAMIC PERFORMANCE | |||||
Slew Rate | SR | RL = 100 kΩ, CL = 50 pF | 28 | V/ms | |
Gain Bandwidth Product | GBP | 105 | kHz | ||
Phase Margin | φM | 75 | Degrees | ||
NOISE PERFORMANCE | |||||
Voltage Noise | en p-p | 0.1 Hz to 10 Hz | 10 | μV p-p | |
Voltage Noise Density | en | f = 1 kHz | 85 | nV/√Hz | |
f = 10 kHz | 75 | nV/√Hz | |||
Current Noise Density | in | <1 | pA/√Hz |
1 VOS is tested under a no load condition.
Table 4.
Parameter | Rating |
Supply Voltage | 16 V |
Input Voltage | GND to VS + 10 V |
Differential Input Voltage | ±3.5 V |
Output Short-Circuit Duration to GND | Indefinite |
Storage Temperature Range | −65°C to +150°C |
−40°C to +85°C | |
Junction Temperature Range | −65°C to +150°C |
Lead Temperature Range (Soldering, 60 sec) | 300°C |
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Table 5. Thermal Resistance
Package Type | θJA | θJC | Unit |
8-Lead SOIC (R Suffix) | 158 | 43 | °C/W |
8-Lead TSSOP (RU Suffix) | 240 | 43 | °C/W |
14-Lead SOIC (R Suffix) | 120 | 36 | °C/W |
14-Lead TSSOP (RU Suffix) | 240 | 43 | °C/W |
1 θJA is specified for the worst-case conditions, that is, θJA is specified for device soldered in circuit board for TSSOP and SOIC packages.
VS = 5V | ||||||||||||||||
45 0
VS = 2.7V
40 TA = 25°C
QUANTITY (Amplifiers)
35
30
25
20
15
10
5
–0.5
INPUT BIAS CURRENT (nA)
–1.0
–1.5
–2.0
–2.5
–3.0
–3.5
–4.0
00291-005
–4.5
0
–1.0 –0.8 –0.6 –0.4 –0.2 0
0.2
0.4
0.6
0.8
1.0
–5.0
–40 –20
0 20 40 60
80 100
00291-008
120
INPUT OFFSET VOLTAGE (mV)
Figure 5. Input Offset Voltage Distribution
TEMPERATURE (°C)
Figure 8. Input Bias Current vs. Temperature
50
VS = 5V
45 TA = 25°C
40
QUANTITY (Amplifiers)
35
30
25
20
15
10
5
0
–1.0 –0.8 –0.6 –0.4 –0.2 0
0.2
0.4
0.6
0.8
1.0
1.0
0.5
INPUT BIAS CURRENT (nA)
0
–0.5
–1.0
–1.5
–2.0
–2.5
–3.0
–3.5
VS = 5V TA = 25°C
00291-009
0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
00291-006
2000
1800
INPUT OFFSET VOLTAGE (µV)
1600
1400
1200
1000
800
600
400
00291-007
200
INPUT OFFSET VOLTAGE (mV)
Figure 6. Input Offset Voltage Distribution
COMMON-MODE VOLTAGE (V)
Figure 9. Input Bias Current vs. Common-Mode Voltage
VS = 5V | ||||||||||||||||
0.5
0.4
INPUT OFFSET CURRENT (nA)
0.3
0.2
0.1
0
–0.1
–0.2
–0.3
VS = 5V | ||||||||||||||||
0
–40 –20
0 20 40 60
80 100
120
–0.4
–40 –20
0 20 40 60
80 100
00291-010
120
TEMPERATURE (°C)
Figure 7. Input Offset Voltage vs. Temperature
TEMPERATURE (°C)
Figure 10. Input Offset Current vs. Temperature
10000
70
VS = 5V TA = 25°C RL = 100kΩ | ||||||||||||||||||||||||
VS = 3V
TA = 25°C 60
OUTPUT VOLTAGE (mV)
1000
100
10
1
SOURCE
SINK
50
OPEN-LOOP GAIN (dB)
40
30
20
10
0
–10
00291-014
–20
0
PHASE SHIFT (Degrees)
45
90
135
180
225
270
0.1
1
10 100
00291-011
1000
–30
100
1k 10k 100k 1M
LOAD CURRENT (µA)
Figure 11. Output Voltage to Supply Rail vs. Load Current
FREQUENCY (Hz)
Figure 14. Open-Loop Gain and Phase vs. Frequency
1000
OUTPUT VOLTAGE (mV)
100
10
1
70
60
50
OPEN-LOOP GAIN (dB)
40
30
20
10
0
–10
–20
VS = 3V TA = 25°C
RL = 100kΩ
0
PHASE SHIFT (Degrees)
45
90
135
180
225
00291-015
270
VS = 5V TA = 25°C | |||||||||||||||||||||||||||
SOURCE | |||||||||||||||||||||||||||
SINK | |||||||||||||||||||||||||||
0.1
1
10 100
00291-012
1000
–30
100
1k 10k 100k 1M
LOAD CURRENT (µA)
Figure 12. Output Voltage to Supply Rail vs. Load Current
FREQUENCY (Hz)
Figure 15. Open-Loop Gain and Phase vs. Frequency
1000
OUTPUT VOLTAGE (mV)
100
10
1
VS = ±5V TA = 25°C
SOURCE
SINK
70
60
50
OPEN-LOOP GAIN (dB)
40
30
20
10
0
–10
–20
VS = 2.7V TA = 25°C RL = 100kΩ
0
PHASE SHIFT (Degrees)
45
90
135
180
225
00291-016
270
0.1
1
10 100
00291-013
1000
–30
100
1k 10k 100k 1M
LOAD CURRENT (µA)
Figure 13. Output Voltage to Supply Rail vs. Load Current
FREQUENCY (Hz)
Figure 16. Open-Loop Gain and Phase vs. Frequency
70
60
50
OPEN-LOOP GAIN (dB)
40
30
20
10
0
–10
–20
VS = ±5V TA = 25°C
RL = 100kΩ TO GROUND
0
45
90
135
180
225
270
90
TA = 25°C
VS = ±5V
80
70
VS = +3V
CMRR (dB)
60 VS = +5V 50
40
30
20
10
00291-017
00291-020
0
PHASE SHIFT (Degrees)
–30
100
1k 10k 100k 1M FREQUENCY (Hz)
Figure 17. Open-Loop Gain and Phase vs. Frequency
–10
1k
10k 100k 1M FREQUENCY (Hz)
Figure 20. CMRR vs. Frequency
10M
60
50
CLOSED-LOOP GAIN (dB)
40
30
20
10
0
–10
–20
–30
160
VS = 5V TA = 25° RL = ∞ | |||||||||||||||||||||||||||
VS = ±5V, +5V, +3V, +2.7 TA = 25°C RL = ∞ | ||||||||||||||||||||||||||||
V
C 140
120
100
PSRR (dB)
80
60
40
20
0
00291-018
–20
–40
10 100 1k 10k 100k 1M FREQUENCY (Hz)
Figure 18. Closed-Loop Gain vs. Frequency
–40
00291-021
10 100 1k 10k 100k 1M FREQUENCY (Hz)
Figure 21. PSRR vs. Frequency
VS = 5V TA = 25°C MARKER @ 67nV/√Hz | ||||||||||
50
VS = +5V
SMALL SIGNAL OVERSHOOT (%)
45 VIN = ±50mV RL = 100kΩ
40 TA = 25°C –OS
(50nV/√Hz/DIV)
35
30
25
20
15
10
00291-019
00291-022
5
+OS
0 2 4
6 8 10
0
10 100
1000
FREQUENCY (kHz)
Figure 19. Voltage Noise Density vs. Frequency
LOAD CAPACITANCE (pF)
Figure 22. Small-Signal Overshoot vs. Load Capacitance
5
VS = 5V
MAXIMUM OUTPUT SWING (V p-p)
VIN = 4V p-p TA = 25°C
4 RL = ∞
3
2
1
4.5
SUPPLY CURRENT/AMPLIFIER (µA)
VS = 5V | ||||||||||||||||
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
10 100 1k 10k
FREQUENCY (Hz)
100k
0
–40
–20 0
20 40 60 80
TEMPERATURE (°C)
100
00291-026
120
00291-023
Figure 23. Maximum Output Swing vs. Frequency Figure 26. Supply Current/Amplifier vs. Temperature
MAXIMUM OUTPUT SWING (V p-p)
3
2
1
0
10 100 1k 10k
VS = 3V
VIN = 2V p-p TA = 25°C RL = ∞
00291-024
100k
3.50
TA = 25°C | |||||||||||
3.25
SUPPLY CURRENT/AMPLIFIER (µA)
3.00
2.75
2.50
2.25
2.00
1.75
1.50
1.25
1.00
0.75
0.50
0.25
0
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
00291-027
6.0
FREQUENCY (Hz)
Figure 24. Maximum Output Swing vs. Frequency
SUPPLY VOLTAGE (±V)
Figure 27. Supply Current/Amplifier vs. Supply Voltage
VS = 3V | ||||||||||||||||
4.0
VS = ±2.5V AV = 1
RL = 100kΩ CL = 50pF TA = 25°C
0mV
A2
SUPPLY CURRENT/AMPLIFIER (µA)
3.5
100
90
3.0
2.5
2.0
1.5
1.0
0.5
0
–40
–20 0
20 40 60 80
TEMPERATURE (°C)
100
10
0%
50mV
100µs
00291-025
00291-028
120
Figure 25. Supply Current/Amplifier vs. Temperature Figure 28. Small-Signal Transient Response
100
90
A2
0mV
VS = ±1.35V AV = 1
RL = 100kΩ CL = 50pF TA = 25°C
A2
0.5V
10
0%
10
0%
50mV
100µs
500mV
100µs
100
90
VS = 2.75V AV = 1
RL = 100kΩ
CL = 50pF TA = 25°C
100
90
00291-029
00291-031
Figure 29. Small-Signal Transient Response Figure 31. Large-Signal Transient Response
100
90
A2
2.5V
VS = 5V AV = 1
RL = 100kΩ CL = 50pF TA = 25°C
A2
2.5V
VS = 5V TA = 25°C
10
0%
10
0%
1V
100µs
1V
1V
200µs
00291-030
00291-032
Figure 30. Large-Signal Transient Response Figure 32. No Phase Reversal
VS = 5V TA = 25°C RL = ∞ | |||||||||||||||||||||||
120
VIN = ±1V p-p
AT = 2kHz
VS = ±1.35V RL = ∞
0V
A2
105
100
90
CHANNEL SEPARATION (dB)
90
75
60
45
30
15
10
0%
0
00291-033
–15
500mV
500mV
50µs
Figure 33. Saturation Recovery Time
–30
100
1k 10k 100k 1M FREQUENCY (Hz)
00291-035
Figure 35. Channel Separation vs. Frequency
100
90
A2
0V
CIRCUIT = AVOL
VS = 2.5V TA = 25°C RL = ∞
10
0%
1V
500mV
100µs
00291-034
Figure 34. Saturation Recovery Time
The OPx81 family of op amps is comprised of extremely low powered, rail-to-rail output amplifiers, requiring less than 4 μA of quiescent current per amplifier. Many other competitors’ devices may be advertised as low supply current amplifiers but draw significantly more current as the outputs of these devices are driven to a supply rail. The supply current of the OPx81 remains under
4 μA even when the output is driven to either supply rail. Supply currents should meet the specification as long as the inputs and outputs remain within the range of the power supplies.
Figure 36 shows a simplified schematic of a single channel for the OPx81. A bipolar differential pair is used in the input stage. PNP transistors are used to allow the input stage to remain linear with the common-mode range extending to ground. This is an important consideration for single-supply applications.
The bipolar front end also contributes less noise than a MOS front end with only nanoamps of bias currents. The output of the op amp consists of a pair of CMOS transistors in a common source configuration. This setup allows the output of the
to the lowest possible input signal excursion and can be found using the following formula:
R VEE VIN , MIN
0.5 10 3
where:
VEE is the negative power supply for the amplifier.
VIN, MIN is the lowest input voltage excursion expected.
For example, a single channel of the OPx81 should be used with a single-supply voltage of +5 V if the input signal may go as low as
−1 V. Because the amplifier is powered from a single supply, VEE is the ground; therefore, the necessary series resistance should be 2 kΩ.
The OPx81 family of op amps was designed for low offset voltages (less than 1 mV).
100kΩ
+3V
100kΩ
amplifier to swing to within millivolts of either supply rail. The headroom required by the output stage is limited by the amount
–0.27V
100kΩ
+ OP281
00291-037
VIN = 1kHz AT
VOUT
of current being driven into the load. The lower the output current, the closer the output can go to either supply rail. Figure 11, Figure 12, and Figure 13 show the output voltage
– 400mV p-p
–0.1V
100kΩ
headroom vs. the load current. This behavior is typical of rail- to-rail output amplifiers.
VCC
OUT
+IN
–IN
Figure 37. Single OPx81 Channel Configured as a Difference Amplifier Operating at VCM < 0 V
The OPx81 is rated with an input common-mode voltage range from VEE to 1 V less than VCC. However, the op amp can operate with a common-mode voltage that is slightly less than VEE. Figure 37 shows a single OPx81 channel configured as a difference amplifier with a single-supply voltage of 3 V. Negative dc voltages are applied at both input terminals, creating a common-mode voltage that is less than ground. A 400 mV p-p input signal is then applied to the noninverting input. Figure 38 shows the resulting input and output waves. Notice how the output of the amplifier also drops slightly negative without distortion.
00291-036
VEE
Figure 36. Simplified Schematic of a Single OPx81 Channel
The input stage to the OPx81 family of op amps consists of a PNP differential pair. If the base voltage of either of these input transistors drops to more than 0.6 V below the negative supply, the input ESD protection diodes become forward-biased, and large currents begin to flow. In addition to possibly damaging the device, this creates a phase reversal effect at the output. To prevent this, the input current should be limited to less than 0.5 mA.
VOUT
VIN
100
90
10
0%
0V
00291-038
0.2ms | |||||||||
0.1V |
Figure 38. Input and Output Signals with VCM < 0 V
Most low supply current amplifiers have difficulty driving capacitive loads due to the higher currents required from the output stage for such loads. Higher capacitance at the output will increase the amount of overshoot and ringing in the amplifier’s step response and may affect the stability of the device. However, through careful design of the output stage and its high phase
The extremely low power supply current demands of the OPx81 family make it ideal for use in long-life battery-powered applications such as a monitoring system. Figure 41 shows a circuit that uses the OP281 as a window comparator.
3V
3V
margin, the OPx81 family can tolerate some degree of capacitive loading. Figure 39 shows the step response of a single channel
3V
R1
VH
D1 10kΩ
5.1kΩ
VOUT
100
90
10
0%
with a 10 nF capacitor connected at the output. Notice that the overshoot of the output does not exceed more than 10% with such a load, even with a supply voltage of only 3 V.
R2
VIN
2kΩ
3V
R3
VL
R4
A1
OP281-A
3V
D2
A2
00291-041
OP281-B
Q1
5.1kΩ
00291-039
Figure 39. Ringing and Overshoot of the Output of the Amplifier
Many single-supply circuits are configured with the circuit biased to half of the supply voltage. In these cases, a false ground reference can be created by using a voltage divider buffered by an amplifier. Figure 40 shows the schematic for such a circuit.
The two 1 MΩ resistors generate the reference voltage while drawing only 1.5 μA of current from a 3 V supply. A capacitor connected from the inverting terminal to the output of the op amp provides compensation to allow a bypass capacitor to be connected at the reference output. This bypass capacitor helps to establish an ac ground for the reference output. The entire reference generator draws less than 5 μA from a 3 V supply source.
3V TO 12V
10kΩ
0.022µF
Figure 41. Using the OP281 as a Window Comparator
The threshold limits for the window are set by VH and VL, provided that VH > VL. The output of the first OP281 (A1) will stay at the negative rail, in this case ground, as long as the input voltage is less than VH. Similarly, the output of the second OP281 (A2) will stay at ground as long the input voltage is higher than VL. As long as VIN remains between VL and VH, the outputs of both op amps will be 0 V. With no current flowing in either D1 or D2, the base of Q1 will stay at ground, putting the transistor in cutoff and forcing VOUT to the positive supply rail. If the input voltage rises above VH, the output of A2 stays at ground, but the output of A1 goes to the positive rail and D1 conducts current. This creates a base voltage that turns on Q1 and drives VOUT low. The same condition occurs if VIN falls below VL with A2’s output going high and D2 conducting current. Therefore, VOUT is high if the input voltage is between VL and VH, but low if the input voltage moves outside of that range.
The R1 and R2 voltage divider sets the upper window voltage, and the R3 and R4 voltage divider sets the lower voltage for the window. For the window comparator to function properly, VH must be a greater voltage than VL.
H
V R2
R1 R2
L
V R4
R3 R4
The 2 kΩ resistor connects the input voltage of the input
1MΩ
00291-040
1MΩ
2
3
1µF
8
OP281 1
4
100Ω
1µF
VREF
1.5V TO 6V
terminals to the op amps. This protects the OP281 from possible excess current flowing into the input stages of the devices. D1 and D2 are small-signal switching diodes (1N4446 or equivalent), and Q1 is a 2N2222 or an equivalent NPN transistor.
Figure 40. Single Channel Configured asa Micropower Bias Voltage Generator
In the design of power-supply control circuits, a great deal of design effort is focused on ensuring the long-term reliability of a pass transistor over a wide range of load current conditions. As a result, monitoring and limiting device power dissipation is of primary importance in these designs. Figure 42 shows an example of a 5 V, single-supply current monitor that can be incorporated into the design of a voltage regulator with fold-
2kΩ VIN = 2V p-p
R1 100kΩ
3V
OP281-A
A1
R2 100kΩ
3V A2
OP281-B
FULL-WAVE RECTIFIED OUTPUT
00291-043
HALF-WAVE RECTIFIED OUTPUT
back current limiting or a high current power supply with crowbar protection. The design capitalizes on the OPx81’s common-mode range extending to ground. Current is monitored in the power-supply return path, where a 0.1 Ω shunt resistor, RSENSE, creates a very small voltage drop. The voltage at the inverting terminal becomes equal to the voltage at the noninverting terminal through the feedback of Q1, which is a 2N2222 or an equivalent NPN transistor. This makes the voltage drop across R1 equal to the voltage drop across RSENSE. Therefore, the current through Q1 becomes directly proportional to the current through RSENSE, and the output voltage is given by the following equation:
Figure 43. Single-Supply Full-Wave and Half-Wave Rectifiers Using an OP281
100
90
10
0%
SCALE 0.1V/DIV
SCALE
0.1ms/DIV
VOUT
VCC
⎛ R2 R
⎜ R1
⎝
SENSE I ⎞
00291-044
L
⎟
⎠
The voltage drop across R2 increases as IL increases; therefore, VOUT decreases if a higher supply current is sensed. For the element values shown, the VOUT transfer characteristic is
−2.5 V/A, decreasing from VCC.
VCC
R2 2.49kΩ
VOUT
Q1
VCC
SINGLE
Figure 44. Full-Wave Rectified Signal
Amplifier A1 is used as a voltage follower that tracks the input voltage only when it is greater than 0 V. This provides a half- wave rectification of the input signal to the noninverting terminal of Amplifier A2. When A1’s output is following the input, the inverting terminal of A2 also follows the input from the virtual ground between the inverting and noninverting terminals of A2. With no potential difference across R1, no current flows through either R1 or R2; therefore, the output of A2 also follows the input. When the input voltage goes below 0 V, the noninverting terminal of A2 becomes 0 V. This makes
A2 work as an inverting amplifier with a gain of 1 and provides
R1 100Ω
0.1Ω RSENSE
CHANNEL OPx81
00291-042
RETURN TO GROUND
a full-wave rectified version of the input signal. A 2 kΩ resistor in series with A1’s noninverting input protects the device when the input signal becomes less than ground.
Figure 42. Low-Side Load Current Monitor
Because of its quick overdrive recovery time, an OP281 can be configured as a full-wave rectifier for low frequency (<500 Hz) applications. Figure 43 shows the schematic.
Figure 45 shows how the OP281 can be used as a two-way amplifier in a telephone headset. One side of the OP281 can be used as an amplifier for the microphone, and the other side can be used to drive the speaker. A typical telephone headset uses a 600 Ω speaker and an electret microphone that requires a supply voltage and a biasing resistor.
0.1µF11kΩ 300kΩ
audio bandwidth. A 2.2 kΩ resistor is used to bias the electret
3V
2.2kΩ
3V
1MΩ
3V
1µF
microphone. This resistor value may vary depending on the specifications of the microphone. The output of the microphone is ac-coupled to the noninverting terminal of the op amp. Two 1 MΩ
1µF MIC OUT
ELECTRET 1MΩ OP281-A
MIC
resistors are used to provide the dc offset for single-supply use.
The OP281-B amplifier (see Figure 45) can provide up to 15 dB of gain for the headset speaker. Incoming audio signals are ac-coupled
1µF 10kΩ
INPUT 1µF
50kΩ
3V
20kΩ
3V
Q1
1µF
to a 10 kΩ potentiometer that is used to adjust the volume. Again, two 1 MΩ resistors provide the dc offset with a 1 μF capacitor establishing an ac ground for the volume-control potentiometer. Because the OP281 is a rail-to-rail output amplifier, it would have difficulty driving a 600 Ω speaker directly. Here, a Class AB buffer is used to isolate the load from the amplifier and to provide the necessary current to drive the speaker. By placing the buffer in the feedback loop of the op amp, crossover distortion can be
10kΩ
3V POT.
1MΩ 1MΩ
1µF
OP281-B
20kΩ
Q2 600Ω SPEAKER
minimized. Q1 and Q2 should have minimum betas of 100. The 600 Ω speaker is ac-coupled to the emitters to prevent quiescent current from flowing into the speaker. The 1 μF coupling capacitor makes an equivalent high-pass filter cutoff at 265 Hz with a 600 Ω
00291-045
Figure 45. Two-Way Amplifier in a Battery-Powered Telephone Headset
The OP281-A op amp provides about 29 dB of gain for audio signals coming from the microphone. The gain is set by the
300 kΩ and 11 kΩ resistors. The gain bandwidth product of the amplifier is 95 kHz, which yields a −3 dB rolloff at 3.4 kHz for the set gain of 28. This is acceptable because telephone audio is band limited for 300 kHz to 3 kHz signals. If higher gain is required for the microphone, an additional gain stage should be used, because adding more gain to the OP281 would limit the
load attached. Again, this does not pose a problem because it is outside the frequency range for telephone audio signals.
The circuit in Figure 45 draws around 250 μA of current. The Class AB buffer has a quiescent current of 140 μA, and roughly 100 μA is drawn by the microphone itself. A CR2032 3 V lithium battery has a life expectancy of 160 mA hours, which means this circuit can run continuously for 640 hours on a single battery.
5.00 (0.1968)
4.80 (0.1890)
4.00 (0.1574)
3.80 (0.1497)
8
5
6.20 (0.2441)
4
1
5.80 (0.2284)
1.27 (0.0500) 0.50 (0.0196)
45°
0.25 (0.0098)
0.10 (0.0040)
BSC
1.75 (0.0688)
1.35 (0.0532) 8°
0°
0.25 (0.0099)
COPLANARITY
0.51 (0.0201)
1.27 (0.0500)
0.10
SEATING PLANE
0.31 (0.0122)
0.25 (0.0098)
0.17 (0.0067)
0.40 (0.0157)
COMPLIANT TO JEDEC STANDARDS MS-012-A A
012407-A
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
Figure 46. 8-Lead Standard Small Outline Package [SOIC_N]
Narrow Body (R-8)
Dimensions shown in millimeters and (inches)
8.75 (0.3445)
8.55 (0.3366)
4.00 (0.1575)
3.80 (0.1496)
6.20 (0.2441)
7
8
14
1
5.80 (0.2283)
1.27 (0.0500)
0.50 (0.0197)
45°
0.25 (0.0098)
0.10 (0.0039) COPLANARITY
BSC
0.10 PLANE 0.25 (0.0098) | |||
0.31 (0.0122) | 0.17 (0.0067) |
0.51 (0.0201)
1.75 (0.0689)
1.35 (0.0531) 8°
0°
SEATING
0.25 (0.0098)
1.27 (0.0500)
0.40 (0.0157)
COMPLIANT TO JEDEC STANDARDS MS-012-AB
060606-A
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
Figure 47. 14-Lead Standard Small Outline Package [SOIC_N]
Narrow Body (R-14)
Dimensions shown in millimeters and (inches)
3.00 2.90
8 5
4.50
4.40
4.30
6.40 BSC
1 4
PIN 1
0.65 BSC
0.15 1.20
0.05
MAX
8°
COPLANARITY 0.10
0.30
0.19
SEATING PLANE
0.20 0° 0.09
0.75
0.60
0.45
COMPLIANT TO JEDEC STANDARDS MO-153-AA
Figure 48. 8-Lead Thin Shrink Small Outline Package [TSSOP] (RU-8)
Dimensions shown in millimeters
5.10
5.00
4.90
4.50
4.40
4.30
14 8
6.40
BSC
PIN 1
1.05
1.00
0.65
BSC
0.20
0.80 1.20
MAX
0.09
0.75
0.15
0.30
8° 0.60
0.05
0.19
SEATING PLANE
0°
COPLANARITY 0.10
0.45
COMPLIANT TO JEDEC STANDARDS MO-153-AB-1
Figure 49. 14-Lead Thin Shrink Small Outline Package [TSSOP] (RU-14)
Dimensions shown in millimeters
Model | Temperature Range | Package Description | Package Option |
OP281GRU-REEL | –40°C to +85°C | 8-Lead TSSOP | RU-8 |
–40°C to +85°C | 8-Lead TSSOP | RU-8 | |
OP281GS | –40°C to +85°C | 8-Lead SOIC_N | R-8 |
OP281GS-REEL | –40°C to +85°C | 8-Lead SOIC_N | R-8 |
OP281GS-REEL7 | –40°C to +85°C | 8-Lead SOIC_N | R-8 |
–40°C to +85°C | 8-Lead SOIC_N | R-8 | |
–40°C to +85°C | 8-Lead SOIC_N | R-8 | |
–40°C to +85°C | 8-Lead SOIC_N | R-8 | |
OP481GRU-REEL | –40°C to +85°C | 14-Lead TSSOP | RU-14 |
–40°C to +85°C | 14-Lead TSSOP | RU-14 | |
OP481GS | –40°C to +85°C | 14-Lead SOIC_N | R-14 |
OP481GS-REEL | –40°C to +85°C | 14-Lead SOIC_N | R-14 |
OP481GS-REEL7 | –40°C to +85°C | 14-Lead SOIC_N | R-14 |
–40°C to +85°C | 14-Lead SOIC_N | R-14 | |
–40°C to +85°C | 14-Lead SOIC_N | R-14 | |
–40°C to +85°C | 14-Lead SOIC_N | R-14 |
1 Z = RoHS Compliant Part.
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