Data Sheet
Very low noise density of 5 nV/√Hz at 1 kHz maximum Excellent input offset voltage of 75 μV maximum
Low offset voltage drift of 1 μV/°C maximum Very high gain of 1500 V/mV minimum Outstanding CMR of 106 dB minimum
Slew rate of 2.4 V/μs typical
–IN A 1
+IN A 2
NC 3
V– 4
NC 5
+IN B 6
–IN B 7
OP270
16 OUT A
15 NC
14 NC
13 V+
12 NC
11 NC
10 OUT B
Gain bandwidth product of 5 MHz typical Industry-standard 8-lead dual pinout
NC 8 NC
9
00325-001
NC = NO CONNECT
Figure 1. 16-Lead SOIC (S-Suffix)
B
OUT A 1 8 V+
–IN A 2
+IN A 3
V– 4
A
OP270
7 OUT B
00325-002
6 –IN B
5 +IN B
The OP270 is a high performance, monolithic, dual operational amplifier with exceptionally low voltage noise density (5 nV/√Hz maximum at 1 kHz). It offers comparable performance to the industry-standard OP27 from Analog Devices, Inc.
The OP270 features an input offset voltage of less than 75 μV and an offset drift of less than 1 μV/°C, guaranteed over the full military temperature range. Open-loop gain of the OP270 is more than 1,500,000 into a 10 kΩ load, ensuring excellent gain accuracy and linearity, even in high gain applications. The input bias current is less than 20 nA, which reduces errors due to signal source resistance. With a common-mode rejection (CMR) of greater than 106 dB and a power supply rejection ratio (PSRR) of less than 3.2 μV/V, the OP270 significantly reduces errors due to ground noise and power supply fluctuations. The power
Figure 2. 8-Lead PDIP (P-Suffix) 8-Lead CERDIP
(Z-Suffix)
consumption of the dual OP270 is one-third less than two OP27 devices, a significant advantage for power conscious applications. The OP270 is unity-gain stable with a gain bandwidth product of 5 MHz and a slew rate of 2.4 V/μs.
The OP270 offers excellent amplifier matching, which is important for applications such as multiple gain blocks, low noise instrumentation amplifiers, dual buffers, and low noise active filters.
The OP270 conforms to the industry-standard 8-lead CERDIP and PDIP pinouts.
For higher speed applications, the ADA4004-2 or the AD8676 are recommended. For a quad op amp, see the OP470 data sheet.
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibilityis assumedby Analog Devicesforitsuse, norforanyinfringements ofpatents orother rightsofthirdpartiesthatmayresultfromitsuse.Specificationssubjecttochangewithoutnotice.No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 ©2001–2015 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com
Typical Performance Characteristics 6
Total Noise and Source Resistance 12
Capacitive Load Driving and Power Supply Considerations 15
Unity-Gain Buffer Applications 15
Five-Band, Low Noise, Stereo Graphic Equalizer 16
Dual Programmable Gain Amplifier 17
10/15—Rev. E to Rev. F
Changes to General Description Section 1
Changes to Supply Voltage Parameter and Differential Input Voltage Parameter, Table 3 5
Deleted Table 4; Renumbered Sequentially 5
2/10—Rev. D to Rev. E
Change to Input Noise Current Density Parameter, Table 1 3
Change to Figure 18 8
2/09—Rev. C to Rev. D
Updated Format..................................................................Universal
Reorganized Layout............................................................Universal
Changes to Figure 7 6
Changes to Figure 22 9
Deleted Applications Heading 11
Changes to Figure 44 17
Changes to Figure 46 18
Updated Outline Dimensions 19
Changes to Ordering Guide 20
4/03—Rev. B to Rev. C
Deletion of OP270A model............................................... Universal Edits to Features 1
Changes to Specifications 2
Deletion of Wafer Limits and Dice Characteristics 4
Changes to Absolute Maximum Ratings 4
Changes to Ordering Guide 4
Changes to Equations in Noise Measurements section 10
Change to Figure 10 11
Updated Outline Dimensions 14
11/02—Rev. A to Rev. B
Updated Ordering Guide 15
9/02—Rev. 0 to Rev. A
Edits to Absolute Maximum Ratings 5
Edits to Ordering Guide 15
2/01—Revision 0: Initial Version
VS = ±15 V, TA = 25°C, unless otherwise noted.
Table 1.
Parameter | Symbol | Test Conditions | Min | Typ | Max | Min | Typ | Max | Min | Typ | Max | Unit |
Input Offset Voltage | VOS | 10 | 75 | 20 | 150 | 50 | 250 | μV | ||||
Input Offset Current | IOS | VCM = 0 V | 1 | 10 | 3 | 15 | 5 | 20 | nA | |||
Input Bias Current | IB | VCM = 0 V | 5 | 20 | 10 | 40 | 15 | 60 | nA | |||
Input Noise Voltage1 | en p-p | 0.1 Hz to 10 Hz | 80 | 200 | 80 | 200 | 80 | nV p-p | ||||
Input Noise Voltage Density2 | en | fO = 10 Hz | 3.6 | 6.5 | 3.6 | 6.5 | 3.6 | nV/√Hz | ||||
en | fO = 100 Hz | 3.2 | 5.5 | 3.2 | 5.5 | 3.2 | nV/√Hz | |||||
en | fO = 1 kHz | 3.2 | 5.0 | 3.2 | 5.0 | 3.2 | nV/√Hz | |||||
Input Noise Current Density | in | fO = 10 Hz | 1.1 | 1.1 | 1.1 | pA/√Hz | ||||||
in | fO = 100 Hz | 0.7 | 0.7 | 0.7 | pA/√Hz | |||||||
in | fO = 1 kHz | 0.6 | 0.6 | 0.6 | pA/√Hz | |||||||
Large-Signal Voltage Gain | AVO | VO = ±10 V, | 1500 | 2300 | 1000 | 1700 | 750 | 1500 | V/mV | |||
RL = 10 kΩ | ||||||||||||
VO = ±10 V, | 750 | 1200 | 500 | 900 | 350 | 700 | V/mV | |||||
RL = 2 kΩ | ||||||||||||
Input Voltage Range3 | IVR | ±12 | ±12.5 | ±12 | ±12.5 | ±12 | ±12.5 | V | ||||
Output Voltage Swing | VO | RL ≥ 2 kΩ | ±12 | ±13.5 | ±12 | ±13.5 | ±12 | ±13.5 | V | |||
Common-Mode Rejection | CMR | VCM = ±11 V | 106 | 125 | 100 | 120 | 90 | 110 | dB | |||
Power Supply Rejection | PSRR | VS = ±4.5 V | 0.56 | 3.2 | 1.0 | 5.6 | 1.5 | 5.6 | μV/V | |||
Ratio | to ±18 V | |||||||||||
Slew Rate | SR | 1.7 | 2.4 | 1.7 | 2.4 | 1.7 | 2.4 | V/μs | ||||
Supply Current | ISY | No load | 4 | 6.5 | 4 | 6.5 | 4 | 6.5 | mA | |||
(All Amplifiers) | ||||||||||||
Gain Bandwidth Product | GBP | 5 | 5 | 5 | MHz | |||||||
Channel Separation1 | CS | VO = ±20 V p-p, | 125 | 175 | 125 | 175 | 175 | dB | ||||
fO = 10 Hz | ||||||||||||
Input Capacitance | CIN | 3 | 3 | 3 | pF | |||||||
Input Resistance | ||||||||||||
Differential Mode | RIN | 0.4 | 0.4 | 0.4 | MΩ | |||||||
Common Mode | RINCM | 20 | 20 | 20 | GΩ | |||||||
Settling Time | tS | AV = +1, 10 V, | 5 | 5 | 5 | μs | ||||||
step to 0.01% |
1 Guaranteed but not 100% tested.
2 Sample tested.
3 Guaranteed by CMR test.
VS = ±15 V, −40°C ≤ TA ≤ 85°C, unless otherwise noted.
Table 2.
Parameter | Symbol | Test Conditions | Min | Typ | Max | Min | Typ | Max | Min | Typ | Max | Unit |
Input Offset Voltage | VOS | 25 | 150 | 45 | 275 | 100 | 400 | μV | ||||
Average Input Offset | TCVOS | 0.2 1 | 0.4 2 | 0.7 3 | μV/°C | |||||||
Voltage Drift | ||||||||||||
Input Offset Current | IOS | VCM = 0 V | 1.5 | 30 | 5 | 40 | 15 | 50 | nA | |||
Input Bias Voltage | IB | VCM = 0 V | 6 | 60 | 15 | 70 | 19 | 80 | nA | |||
Large-Signal Voltage Gain | AVO | VO = ±10 V, | 1000 | 1800 | 600 | 1400 | 400 | 1250 | V/mV | |||
RL = 10 kΩ | ||||||||||||
AVO | VO = ±10 V, | 500 | 900 | 300 | 700 | 225 | 670 | V/mV | ||||
RL = 2 kΩ | ||||||||||||
Input Voltage Range1 | IVR | ±12 | ±12.5 | ±12 | ±12.5 | ±12 | ±12.5 | V | ||||
Output Voltage Swing | VO | RL ≥ 2 kΩ | ±12 | ±13.5 | ±12 | ±13.5 | ±12 | ±13.5 | V | |||
Common-Mode Rejection | CMR | VCM = ±11 V | 100 | 120 | 94 | 115 | 90 | 100 | dB | |||
Power Supply Rejection | PSRR | VS = ±4.5 V to ±18 V | 0.7 | 5.6 | 1.8 | 10 | 2.0 | 1.5 | μV/V | |||
Ratio | ||||||||||||
Supply Current | ISY | No load | 4.4 | 7.2 | 4.4 | 7.2 | 4.4 | 7.2 | mA | |||
(All Amplifiers) |
1 Guaranteed by CMR test.
Table 3.
Parameter | Rating |
Supply Voltage | ±18 V |
Differential Input Voltage1 | ±1.0 V |
Differential Input Current1 | ±25 mA |
Input Voltage | Supply voltage |
Output Short-Circuit Duration | Continuous |
Storage Temperature Range | −65°C to +150°C |
Lead Temperature Range (Soldering, 60 sec) | 300°C |
Junction Temperature (TJ) | −65°C to +150°C |
Operating Temperature Range | −40°C to +85°C |
1 The OP270 inputs are protected by back-to-back diodes. To achieve low noise performance, current-limiting resistors are not used. If the differential voltage exceeds +10 V, the input current should be limited to ±25 mA.
Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability.
TA = 25°C VS = ±15V
10
9
8
VOLTAGE NOISE DENSITY (nV/√Hz)
7
6
5
4
3
10
TA = 25°C
CURRENT NOISE DENSITY (pA/√Hz)
VS = ±15V
1
1/f CORNER = 5Hz
2
00352-004
1
1 10 100 1k FREQUENCY (Hz)
Figure 3. Voltage Noise Density vs. Frequency
1/f CORNER = 200Hz
00352-007
0.1
10 100 1k 10k FREQUENCY (Hz)
Figure 6. Current Noise Density vs. Frequency
TA = 25°C
VS = ±15V | |||||||
5 40
VOLTAGE NOISE DENSITY (nV/√Hz)
30
4
AT 10kHz
3 AT 1kHz
2
20
VOLTAGE (µV)
10
0
–10
00352-008
–20
00352-005
1
0 ±5 ±10 ±15 ±20
–30
–75 –50 –25 0
25 50 75 100 125
SUPPLY VOLTAGE (V)
Figure 4. Voltage Noise Density vs. Supply Voltage
TEMPERATURE (°C)
Figure 7. Input Offset Voltage vs. Temperature
TA = 25°C VS = ±15V | ||||
TA = 25°C TS = ±15V | |||||||||
0.1Hz TO 10Hz NOISE 5
NOISE VOLTAGE (100nV/DIV)
CHANGE IN OFFSET VOLTAGE (µA)
4
3
2
1
TIME (1 sec/DIV)
0
00352-006
00352-009
0 1 2 3 4 5
TIME (Minutes)
Figure 5. 0.1 Hz to 10 Hz Input Voltage Noise Figure 8. Warm-Up Offset Voltage Drift
VS = ±15V VCM = 0V | |||||||
7
INPUT BIAS CURRENT (nA)
6
5
4
3
2
–75 –50 –25 0
00352-010
25 50 75 100 125
130
120
110
100
90
CMR (dB)
80
70
60
50
40
30
20
10
1 10
100
TA = 25°C VS = ±15V
00352-013
1k 10k 100k 1M
TEMPERATURE (°C)
Figure 9. Input Bias Current vs. Temperature
FREQUENCY (Hz)
Figure 12. CMR vs. Frequency
VS = ±15V VCM = 0V | ||||||||
5 6
INPUT OFFSET CURRENT (nA)
TOTAL SUPPLY CURRENT (mA)
4
5
3
+125°C
+25°C
–55°C
4
2
3
00352-011
1
0
–75 –50 –25 0
25 50 75 100 125
2
00352-014
0 ±5 ±10 ±15 ±20
TEMPERATURE (°C)
Figure 10. Input Offset Current vs. Temperature
SUPPLY VOLTAGE (V)
Figure 13. Total Supply Current vs. Supply Voltage
TA = +25°C VS = ±15V | |||||||||
VS = ±15V | |||||||
7 8
7
INPUT BIAS CURRENT (nA)
TOTAL SUPPLY CURRENT (mA)
6
6
5 5
4
4 3
2
3
00352-012
00352-015
1
2
–10.0 –5.0 0 5.0
10.0
0
–75 –50 –25 0
25 50 75 100 125
–12.5 –7.5 –2.5 2.5
COMMON-MODE VOLTAGE (V)
7.5 12.5
TEMPERATURE (°C)
Figure 11. Input Bias Current vs. Common-Mode Voltage Figure 14. Total Supply Current vs. Temperature
140
120
100
PSR (dB)
80
60
40
20
25
20
OPEN-LOOP GAIN (dB)
15
10
5
GAIN
0
–5
PHASE
80
TA = 25°C VS = ±15V
PHASE SHIFT (Degrees)
100
120
PHASE MARGIN = 62°
140
160
180
TA = 25°C | ||||||||||||||||||||||||||||
–PSR | ||||||||||||||||||||||||||||
+PSR | ||||||||||||||||||||||||||||
0
1 10
100
00352-016
1k 10k 100k 1M 10M 100M FREQUENCY (Hz)
–10
00352-019
1 2 3 4 5 6 7 8 9 10
FREQUENCY (MHz)
Figure 15. PSR vs. Frequency Figure 18. Open-Loop Gain and Phase Shift vs. Frequency
140
120
OPEN-LOOP GAIN (dB)
100
80
60
40
20
5000
OPEN-LOOP GAIN (V/mA)
4000
3000
2000
1000
TA = 25°C VS = ±15V | ||||||||||||||||||||||||||||
0
1 10
100
00352-017
1k 10k 100k 1M 10M 100M FREQUENCY (Hz)
0
00352-020
0 ±5 ±10 ±15 ±20 ±25
SUPPLY VOLTAGE (V)
Figure 16. Open-Loop Gain vs. Frequency Figure 19. Open-Loop Gain vs. Supply Voltage
80 80
TA = 25°C
GAIN BANDWIDTH PRODUCT (MHz)
VS = ±15V 8
60
CLOSED-LOOP GAIN (dB)
PHASE MARGIN (Degrees)
70
7
40
Ф
60 6
20
5
50 GBP
0
00352-018
00352-021
4
–20
1k 10k 100k 1M 10M
40
–75 –50 –25 0
25 50 75 100 125 150
FREQUENCY (Hz)
Figure 17. Closed-Loop Gain vs. Frequency
TEMPERATURE (°C)
Figure 20. Phase Margin and Gain Bandwidth Product vs. Temperature
28
TA = 25°C
100
TA = 25°C
VS = ±15V
MAXIMUM OUTPUT SWING (V)
24 THD = 1%
20
VS = ±15V
OUTPUT IMPEDANCE (Ω)
75
AV = 1
16
50
12
AV = 100
8
25
AV = 10
00352-022
00352-025
4
0
1k 10k 100k 1M 10M FREQUENCY (Hz)
Figure 21. Maximum Output Swing vs. Frequency
0
1k 10k 100k 1M 10M FREQUENCY (Hz)
Figure 24. Output Impedance vs. Frequency
15
TA = 25°C
MAXIMUM OUTPUT VOLTAGE (V)
14 VS = ±15V POSITIVE SWING
13
12
11 NEGATIVE
SWING
10
9
8
7
6
2.8
VS = ±15V | |||||||
–SR | |||||||
+SR | |||||||
2.7
SLEW RATE (V/µs)
2.6
2.5
2.4
00352-026
2.3
00352-023
5
100 1k 10k
2.2
–75 –50 –25 0
25 50 75 100 125
LOAD RESISTANCE (Ω)
Figure 22. Maximum Output Voltage vs. Load Resistance
TEMPERATURE (°C)
Figure 25. Slew Rate vs. Temperature
50
TA = 25°C
SMALL-SIGNAL OVERSHOOT (%)
VS = ±15V VIN = 100mV
40 AV = +1
30
20
10
00352-024
0
190
180
CHANNEL SEPARATION (dB)
170
160
150
140
130
120
110
100
90
80
70
TA = 25°C VS = ±15V
00352-027
VO = 20V p-p TO 10kHz
0 200 400 600 800 1000
1 10
100
1k 10k 100k 1M
CAPACITIVE LOAD (pF)
Figure 23. Small-Signal Overshoot vs. Capacitive Load
FREQUENCY (Hz)
Figure 26. Channel Separation vs. Frequency
TOTAL HARMONIC DISTORTION (%)
0.1
0.01
TA = 25°C VS = ±15V VO = 20V p-p RL = 2kΩ
TA = 25°C VS = ±15V AV = +1 RL = 2kΩ | |||||||||
50 | mV | 200 | ns |
AV = 10
00352-030
AV = 1
00352-028
0.001
10 100 1k 10k FREQUENCY (Hz)
Figure 27. Total Harmonic Distortion vs. Frequency
Figure 29. Small-Signal Transient Response
TA = 25°C VS = ±15V AV = +1 RL = 2kΩ | |||||||||
5 | V | 20 | µs |
00352-029
Figure 28. Large-Signal Transient Response
5kΩ
500Ω
1/2
OP270
V1 20Vp-p
5kΩ
50Ω
1/2
OP270
V2
CHANNEL SEPARATION = 20 LOG
V1 V2/1000
00325-031
Figure 30. Channel Separation Test Circuit
+18V
100kΩ
200kΩ
100kΩ
8
2
1/2 1
OP270
3
6
1/2 7
OP270
5
4
00325-032
–18V
Figure 31. Burn-In Circuit
The OP270 is a very low noise dual op amp, exhibiting a typical voltage noise density of only 3.2 nV/√Hz at 1 kHz. Because the voltage noise is inversely proportional to the square root of the collector current, the exceptionally low noise characteristic of the OP270 is achieved in part by operating the input transistors at high collector currents. Current noise, however, is directly proportional to the square root of the collector current. As a result, the outstanding voltage noise density performance of the OP270 is gained at the expense of current noise performance, which is normal for low noise amplifiers.
To obtain the best noise performance in a circuit, it is vital to understand the relationships among voltage noise (en), current noise (in), and resistor noise (et).
Figure 33 also shows the relationship between total noise and source resistance, but at 10 Hz. Total noise increases more quickly than shown in Figure 32 because current noise is inversely proportional to the square root of frequency. In Figure 33, the current noise of the OP270 dominates the total noise when RS is greater than 5 kΩ.
Figure 32 and Figure 33 show that to reduce total noise, source resistance must be kept to a minimum. In applications with a high source resistance, the OP200, with lower current noise than the OP270, can provide lower total noise.
100
TOTAL NOISE (nV/√Hz)
OP200
The total noise of an op amp can be calculated by 10
En
where:
(en)2 (inRs )2 (et )2
OP270
En is the total input-referred noise.
en is the op amp voltage noise.
in is the op amp current noise.
et is the source resistance thermal noise.
RS is the source resistance.
The total noise is referred to the input and at the output is amplified by the circuit gain.
Figure 32 shows the relationship between total noise at 1 kHz and source resistance. When RS is less than 1 kΩ, the total noise is dominated by the voltage noise of the OP270. As RS rises above 1 kΩ, total noise increases and is dominated by resistor noise rather than by the voltage or current noise of the OP270. When RS exceeds 20 kΩ, the current noise of the OP270 becomes the major contributor to total noise.
100
RESISTOR NOISE ONLY
00352-034
1
100 1k 10k 100k SOURCE RESISTANCE (Ω)
Figure 33. Total Noise vs. Source Resistance (Including Resistor Noise) at 10 Hz
Figure 34 shows peak-to-peak noise vs. source resistance over the 0.1 Hz to 10 Hz range. At low values of RS, the voltage noise of the OP270 is the major contributor to peak-to-peak noise, with current noise becoming the major contributor as RS increases. The crossover point between the OP270 and the OP200 for peak-to-peak noise is at a source resistance of 17 kΩ.
1k
OP200
TOTAL NOISE (nV/√Hz)
PEAK-TO-PEAK NOISE (nV)
100
OP200
10
OP270
OP270
RESISTOR NOISE ONLY
RESISTOR NOISE ONLY
00352-033
1
100 1k 10k 100k SOURCE RESISTANCE (Ω)
Figure 32. Total Noise vs. Source Resistance (Including Resistor Noise) at 1 kHz
10
00352-035
100 1k 10k 100k SOURCE RESISTANCE (Ω)
Figure 34. Peak-to-Peak Noise (0.1 Hz to 10 Hz) vs. Source Resistance (Including Resistor Noise)
For reference, typical source resistances of some signal sources are listed in Table 4.
Table 4. Typical Source Resistances
Device | Source Impedance | Comments |
Strain Gage | <500 Ω | Typically used in low frequency applications. |
Magnetic Tapehead, Microphone | <1500 Ω | Low IB is very important to reduce self-magnetization problems when direct coupling is used. OP270 IB can be disregarded. |
Magnetic Phonograph Cartridge | <1500 Ω | Low IB is important to reduce self-magnetization problems in direct-coupled applications. OP270 does not introduce any self-magnetization problems. |
Linear Variable Differential Transformer | <1500 Ω | Used in rugged servo-feedback applications. The bandwidth of interest is 400 Hz to 5 kHz. |
R3 1.24kΩ
R1 5Ω
R2 OP270
5Ω DUT
R4 200Ω
OP27E
R5 909Ω
C1
2µF
R6 600Ω
R8
D1, D2 1N4148
OP27E
R9 306Ω
R10 65.4kΩ
C4 0.22µF
R11 65.4kΩ
C3 0.22µF
OP42E
R13 5.9kΩ
R14 4.99kΩ
e
OUT
C5
1µF
10kΩ
C2 0.032µF
R12 10kΩ
00325-036
GAIN = 50,000 VS = ±15V
Figure 35. Peak-to-Peak Voltage Noise Test Circuit (0.1 Hz to 10 Hz)
The circuit of Figure 35 is a test setup for measuring peak-to- peak voltage noise. To measure the 200 nV peak-to-peak noise specification of the OP270 in the 0.1 Hz to 10 Hz range, the
following precautions must be observed:
Noise Measurement—Noise Voltage Density
The circuit of Figure 37 shows a quick and reliable method for measuring the noise voltage density of dual op amps. The first amplifier is in unity gain, with the final amplifier in a noninverting gain of 101. Because the noise voltages of the amplifiers are
uncorrelated, they add in rms to yield
The device has to be warmed up for at least five minutes.
eOUT
101
enA
2 enB
2
As shown in the warm-up drift curve (see Figure 8), the offset voltage typically changes 2 μV due to increasing chip temperature after power-up. In the 10 sec measurement
interval, these temperature-induced effects can exceed tens
The OP270 is a monolithic device with two identical amplifiers. Therefore, the noise voltage densities of the amplifiers match, giving
of nanovolts.
eOUT
101
2e 2 101
2en
For similar reasons, the device has to be well shielded from air currents. Shielding also minimizes thermocouple effects.
Sudden motion in the vicinity of the device can also feed through to increase the observed noise.
The test time to measure noise of 0.1 Hz to 10 Hz should
1/2
n
R1 100Ω
R2 10kΩ
1/2 OP270
eOUT
not exceed 10 sec. As shown in the noise-tester frequency response curve of Figure 36, the 0.1 Hz corner is defined by only one pole. The test time of 10 sec acts as an additional
OP270
TO SPECTRUM ANALYZER
00325-038
eOUT (nV/√Hz) ≈ 101 (√2en) VS = ±15V
pole to eliminate noise contribution from the frequency band below 0.1 Hz.
A noise voltage density test is recommended when measuring noise on several units. A 10 Hz noise voltage density mea- surement correlates well with a 0.1 Hz to 10 Hz peak-to-peak noise reading because both results are determined by the
white noise and the location of the 1/f corner frequency.
Figure 37. Noise Voltage Density Test Circuit
Noise Measurement—Current Noise Density
The test circuit shown in Figure 38 can be used to measure current noise density. The formula relating the voltage output to the current noise density is
enOUT 2 2
Power should be supplied to the test circuit by well bypassed
i G
40 nV / Hz
low noise supplies, such as batteries. Such supplies will min- imize output noise introduced via the amplifier supply pins.
100
80
n RS
where:
G is a gain of 10,000.
RS = 100 kΩ source resistance.
R3 1.24kΩ
GAIN (dB)
60
R1 R2
5Ω 100kΩ
OP270
40 DUT
20
00352-037
R4
OP27E
R5 8.06kΩ
enOUT
TO SPECTRUM ANALYZER
00325-039
GAIN = 10,000
200Ω
0
VS = ±15V
0.01 0.1 1 10 100
FREQUENCY (Hz)
Figure 36. 0.1 Hz to 10 Hz Peak-to-Peak Voltage Noise Test Circuit Frequency Response
Figure 38. Current Noise Density Test Circuit
The OP270 is unity-gain stable and capable of driving large capacitive loads without oscillating. Nonetheless, good supply bypassing is highly recommended. Proper supply bypassing reduces problems caused by supply line noise and improves the capacitive load driving capability of the OP270.
In the standard feedback amplifier, the output resistance of the op amp combines with the load capacitance to form a low-pass filter that adds phase shift in the feedback network and reduces stability. A simple circuit to eliminate this effect is shown in Figure 39. The components C1 and R3 decouple the amplifier from the load capacitance and provide additional stability. The values of C1 and R3 shown in Figure 39 are for a load capacitance of up to 1000 pF when used with the OP270.
V+
When Rf ≤ 100 Ω and the input is driven with a fast, large signal pulse (>1 V), the output waveform looks like the one in Figure 40.
During the fast feedthrough-like portion of the output, the input protection diodes effectively short the output to the input, and a current, limited only by the output short-circuit protection, is drawn by the signal generator. With Rf ≥ 500 Ω, the output is capable of handling the current requirements (IL ≤ 20 mA at 10 V);
the amplifier stays in its active mode and a smooth transition occurs.
When Rf > 3 kΩ, a pole created by Rf and the input capacitance (3 pF) of the amplifier creates additional phase shift and reduces phase margin. A small capacitor (20 pF to 50 pF) in parallel with Rf helps eliminate this problem.
Rf
+ C2
C3 10µF 0.1µF
OP270 2.4V/µs
00325-041
R2
R1
VIN
OP270
C1 200pF
R3 50Ω
VOUT C1
1000pF
C5 0.1µF
V–
C4
+ 10µF
00325-040
PLACE SUPPLY DECOUPLING CAPACITOR AT OP270
Figure 39. Driving Large Capacitive Loads
The simple amplifier depicted in Figure 41 utilizes a monolithic dual operational amplifier and a few resistors to substantially reduce phase error compared with conventional amplifier designs. At a given gain, the frequency range for a specified phase accuracy is more than a decade greater than that of a standard single op amp amplifier.
The low phase error amplifier performs second-order fre- quency compensation through the response of Op Amp A2 in the feedback loop of A1. Both op amps must be extremely well matched in frequency response. At low frequencies, the A1
feedback loop forces V2/(K1 + 1) = VIN. The A2 feedback loop forces V /(K1 + 1) = V /(K1 + 1), yielding an overall transfer
0
SINGLE OP AMP. CONVENTIONAL DESIGN | ||||||||||||||||||
CASCADED (TWO STAGES) | ||||||||||||||||||
LOW PHASE ERROR AMPLIFIER | ||||||||||||||||||
–1
PHASE SHIFT (Degrees)
–2
–3
–4
–5
–6
–7
0.001 0.005 0.01
0.05
0.1
00352-043
0.5 1
O 2 FREQUENCY RATIO (1/βω)(ω/ωT)
function of VO/VIN = K1 + 1. The dc gain is determined by the
resistor divider at the output, VO, and is not directly affected by the resistor divider around A2. Note that, like a conventional single op amp amplifier, the dc gain is set by resistor ratios only. Minimum gain for the low phase error amplifier is 10.
R2 R2 = R1
R2 K2
1/2
Figure 42. Phase Error Comparison
The graphic equalizer circuit shown in Figure 43 provides 15 dB of boost or cut over a five-band range. Signal-to-noise ratio over a 20 kHz bandwidth is better than 100 dB and referred to a 3 V rms input. Larger inductors can be replaced by active inductors, but consequently reduces the signal-to-noise ratio.
OP270E V2
A2
VIN
C1 0.47µF
1/2
R2 3.3kΩ
1/2
R1
R1 K1
R1 47kΩ
OP270E 1/2
OP270E
R4
R14
100Ω
VOUT
VIN
OP270E A1
R3 680Ω
C2
6.8µF L1
+
1kΩ
60Hz
R13 3.3kΩ
ASSUME A1 AND A2 ARE MATCHED.
ωT
VO VO = (K1 + 1)VIN
TANTALUM 1H
R5 C3
R6
1kΩ
AO(s) = s
680Ω
1µF L2
+
200Hz
00325-042
Figure 41. Low Phase Error Amplifier
Figure 42 compares the phase error performance of the low
TANTALUM
C4
600mH
R8
1kΩ
R7 0.22µF L3
800Hz
phase error amplifier with a conventional single op amp amplifier and a cascaded two-stage amplifier. The low phase
680Ω +
180mH
R10
1kΩ
error amplifier shows a much lower phase error, particularly for frequencies where ω/βωT < 0.1. For example, a phase error of
−0.1° occurs at 0.002 ω/βωT for the single op amp amplifier, but
at 0.11 ω/βωT for the low phase error amplifier.
R9 680Ω
C5
0.047µF L4
+
60mH
C6
R12
1kΩ
3kHz
R11
0.022µF L5
10kHz
00325-044
680Ω +
10mH
Figure 43. Five-Band, Low Noise Graphic Equalizer
Figure 44 uses a DAC8221 (a dual 12-bit CMOS DAC) to pan a signal between two channels. One channel is formed by the current output of DAC A driving one-half of an OP270 in a current-to-voltage converter configuration. The other channel is formed by the complementary output current of DAC A,
DAC8221P
+5V 21
VDD
RFBA 3
+15V
0.01µF
+
10µF
–
which normally flows to ground through the AGND pin. This complementary current is converted to a voltage by the other
VIN
4 VREFA
DAC A
IOUTA 2
2 8
1/2
OP270GP
1 OUT
half of the OP270, which also holds AGND at virtual ground.
Gain error due to mismatching between the internal DAC ladder resistors and the current-to-voltage feedback resistors is eliminated by using feedback resistors internal to the DAC8221. Only DAC A passes a signal; DAC B provides the second
feedback resistor. With VREFB unconnected, the current-to- voltage converter, using R , is accurate and not influenced by
DAC DATA BUS PINS 6 (MSB) TO 17 (LSB)
22 VREFB
NC DAC B
18
AGND 1
RFBB 23
IOUTB 24
3
0.1µF
4
–15V
6
1/2 7
OP270GP
5
+
10µF
–
OUT
FBB
digital data reaching DAC B. Distortion of the digital panning control is less than 0.002% over the 20 Hz to 20 kHz audio
WRITE
DAC A/DAC B
19 CS
range. Figure 45 shows the complementary outputs for a 1 kHz input signal and a digital ramp applied to the DAC data input.
The dual OP270 and the DAC8221 (a dual 12-bit CMOS DAC) can be combined to form a space-saving, dual programmable amplifier. The digital code present at the DAC, which is easily set by a microprocessor, determines the ratio between the internal feedback resistor and the resistance that the DAC ladder presents to the op amp feedback loop. Gain of each amplifier is
CONTROL 20 WR
5 | V 5 | V | 1 | ms |
DGND 5
00325-045
Figure 44. Digital Panning Control
VO VIN
4096
n
where n is the decimal equivalent of the 12-bit digital code present at the DAC.
If the digital code present at the DAC consists of all 0s, the feedback loop opens, causing the op amp output to saturate. A 20 MΩ resistor placed in parallel with the DAC feedback loop eliminates this problem with only a very small reduction in gain accuracy.
A OUT
00352-046
Figure 45. Digital Panning Control Output
+15V
+5V
DAC8221P
21
VDD
VREFA 4
0.01µF
3 RFBA
VINA
DAC A
IOUTA 2
AGND 1
20MΩ
2 8
1/2
OP270EZ
3
4
+
10µF
–
1
VOUTA
+
23
VINB
RFBB
DAC B
IOUTB 24
–15V
6
0.1µF
10µF
–
WRITE
DAC DATA BUS PINS 6 (MSB) TO 17 (LSB)
18
19
20MΩ
VREFB 22
1/2
OP270GP
5
7
VOUTB
CONTROL 20
DGND 5
00325-047
Figure 46. Dual Programmable Gain Amplifier
V+
BIAS
OUT
–IN +IN
00325-003
V–
Figure 47. Simplified Schematic (One of Two Amplifiers Is Shown)
0.005 (0.13) MIN
0.055 (1.40) MAX
8 5
0.310 (7.87)
0.220 (5.59)
1 4
0.100 (2.54) BSC
0.405 (10.29) MAX 0.320 (8.13)
0.290 (7.37)
0.200 (5.08)
MAX
0.200 (5.08)
0.125 (3.18)
0.023 (0.58)
0.014 (0.36) 0.070 (1.78)
0.030 (0.76)
0.060 (1.52)
0.015 (0.38)
0.150 (3.81) MIN
SEATING PLANE
15°
0°
0.015 (0.38)
0.008 (0.20)
CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
Figure 48. 8-Lead Ceramic Dual In-Line Package [CERDIP]
Z-Suffix (Q-8)
Dimensions shown in inches and (millimeters)
0.400 (10.16)
0.365 (9.27)
0.355 (9.02)
0.210 (5.33)
MAX
8
1
0.100 (2.54) BSC
0.280 (7.11)
5
0.250 (6.35)
4
0.240 (6.10)
0.325 (8.26)
0.310 (7.87)
0.300 (7.62)
0.060 (1.52)
MAX
0.195 (4.95)
0.130 (3.30)
0.115 (2.92)
0.015
0.150 (3.81)
(0.38)
0.015 (0.38)
0.130 (3.30) MIN
0.115 (2.92) SEATING
GAUGE
PLANE 0.014 (0.36)
0.022 (0.56)
0.018 (0.46)
0.014 (0.36)
PLANE
0.005 (0.13) MIN
0.430 (10.92) MAX
0.010 (0.25)
0.008 (0.20)
0.070 (1.78)
0.060 (1.52)
0.045 (1.14)
COMPLIANT TO JEDEC STANDARDS MS-001
070606-A
CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. CORNER LEADS MAY BE CONFIGURED AS WHOLE OR HALF LEADS.
Figure 49. 8-Lead Plastic Dual In-Line Package [PDIP] Narrow Body
P-Suffix (N-8)
Dimensions shown in inches and (millimeters)
10.50 (0.4134)
10.10 (0.3976)
16
9
7.60 (0.2992)
7.40 (0.2913)
8
1
10.65 (0.4193)
10.00 (0.3937)
0.30 (0.0118)
0.10 (0.0039)
COPLANARITY 0.10
0.51 (0.0201)
0.31 (0.0122)
2.35 (0.0925)
SEATING PLANE
8°
0°
0.33 (0.0130)
0.20 (0.0079)
45°
1.27 (0.0500) | 0.75 (0.0295) | ||
BSC | 2.65 (0.1043) | 0.25 (0.0098) | |
1.27 (0.0500)
0.40 (0.0157)
032707-B
COMPLIANT TO JEDEC STANDARDS MS-013- AA CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
Figure 50. 16-Lead Standard Small Outline Package [SOIC_W] Wide Body
S-Suffix (RW-16)
Dimensions shown in millimeters and (inches)
Model1 | TA = +25°C VOS Max (μV) | θJC (°C/W) | θJA 2 (°C/W) | Temperature Range | Package Description | Package Option |
OP270EZ | 75 | 12 | 134 | −40°C to +85°C | 8-Lead CERDIP | Q-8 (Z-Suffix) |
OP270FZ | 150 | 12 | 134 | −40°C to +85°C | 8-Lead CERDIP | Q-8 (Z-Suffix) |
OP270GP | 250 | 37 | 96 | −40°C to +85°C | 8-Lead PDIP | N-8 (P-Suffix) |
OP270GPZ | −40°C to +85°C | 8-Lead PDIP | N-8 (P-Suffix) | |||
OP270GS | 250 | 27 | 92 | −40°C to +85°C | 16-Lead SOIC_W | RW-16 (S-Suffix) |
OP270GS-REEL | −40°C to +85°C | 16-Lead SOIC_W | RW-16 (S-Suffix) | |||
OP270GSZ | −40°C to +85°C | 16-Lead SOIC_W | RW-16 (S-Suffix) | |||
OP270GSZ-REEL | −40°C to +85°C | 16-Lead SOIC_W | RW-16 (S-Suffix) |
1 The OP270GPZ, OP270GSZ, and OP270GSZ-REEL are RoHS compliant parts.
2 θJAis specified for worst-case mounting conditions, that is, θJA is specified for device in socket for CERDIP and PDIP packages; θJAis specified for device soldered to printed circuit board for SOIC package.
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