SBOS924D – SEPTEMBER 2018 – REVISED JANUARY 2020
Precision super beta input performance:
Low offset voltage: 5 µV (typical)
Ultra-low drift: 0.1 µV/°C (typical)
Low input bias current: 0.3 nA (typical)
Ultra-low noise:
Low 0.1-Hz to 10-Hz noise: 90 nVPP
Low voltage noise: 2.2 nV/√Hz at 1 kHz
High CMRR: 132 dB (minimum)
Gain bandwidth product: 18 MHz
Slew rate: 6.4 V/µs
Low quiescent current: 2.5 mA/channel (maximum)
Short-circuit current: ±65 mA
Wide supply range: ±2.25 V to ±18 V
No phase reversal
Rail-to-rail output
Description
The OPA2210 is the next generation of OPA2209 operational amplifier (op amp). The OPA2210 precision operational amplifier is built on TI's precision super beta complementary bipolar semiconductor process, which offers ultra-low flicker noise, low offset voltage, and low offset voltage temperature drift.
The OPA2210 achieves very low voltage noise density (2.2 nV/√Hz) while consuming only 2.5 mA (maximum) per amplifier. This device also offers rail- to-rail output swing, which helps to maximize dynamic range.
In precision data acquisition applications, the OPA2210 provides fast settling time to 16-bit accuracy, even for 10-V output swings. Excellent ac performance, combined with only 35 µV (maximum) of offset and 0.6 µV/°C (maximum) drift over temperature, makes the OPA2210 very suitable for high-speed, high-precision applications.
The OPA2210 is specified over a wide dual power- supply range of ±2.25 V to ±18 V, or single-supply operation from 4.5 V to 36 V and is specified from
–40°C to 125°C.
The OPA2210 comes in 8-pin SOIC, VSSOP, and WSON packages.
PART NUMBER | PACKAGE | BODY SIZE (NOM) |
OPA2210 | SOIC (8) | 4.90 mm × 3.91 mm |
VSSOP (8) | 3.00 mm × 3.00 mm | |
WSON (8) (preview) | 3.00 mm × 3.00 mm |
For all available packages, see the package option addendum at the end of the data sheet.
OPA2210 0.1-Hz to 10-Hz Noise OPA2210 Offset Voltage Drift Distribution
20%
Input Voltage Noise (50 nV/div)
17.5%
Total Amplifiers (%)
15%
12.5%
10%
7.5%
5%
2.5%
Time (1 s/div)
0
-0.6 -0.5 -0.4 -0.3 -0.2 -0.1 0 0.1 0.2 0.3 0.4 0.5 0.6
Offset Voltage Drift (V/C)
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA.
Features 1
Applications 1
Description 1
Revision History 2
Pin Configuration and Functions 3
Specifications 4
Detailed Description 14
Application and Implementation 18
Power Supply Recommendations 23
Layout 23
Device and Documentation Support 24
Device Support 24
Documentation Support 25
Receiving Notification of Documentation Updates 25 11.4 Support Resources 25
Mechanical, Packaging, and Orderable Information 25
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision C (September 2019) to Revision D Page
Added OPA2210 DRG package to data sheet as advanced information (preview) 1
Changes from Revision B (March 2019) to Revision C Page
Changed super-ß to super beta for easier searching 1
Added SOIC package 1
Changes from Revision A (December 2018) to Revision B Page
Changed "OPAx145" to "OPA2210" 18
Fixed link to TIDA-01427 21
Changes from Original (September 2018) to Revision A Page
First release of production-data data sheet 1
Pin Configuration and Functions
D, DGK, and DRG(1) Packages 8-Pin SOIC, VSSOP, and WSON
Top View
OUT A 1
IN A 2
+IN A 3
V 4
8 V+
A 7 OUT B
B 6 IN B
5 +IN B
DRG package is preview.
Pin Functions
PIN | I/O | DESCRIPTION | |
NAME | NO. | ||
–IN A | 2 | I | Inverting input, channel A |
+IN A | 3 | I | Noninverting input, channel A |
–IN B | 6 | I | Inverting input, channel B |
+IN B | 5 | I | Noninverting input, channel B |
OUT A | 1 | O | Output, channel A |
OUT B | 7 | O | Output, channel B |
V– | 4 | — | Negative (lowest) power supply |
V+ | 8 | — | Positive (highest) power supply |
over operating free-air temperature range (unless otherwise noted)(1)
MIN MAX | UNIT | |||
Voltage | Supply voltage, VS = (V+) – (V–) | 40 | V | |
Signal input pins(2) | (V–) – 0.5 (V+) + 0.5 | |||
Signal input pins | Differential | 1 | ||
Current | Signal input pins(2) | –10 10 | mA | |
Output short circuit(3) | Continuous | |||
Temperature | Junction, TJ | 150 | °C | |
Storage temperature, Tstg | –65 150 |
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the de vice. Theseare stress ratings only, which do not imply functional operation of the device at these or anyother conditions beyond those indicated under Recommended OperatingConditions. Exposure to absolute-maximum-rated conditions for extended periods mayaffect device reliability.
For input voltages beyond the power-supply rails, voltage orcurrent must be limited.
Short circuit to ground, one amplifier per package.
VALUE | UNIT | |||
V(ESD) | Electrostatic discharge | Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) | ±4000 | V |
Charged-device model (CDM), per JEDEC specification JESD22-C101(2) | ±1500 |
JEDEC document JEP155 states that 500-V HBM allows safemanufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safemanufacturing with a standard ESD control process.
Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN MAX | UNIT | |
Specified voltage, VS | ±2.25 ±18 | V |
Specified temperature | –40 125 | °C |
Operating temperature, TA | –55 150 | °C |
THERMAL METRIC(1) | OPA2210 | UNIT | ||
D (SOIC) | DGK (VSSOP) | |||
8 PINS | 8 PINS | |||
RθJA | Junction-to-ambient thermal resistance | 126.1 | 132.7 | °C/W |
RθJC(top) | Junction-to-case (top) thermal resistance | 65.7 | 38.5 | °C/W |
RθJB | Junction-to-board thermal resistance | 69.5 | 52.1 | °C/W |
ψJT | Junction-to-top characterization parameter | 17.4 | 2.4 | °C/W |
ψJB | Junction-to-board characterization parameter | 68.9 | 52.8 | °C/W |
RθJC(bot) | Junction-to-case (bottom) thermal resistance | n/a | n/a | °C/W |
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.
at VS = ±15 V, TA = 25°C, RL = 10 kΩ connected to midsupply, and VCM =VOUT = midsupply (unless otherwise noted)
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | ||
OFFSET VOLTAGE | |||||||
VOS | Input offset voltage | VS = ±15 V, VCM = 0 V | ±5 | ±35 | µV | ||
dVOS/dT | Input offset voltage drift | TA = –40°C to 125°C | ±0.1 | ±0.5 | µV/°C | ||
VOS-matching | Input offset voltage matching | ±5 | ±35 | µV | |||
PSRR | vs power supply | VS = ±2.25 V to ±18 V | TA = 25°C | 0.05 | 0.5 | µV/V | |
TA = –40°C to 125°C | ±1 | ||||||
Channel separation | DC | ±0.1 | µV/V | ||||
INPUT BIAS OPERATION | |||||||
IB | Input bias current | VCM = 0 V | TA = 25°C | ±0.3 | ±2 | nA | |
TA = –40°C to 85°C | ±4 | ||||||
TA = –40°C to 125°C | ±7 | ||||||
IOS | Input offset current | VCM = 0 V | TA = 25°C | ±0.1 | ±2 | nA | |
TA = –40°C to 85°C | ±4 | ||||||
TA = –40°C to 125°C | ±7 | ||||||
NOISE | |||||||
en p-p | Input voltage noise | f = 0.1 Hz to 10 Hz | 0.09 | µVPP | |||
en | Noise density | f = 10 Hz | 2.5 | nV/√Hz | |||
f = 100 Hz | 2.25 | ||||||
f = 1 kHz | 2.2 | ||||||
In | Input current noise density | f = 1 kHz | 400 | fA/√Hz | |||
INPUT VOLTAGE RANGE | |||||||
VCM | Common-mode voltage range | (V–) + 1.5 | (V+) – 1.5 | V | |||
CMRR | Common-mode rejection ratio | (V–) + 1.5 V < VCM < (V+) – 1.5 V | 132 | 140 | dB | ||
(V–) + 1.5 V < VCM < (V+) – 1.5 V, TA = –40°C to 125°C | 120 | 130 | |||||
INPUT IMPEDANCE | |||||||
Differential | 400 || 9 | kΩ || pF | |||||
Common-mode | 109 || 0.5 | Ω || pF | |||||
OPEN-LOOP GAIN | |||||||
AOL | Open-loop voltage gain | (V–) + 0.2 V < VO < (V+) – 0.2 V, RL = 10 kΩ | TA = 25°C | 126 | 132 | dB | |
TA = –40°C to 125°C | 120 | ||||||
(V–) + 0.6 V < VO < (V+) – 0.6 V, RL = 600 Ω(1) | TA = 25°C | 114 | 120 | ||||
TA = –40°C to 85°C | 110 | ||||||
FREQUENCY RESPONSE | |||||||
GBW | Gain bandwidth product | 18 | MHz | ||||
SR | Slew rate | 6.4 | V/µs | ||||
Phase margin (Φm) | RL = 10 kΩ, CL = 25 pF | 80 | degrees | ||||
tS | Settling time | 0.1%, G = –1, 10-V step, CL = 100 pF | 2.1 | µs | |||
0.0015% (16-bit), G = –1, 10-V step, CL = 100 pF | 2.6 | ||||||
Overload recovery time | G = –10 | 0.5 | µs | ||||
Total harmonic distortion + noise (THD+N) | G = +1, f = 1 kHz, VO = 20 VPP, 600 Ω | 0.000025 | % |
(1) Temperature range limited by thermal performance of the package.
Electrical Characteristics (continued)
at VS = ±15 V, TA = 25°C, RL = 10 kΩ connected to midsupply, and VCM =VOUT = midsupply (unless otherwise noted)
PARAMETER | TEST CONDITIONS | MIN TYP MAX | UNIT | ||
OUTPUT | |||||
Voltage output swing | RL = 10 kΩ, AOL > 130 dB | (V–) + 0.2 (V+) – 0.2 | V | ||
RL = 600 Ω, AOL > 114 dB | (V–) + 0.6 (V+) – 0.6 | ||||
RL = 10 kΩ, AOL > 120 dB, TA = –40°C to 125°C | (V–) + 0.2 (V+) – 0.2 | ||||
ISC | Short-circuit current | VS = ±18 V | ±65 | mA | |
CLOAD | Capacitive load drive (stable operation) | ||||
ZO | Open-loop output impedance | ||||
POWER SUPPLY | |||||
IQ | Quiescent current (per amplifier) | IO = 0 A | TA = 25°C | 2.2 2.5 | mA |
TA = –40°C to 125°C | 3.25 |
at TA = 25°C, VS = ±15 V, RL = 10 kΩ connected to midsupply, and VCM = VOUT = midsupply (unless otherwise noted)
15%
Total Amplifiers (%)
10%
5%
20%
17.5%
Total Amplifiers (%)
15%
12.5%
10%
7.5%
5%
2.5%
0
-35 -30 -25 -20 -15 -10 -5 0 5 10 15 20 25 30 35
0
-0.6 -0.5 -0.4 -0.3 -0.2 -0.1 0 0.1 0.2 0.3 0.4 0.5 0.6
Input-Referred Offset Voltage (V)
Offset Voltage Drift (V/C)
Figure 1. Offset Voltage Production Distribution Figure 2. Offset Voltage Drift Distribution
100 10
Voltage Noise Density (nV/✓Hz)
Current Noise Density (pA/✓Hz)
10 1
1
100m 1 10 100 1k 10k 100k
Frequency (Hz)
0.1
100m 1 10 100 1k 10k 100k
Frequency (Hz)
Figure 3. Input Voltage Noise Spectral Density vs Frequency Figure 4. Input Current Noise Spectral Density vs Frequency
Total Harmonic Distortion Noise (dB)
0.01 -80
G 1
G 1
Input Voltage Noise (50 nV/div)
Total Harmonic Distortion Noise ()
0.001 -100
0.0001 -120
1E-5
100 1k 10k Frequency (Hz)
-140
Time (1 s/div)
Figure 5. 0.1-Hz to 10-Hz Voltage Noise
VOUT = 3.5 VRMS RL = 600 Ω
Figure 6. THD+N Ratio vs Frequency
Typical Characteristics (continued)
at TA = 25°C, VS = ±15 V, RL = 10 kΩ connected to midsupply, and VCM = VOUT = midsupply (unless otherwise noted)
Total Harmonic Distortion Noise (%)
1
0.1
0.01
G 1 G 1
-40
-60
-80
120
Total Harmonic Distortion + Noise (dB)
Input-referred Offset Voltage (V)
90
60
30
0.001
0.0001
-100
-120
0
-30
-60
1E-5
10m 100m 1 10
Output Amplitude (VRMS)
f = 1 kHz RL = 600 Ω
-140
-90
-120
-50 -25 0 25 50 75 100 125
Temperature (C)
50
Input-referred Offset Voltage (V)
30
10
-10
-30
-50
Figure 7. THD+N vs Output Amplitude
Vcm = -13.5 V Vcm = 13.5 V
5 typical units
Figure 8. Input Offset Voltage vs Temperature
50
Input-Referred Offset Voltage (V)
40
30
20
10
0
-10
-20
-30
-40
-50
-15 -10 -5 0 5 10 15
Input Common-mode Voltage (V)
5 typical units
Figure 9. Offset Voltage vs Common-Mode Voltage
PSRR PSRR | ||||||||||||||||||||||
160
Power-Supply Rejection Ratio (dB)
140
120
0 4 8 12 16 20 24 28 32 36
Supply Voltage (V)
5 typical units
Figure 10. Offset Voltage vs Supply Voltage
Power Supply Rejection Ratio (dB)
Power Supply Rejection Ratio (V/V)
160 0.01
150
100
80
60
40
20
0
140
130
120
0.1
1
100m 1 10 100 1k 10k 100k 1M 10M
Frequency (Hz)
-50 -25 0 25 50 75 100 125
Temperature (C)
Figure 11. PSSR vs Frequency Figure 12. PSRR vs Temperature
Typical Characteristics (continued)
CMRR
at TA = 25°C, VS = ±15 V, RL = 10 kΩ connected to midsupply, and VCM = VOUT = midsupply (unless otherwise noted)
160
Common-Mode Rejection Ratio (dB)
140
120
160 0.01
Common-mode Rejection Ratio (dB)
Common-mode Rejection Ratio (V/V)
150
100
80
60
40
20
140
130
120
0.1
1
100 1k 10k 100k 1M 10M
Frequency (Hz)
-50 -25 0 25 50 75 100 125
Temperature (C)
1000
Figure 13. CMRR vs Frequency Figure 14. CMRR vs Temperature
140 180
Gain
120
Phase
160
100
100 140
Phase ()
Gain (dB)
80 120
Zo ()
60 100
40 80
10
20 60
1
10 100 1k 10k 100k 1M 10M 100M
Frequency (Hz)
0 40
-20 20
100m 1 10 100 1k 10k 100k 1M 10M
Frequency (Hz)
Figure 15. Open-Loop Output Impedance vs Frequency Figure 16. Open-Loop Gain and Phase vs Frequency
10 k Load | ||||||
600 Load | ||||||
160 0.01 20%
150
Open-loop Gain (dB)
140
130
120
110
100
0.1
1
10
15%
Open-loop Gain (V/V)
Total Amplifiers (%)
10%
5%
-50 -25 0 25 50 75 100 125
Temperature (C)
0
-2 -1.5 -1 -0.5 0
0.5 1 1.5 2
Positive Input Bias Current (nA)
Figure 17. Open-Loop Gain vs Temperature
Figure 18. Positive Input Bias Current Production Distribution
Typical Characteristics (continued)
at TA = 25°C, VS = ±15 V, RL = 10 kΩ connected to midsupply, and VCM = VOUT = midsupply (unless otherwise noted)
20% 20%
16%
Total Amplifiers (%)
Total Amplifiers (%)
15%
12%
8%
10%
5%
4%
0
-2 -1.5 -1 -0.5 0
0.5 1 1.5 2
0
-2 -1.5 -1 -0.5 0
0.5 1 1.5 2
Negative Input Bias Current (nA) Input Offset Current (nA)
1.2
Ib+, Ib- and Ios (nA)
0.9
0.6
0.3
0
-0.3
Figure 19. Negative Input Bias Current Production Distribution
Figure 20. Input Offset Current Production Distribution
1000
800
Input Bias Current (pA)
600
400
200
0
-200
-400
-600
-800
-1000
Ib+ | ||||||||
Ib- | ||||||||
Ios |
-75 -50 -25 0 25 50 75 100 125 150
Temperature (C)
-14 -12 -10 -8 -6 -4 -2 0 2 4 6 8 10 12 14
Input Common-mode Voltage (V)
1000
800
Input Bias Current (pA)
600
400
200
0
-200
-400
-600
-800
-1000
Figure 21. Input Bias and Input Offset Currents vs Temperature
Figure 22. Positive Input Bias Current vs Common-Mode Voltage
1000
800
Input Offset Current (pA)
600
400
200
0
-200
-400
-600
-800
-1000
-14 -12 -10 -8 -6 -4 -2 0 2 4 6 8 10 12 14
Input Common-mode Voltage (V)
-14 -12 -10 -8 -6 -4 -2 0 2 4 6 8 10 12 14
Input Common-mode Voltage (V)
Figure 23. Negative Input Bias Current vs Common-Mode Voltage
Figure 24. Input Offset Current vs Common-Mode Voltage
Typical Characteristics (continued)
at TA = 25°C, VS = ±15 V, RL = 10 kΩ connected to midsupply, and VCM = VOUT = midsupply (unless otherwise noted)
2.5
2.4
Quiescent Current (mA)
2.3
2.2
2.1
2
1.9
1.8
1.7
1.6
1.5
0 4 8 12 16 20 24 28 32 36
Supply Voltage (V)
3.25
3
Quiescent Current (mA)
2.75
2.5
2.25
2
1.75
1.5
1.25
1
-50 -25 0 25 50 75 100 125
Temperature (C)
Figure 25. Quiescent Current vs Supply Voltage Figure 26. Quiescent Current vs Temperature
15 -12
25C
14.5 -12.5
Output Voltage (V)
Output Voltage (V)
-40C
85C
14 -13
125C
13.5
13
12.5
85C
125C
-13.5
-14
-14.5
-40C 25C
12
0 10 20 30 40 50 60
Output Current (mA)
-15
0 10 20 30 40 50 60
Output Current (mA)
Figure 27. Output Voltage vs Output Current (Sourcing) Figure 28. Output Voltage vs Output Current (Sinking)
Vin (V)
Vout (V)
Short Circuit Current (mA)
60
Voltage (5V/div)
55
50
Sinking Sourcing
45
40
-50 -25 0 25 50 75 100 125
Temperature (C)
Time (100 s/div)
Figure 29. Short-Circuit Current vs Temperature Figure 30. No Phase Reversal
Typical Characteristics (continued)
at TA = 25°C, VS = ±15 V, RL = 10 kΩ connected to midsupply, and VCM = VOUT = midsupply (unless otherwise noted)
Voltage (5 V/div)
Voltage (5 V/div)
VOUT VIN
VOUT VIN
G = -10
Time (500 ns/div)
G = -10
Time (500 ns/div)
Figure 31. Positive Overload Recovery Figure 32. Negative Overload Recovery
Voltage (5 mV/div)
Time (1 s/div)
G = +1 10-mV step, CL = 100 pF, RL = 600 Ω
Figure 33. Small-Signal Step Response
Voltage (5 mV/div)
Time (1 s/div)
G = –1 10-mV step, CL = 100 pF, RL = 600 Ω
Figure 34. Small-Signal Step Response
Voltage (2 V/div)
Time (1 s/div)
G = +1 10-V step, CL = 100 pF, RL = 600 Ω
Figure 35. Large-Signal Step Response
Voltage (2 V/div)
Time (1 s/div)
G = –1 10-V step, CL = 100 pF, RL = 600 Ω
Figure 36. Large-Signal Step Response
Typical Characteristics (continued)
10-V step
40
Overshoot ()
EMIRR IN+ (dB)
Output (1 mV/div)
at TA = 25°C, VS = ±15 V, RL = 10 kΩ connected to midsupply, and VCM = VOUT = midsupply (unless otherwise noted)
80
G 1 G 1
Falling
Rising
60
20
0
20
100
Capactiance (pF)
1000 2000
Time (4 s/div)
Figure 37. Small-Signal Overshoot vs Capacitive Load
Figure 38. Settling Time
140
130
120
110
100
90
80
70
60
50
40
30
20
10M
100M 1G
Frequency (Hz)
PRF = –10 dBm
Figure 39. EMIRR vs Frequency
The OPA2210 is the next generation of OPA2209 operational amplifier. The OPA2210 offers improved input offset voltage, offset voltage temperature drift, input bias current and lower 1/f noise corner frequency. In addition, this device offers excellent overall performance with high CMRR, PSRR, and AOL.The OPA2210 precision operational amplifier is unity-gain stable and free from unexpected output and phase reversal. Applications with noisy or high-impedance power supplies require decoupling capacitors placed close to the device pins. In most cases, 0.1-µF capacitors are adequate. The Functional Block Diagram shows a simplified schematic of the OPA2210. This die uses a SiGe bipolar process and contains 180 transistors.
V+
Pre-Output Driver OUT
IN-
IN+
V- Copyright © 2016, Texas Instruments Incorporated
The OPA2210 op amp can be used with single or dual supplies within an operating range of VS = 4.5 V (±2.25 V) up to 36 V (±18 V). Supply voltages higher than 40 V total can permanently damage the device.
In addition, key parameters are assured over the specified temperature range, TA = –40°C to +125°C. Parameters that vary significantly with operating voltage or temperature are shown in the Typical Characteristics.
The input terminals of the OPA2210 are protected from excessive differential voltage with back-to-back diodes, as shown in Figure 40. In most circuit applications, the input protection circuitry has no consequence. However, in low-gain or G = 1 circuits, fast ramping input signals can forward-bias these diodes because the output of the amplifier cannot respond rapidly enough to the input ramp. This effect is illustrated in Figure 35 and Figure 36 in the Typical Characteristics section. If the input signal is fast enough to create this forward-bias condition, the input signal current must be limited to 10 mA or less. If the input signal current is not inherently limited, an input series resistor can be used to limit the signal input current. This input series resistor degrades the low-noise performance of the OPA2210. See Noise Performance for further information on noise performance.
Feature Description (continued)
Figure 40 shows an example configuration that implements a current-limiting feedback resistor.
RF
-
Output
RI
+
Input
Figure 41 shows the total circuit noise for varying source impedances with the op amp in a unity-gain configuration (no feedback resistor network, and therefore no additional noise contributions). Two different op amps are shown with the total circuit noise calculated. The OPA2210 has very low voltage noise, making this device a great choice for low source impedances (less than 2 kΩ). As a comparable precision FET-input op amp (very low current noise), the OPA827 has somewhat higher voltage noise, but lower current noise. It provides excellent noise performance at moderate to high source impedance (10 kΩ and up). For source impedance lower than 300 Ω, the OPA211 may provide lower noise.
The equation in Figure 41 shows the calculation of the total circuit noise, with these parameters:
en = voltage noise,
in = current noise,
RS = source impedance,
k = Boltzmann's constant = 1.38 × 10–23 J/K, and
T = temperature in Kelvins
For more details on calculating noise, see Basic Noise Calculations.
10k
VOLTAGE NOISE SPECTRAL DENSITY vs SOURCE RESISTANCE
Votlage Noise Spectral Density, EO
1k
100
10
EO
RS
OPA827
OPAx210
Resistor Noise
O n n S S
E 2 = e 2 + (i R )2 + 4kTR
1
100 1k 10k 100k 1M
Source Resistance, RS (W)
Figure 41. Noise Performance of the OPA2210 and OPA827 in Unity-Gain Buffer Configuration
Feature Description (continued)
Designers often ask questions about the capability of an operational amplifier to withstand electrical overstress. These questions tend to focus on the device inputs, but may involve the supply voltage pins or even the output pin. Each of these different pin functions have electrical stress limits determined by the voltage breakdown characteristics of the particular semiconductor fabrication process and specific circuits connected to the pin. Additionally, internal electrostatic discharge (ESD) protection is built into these circuits to protect them from accidental ESD events both before and during product assembly.
It is helpful to have a good understanding of this basic ESD circuitry and its relevance to an electrical overstress event. See Figure 42 for an illustration of the ESD circuits contained in the OPA2210 (indicated by the dashed line area). The ESD protection circuitry involves several current-steering diodes connected from the input and output pins and routed back to the internal power-supply lines, where they meet at an absorption device internal to the operational amplifier. This protection circuitry is intended to remain inactive during normal circuit operation.
An ESD event produces a short duration, high-voltage pulse that is transformed into a short duration, high- current pulse as it discharges through a semiconductor device. The ESD protection circuits are designed to provide a current path around the operational amplifier core to prevent it from being damaged. The energy absorbed by the protection circuitry is then dissipated as heat.
When an ESD voltage develops across two or more of the amplifier device pins, current flows through one or more of the steering diodes. Depending on the path that the current takes, the absorption device may activate. The absorption device has a trigger, or threshold voltage, that is above the normal operating voltage of the OPA2210 but below the device breakdown voltage level. Once this threshold is exceeded, the absorption device quickly activates and clamps the voltage across the supply rails to a safe level.
When the operational amplifier connects into a circuit such as the one Figure 42 shows, the ESD protection components are intended to remain inactive and not become involved in the application circuit operation. However, circumstances may arise where an applied voltage exceeds the operating voltage range of a given pin. If this condition occur, there is a risk that some of the internal ESD protection circuits may be biased on, and conduct current. Any such current flow occurs through steering diode paths and rarely involves the absorption device.
Figure 42 depicts a specific example where the input voltage, VIN, exceeds the positive supply voltage (+VS) by 500 mV or more. Much of what happens in the circuit depends on the supply characteristics. If +VS can sink the current, one of the upper input steering diodes conducts and directs current to +VS. Excessively high current levels can flow with increasingly higher VIN. As a result, the datasheet specifications recommend that applications limit the input current to 10 mA.
If the supply is not capable of sinking the current, VIN may begin sourcing current to the operational amplifier, and then take over as the source of positive supply voltage. The danger in this case is that the voltage can rise to levels that exceed the operational amplifier absolute maximum ratings.
Another common question involves what happens to the amplifier if an input signal is applied to the input while the power supplies +VS and/or –VS are at 0 V.
Again, it depends on the supply characteristic while at 0 V, or at a level below the input signal amplitude. If the supplies appear as high impedance, then the operational amplifier supply current may be supplied by the input source through the current steering diodes. This state is not a normal bias condition; the amplifier will not operate normally. If the supplies are low impedance, then the current through the steering diodes can become quite high. The current level depends on the ability of the input source to deliver current, and any resistance in the input path.
Feature Description (continued)
If there is an uncertainty about the ability of the supply to absorb this current, external Transient Voltage Suppressor (TVS) diodes may be added to the supply pins as shown in Figure 42. The breakdown voltage must be selected such that the diode does not turn on during normal operation.
However, its breakdown voltage must be low enough so that the TVS diode conducts if the supply pin begins to rise above the safe operating supply voltage level.
TVS(2)
RF
+VS
+V
RI
R (3)
-In
Op Amp
ESD Current- Steering Diodes
OPAx210
Out
S +In
ID
Core
Edge-Triggered ESD Absorption Circuit
RL
V
(1)
IN -V
-VS
TVS(2)
VIN = +VS + 500 mV
TVS: +VS(max) > VTVSBR (Min) > +VS
Suggested value approximately 1 kΩ
Figure 42. Equivalent Internal ESD Circuitry and Relation to a Typical Circuit Application
The OPA2210 is operational when the power-supply voltage is greater than 4.5 V (±2.25 V). The maximum power-supply voltage for the OPA2210 is 36 V (±18 V).
Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.
The OPA2210 is a unity-gain stable, precision operational amplifier with very low noise. Applications with noisy or high-impedance power supplies require decoupling capacitors close to the device pins. In most cases, 0.1-µF capacitors are adequate.
Low-noise circuit design requires careful analysis of all noise sources. External noise sources can dominate in many cases; consider the effect of source resistance on overall op amp noise performance. Total noise of the circuit is the root-sum-square combination of all noise components.
The resistive portion of the source impedance produces thermal noise proportional to the square root of the resistance. This function is plotted in Figure 41. The source impedance is usually fixed; consequently, select the op amp and the feedback resistors to minimize the respective contributions to the total noise.
Figure 43 illustrates both noninverting (A) and inverting (B) op amp circuit configurations with gain. In circuit configurations with gain, the feedback network resistors also contribute noise. In general, the current noise of the op amp reacts with the feedback resistors to create additional noise components. However, the extremely low current noise of the OPA2210 means that its current noise contribution can be neglected.
The feedback resistor values can generally be chosen to make these noise sources negligible. Low impedance feedback resistors load the output of the amplifier. The equations for total noise are shown for both configurations.
Application Information (continued)
Noise in Noninverting Gain Configuration
Noise at the output is given as EO, where
R1 R2
R
R · R 2
(1) E = (1 + 2) · (e )2 + (e )2 + (e
)2 + (i
R )2 + (i
[ 1 2 ]) [ V ]
GND
0 R1 S N
R1 IIR2 N S
N R1 + R2
RMS
EO
+ (2) eS
RS
= J4 · kB · T(K) · RS
[ V ]
Thermal noise of RS
(3) e = 4 · k
T(K) · [ R1 · R2 ] [ V ] Thermal noise of R || R
R1 IIR2 B
+
V
R1 + R2 1 2
I
S
Source GND
(4) k = 1.38065 · 10-23 [ ]
B
K
(5) T(K) = 237.15 + T(°C) [ K ]
Boltzmann Constant Temperature in kelvins
Noise in Inverting Gain Configuration
Noise at the output is given as EO, where
R1 R2
(6) E
= (1 + R2 ) · (e )2 + (e
)2 + i
2
· ( RS + R1) · R2 [ V ]
0 RS + R1 N
RS
EO
R1 +RS IIR2
N RS + R1 + R2
RMS
+ (7) e
= 4 · k
(RS + R1) · R2 V
· T(K) · [ ]
+
VS
R1 +RS IIR2 B
RS + R1 + R2
Thermal noise of (R1 + RS) || R2
Source
GND
(8) kB = 1.38065 · 10-23
I
[ K ]
Boltzmann Constant
GND
(9) T(K) = 237.15 + T(°C) [ K ]
Temperature in kelvins
Copyright © 2017, Texas Instruments Incorporated
eN is the voltage noise of the amplifier. For the OPA2210 operational amplifier, eN = 2.2 nV/√Hz at 1 kHz.
iN is the current noise of the amplifier. For the OPA2210 operational amplifier, iN = 400 fA/√Hz at 1 kHz.
For additional resources on noise calculations visit TI's Precision Labs Series.
R4
2.94 k0
R1 590 0
C2 39 nF
R3 499 0
C5
1 nF
+
OPAx210
Output
Low-pass filters are commonly employed in signal processing applications to reduce noise and prevent aliasing. The OPA2210 is designed to construct high-speed, high-precision active filters. Figure 44 shows a second-order, low-pass filter commonly encountered in signal processing applications.
Use the following parameters for this design example:
Gain = 5 V/V (inverting gain)
Low-pass cutoff frequency = 25 kHz
Second-order Chebyshev filter response with 3-dB gain peaking in the passband
The infinite-gain multiple-feedback circuit for a low-pass network function is shown in Figure 44. Use Equation 1 to calculate the voltage transfer function.
Output (s)
1/ R1R3C2C5
Input s2 (s / C2 )(1/ R1 1/ R3 1/ R4 ) 1/ R3R4C2C5
(1)
Gain R4
R1
fc
1
2
(1/ R3R4C2C5 )
(2)
Figure 45. OPA2210 Second-Order, 25-kHz, Chebyshev, Low-Pass Filter
8.3.1 Time Gain Control System for Ultrasound Applications
During an ultrasound send-receive cycle, the magnitude of reflected signal depends on the depth of penetration. The ultrasound signal incident on the receiver decreases in amplitude as a function of the time elapsed since transmission, and the TGC helps achieve the best possible signal-to-noise ratio (SNR), even with the decreasing signal amplitude. When the image is displayed, similar material must have similar brightness, regardless of depth; this is achieved by Linear-in-dB gain, which means the decibel gain is a linear function of the control voltage (VCNTL).
There are multiple approaches for a TGC control circuit that are based on the type of DAC. Figure 46 shows a high level block diagram for the topology using a current-output multiplying DAC (MDAC) to generate the drive for VCNTL. The op amp used for current-to-voltage (I-to-V) conversion must have low-voltage noise as well as low- current noise density. The current density helps in reducing the overall noise performance because of the DAC output configuration. Because the DAC output can go up to ±10 V, the op amp must have bipolar operation. The OPA2210 is employed here due to its low voltage-noise density of 2.2 nV/√Hz, low current-noise density of 500 fA/√Hz, rail-to-rail output and its ability to accept a wide supply range of ±2.25 to ±18 V and provide rail-to-rail output. The low offset voltage and offset drift of the OPA2210 facilitate excellent dc accuracy for the circuit.
The OPA2210 is used to filter and buffer the 10-V reference voltage generated by the REF5010. This serves as the reference voltage for the DAC8802, which generates a current output on IOUT corresponding to the digital input code. The IOUT pin of the DAC8802 is connected to the virtual ground (negative terminal) of the OPA2210; the feedback resistor (RFB is internal to the DAC8802) is connected to the output of the OPA2210, resulting in a current-to-voltage conversion. The output of the OPA2210 has a range of –10 V to 0 V, and it is input to the THS4130, which is configured as a Sallen-Key filter. Finally, the 10-V range is attenuated down to a 1.5-V range, with common mode of 0.75 V using a resistive attenuator. See 2.3-nV/√Hz, Differential, Time Gain Control DAC Reference Design for Ultrasound for an in-depth analysis of Figure 46.
System Example (continued)
I-to-V Converters
+13 V -13 V
2nd Order Filter (fc = 150 kHz)
+5 V
+13 V-13 V
FPGA or Controller Interface
DAC8802
Connector
SPI
OPA2210
THS4130 VCM
VCNTL-P
Passive Attenuator
VCNTL (0 to 1.5V)
with VCM (0.75V)
VCNTL-M
REF+ REF-
+13 V -13 V
+13 V
REF5010
10 V
10 V
10V from REF5010
Required VCM as per AFE
Resistor Divider
0.75 V
OPA2210
-10 V
+5 V to 12 V
+15 V
LM5160
-15 V
+13 V
TPS7A39
-13 V
TPS7A47
Used only if +/-15 V is not available
+5 V
Figure 46. Block Diagram for Time Gain Control System for Ultrasound
The OPA2210 is specified for operation from 4.5 V to 36 V (±2.25 V to ±18 V); many specifications apply from
–40°C to 125°C. Parameters that can exhibit significant variance with regard to operating voltage or temperature are presented in the Typical Characteristics.
For best operational performance of the device, use good printed circuit board (PCB) layout practices, including the following guidelines:
Noise can propagate into analog circuitry through the power pins of the circuit as a whole and op amp itself. Bypass capacitors are used to reduce the coupled noise by providing low-impedance power sources local to the analog circuitry.
Connect low-ESR, 0.1-µF ceramic bypass capacitors between each supply pin and ground, placed as close to the device as possible. A single bypass capacitor from V+ to ground is applicable for single-supply applications.
Separate grounding for analog and digital portions of circuitry is one of the simplest and most-effective methods of noise suppression. One or more layers on multilayer PCBs are usually devoted to ground planes. A ground plane helps distribute heat and reduces EMI noise pickup. Make sure to physically separate digital and analog grounds paying attention to the flow of the ground current.
To reduce parasitic coupling, run the input traces as far away from the supply or output traces as possible. If these traces cannot be kept separate, crossing the sensitive trace perpendicular is much better as opposed to in parallel with the noisy trace.
Place the external components as close to the device as possible.
Keep the length of input traces as short as possible. Always remember that the input traces are the most sensitive part of the circuit.
Consider a driven, low-impedance guard ring around the critical traces. A guard ring can significantly reduce leakage currents from nearby traces that are at different potentials.
Cleaning the PCB following board assembly is recommended for best performance.
Any precision integrated circuit may experience performance shifts due to moisture ingress into the plastic package. Following any aqueous PCB cleaning process, baking the PCB assembly is recommended to remove moisture introduced into the device packaging during the cleaning process. A low-temperature, post- cleaning bake at 85°C for 30 minutes is sufficient for most circumstances.
Run the input traces as far away from the supply lines
Place components close to device and to each other to reduce parasitic errors
VS+
as possible RF
OUT B
-IN A
OUT A
V+
GND
RG
GND
VIN
-IN B
+IN A
Use a low-ESR, ceramic bypass capacitor
V-
+IN B
Use low-ESR, ceramic bypass capacitor
GND
VS-
VOUT A
Figure 47. OPA2210 Layout Example
Ground (GND) plane on another layer
Device and Documentation Support
TINA-TI™ (Free Software Download)
TINA™ is a simple, powerful, and easy-to-use circuit simulation program based on a SPICE engine. TINA-TI™ is a free, fully-functional version of the TINA software, preloaded with a library of macro models in addition to a range of both passive and active models. TINA-TI provides all the conventional DC, transient, and frequency domain analysis of SPICE, as well as additional design capabilities.
Available as a free download from the Analog eLab Design Center, TINA-TI offers extensive post-processing capability that allows users to format results in a variety of ways. Virtual instruments offer the ability to select input waveforms and probe circuit nodes, voltages, and waveforms, creating a dynamic quick-start tool.
NOTE
The DIP Adapter EVM tool provides an easy, low-cost way to prototype small surface mount ICs. The evaluation tool these TI packages: D or U (SOIC-8), PW (TSSOP-8), DGK (VSSOP-8), DBV (SOT23-6, SOT23-5 and
SOT23-3), DCK (SC70-6 and SC70-5), and DRL (SOT563-6). The DIP Adapter EVM may also be used with terminal strips or may be wired directly to existing circuits.
Universal Operational Amplifier EVM
The Universal Op Amp EVM is a series of general-purpose, blank circuit boards that simplify prototyping circuits for a variety of IC package types. The evaluation module board design allows many different circuits to be constructed easily and quickly. Five models are offered, with each model intended for a specific package type. PDIP, SOIC, VSSOP, TSSOP, and SOT-23 packages are all supported.
NOTE
These boards are unpopulated, so users must provide their own ICs. TI recommends requesting several op amp device samples when ordering the Universal Op Amp EVM.
TI Precision Designs are analog solutions created by TI’s precision analog applications experts and offer the theory of operation, component selection, simulation, complete PCB schematic and layout, bill of materials, and measured performance of many useful circuits. TI Precision Designs are available online at http://www.ti.com/ww/en/analog/precision-designs/.
WEBENCH® Filter Designer
WEBENCH® Filter Designer is a simple, powerful, and easy-to-use active filter design program. The WEBENCH Filter Designer lets you create optimized filter designs using a selection of TI operational amplifiers and passive components from TI's vendor partners.
Available as a web-based tool from the WEBENCH® Design Center, WEBENCH® Filter Designer allows you to design, optimize, and simulate complete multistage active filter solutions within minutes.
The following documents are relevant to using the OPA2210 and recommended for reference. All are available for download at www.ti.com (unless otherwise noted):
Texas Instruments, OPA827 Low-Noise, High-Precision, JFET-Input Operational Amplifier data sheet
Texas Instruments, OPA2x11 1.1-nv/√Hz Noise, Low Power, Precision Operational Amplifier data sheet
Texas Instruments, OPA210, OPA2210, OPA4210 EMI Immunity Performance technical brief
Texas Instruments, OPAx209 2.2-nV/√Hz, Low-Power, 36-V Operational Amplifier data sheet
Texas Instruments, Microcontroller PWM to 12-bit Analog Out design guide
Texas Instruments, Capacitive Load Drive Solution Using an Isolation Resistor design guide
Texas Instruments, Diagnostic Patient Monitoring and Therapy Application guide
Receiving Notification of Documentation Updates
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TINA-TI, E2E are trademarks of Texas Instruments. WEBENCH is a registered trademark of Texas Instruments. TINA, DesignSoft are trademarks of DesignSoft, Inc.
All other trademarks are the property of their respective owners.
Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
www.ti.com 6-Feb-2020
PACKAGING INFORMATION
Orderable Device | Status (1) | Package Type | Package Drawing | Pins | Package Qty | Eco Plan (2) | Lead/Ball Finish (6) | MSL Peak Temp (3) | Op Temp (°C) | Device Marking (4/5) | Samples |
OPA2210ID | ACTIVE | SOIC | D | 8 | 75 | Green (RoHS & no Sb/Br) | NIPDAU | Level-2-260C-1 YEAR | -40 to 125 | OP2210 | |
OPA2210IDGKR | ACTIVE | VSSOP | DGK | 8 | 2500 | Green (RoHS & no Sb/Br) | NIPDAUAG | Level-2-260C-1 YEAR | -40 to 125 | 1OHQ | |
OPA2210IDGKT | ACTIVE | VSSOP | DGK | 8 | 250 | Green (RoHS & no Sb/Br) | NIPDAUAG | Level-2-260C-1 YEAR | -40 to 125 | 1OHQ | |
OPA2210IDR | ACTIVE | SOIC | D | 8 | 2500 | Green (RoHS & no Sb/Br) | NIPDAU | Level-2-260C-1 YEAR | -40 to 125 | OP2210 | |
OPA2210IDRGR | PREVIEW | SON | DRG | 8 | 3000 | TBD | Call TI | Call TI | -40 to 125 | ||
OPA2210IDRGT | PREVIEW | SON | DRG | 8 | 250 | TBD | Call TI | Call TI | -40 to 125 | ||
POPA2210IDRGT | ACTIVE | SON | DRG | 8 | 250 | TBD | Call TI | Call TI | -40 to 125 |
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device.
Addendum-Page 1
www.ti.com 6-Feb-2020
(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
www.ti.com 19-Dec-2019
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device | Package Type | Package Drawing | Pins | SPQ | Reel Diameter (mm) | Reel Width W1 (mm) | A0 (mm) | B0 (mm) | K0 (mm) | P1 (mm) | W (mm) | Pin1 Quadrant |
OPA2210IDGKR | VSSOP | DGK | 8 | 2500 | 330.0 | 12.4 | 5.3 | 3.4 | 1.4 | 8.0 | 12.0 | Q1 |
OPA2210IDGKT | VSSOP | DGK | 8 | 250 | 330.0 | 12.4 | 5.3 | 3.4 | 1.4 | 8.0 | 12.0 | Q1 |
OPA2210IDR | SOIC | D | 8 | 2500 | 330.0 | 12.4 | 6.4 | 5.2 | 2.1 | 8.0 | 12.0 | Q1 |
Pack Materials-Page 1
www.ti.com 19-Dec-2019
*All dimensions are nominal
Device | Package Type | Package Drawing | Pins | SPQ | Length (mm) | Width (mm) | Height (mm) |
OPA2210IDGKR | VSSOP | DGK | 8 | 2500 | 366.0 | 364.0 | 50.0 |
OPA2210IDGKT | VSSOP | DGK | 8 | 250 | 366.0 | 364.0 | 50.0 |
OPA2210IDR | SOIC | D | 8 | 2500 | 367.0 | 367.0 | 35.0 |
Pack Materials-Page 2
SOIC - 1.75 mm max height
SCALE 2.800
SMALL OUTLINE INTEGRATED CIRCUIT
C
.189-.197
[4.81-5.00]
NOTE 3
.228-.244 TYP
A | ||
1 |
[5.80-6.19]
.050
[1.27]
PIN 1 ID AREA
6X
8
2X
.150
[3.81]
C
SEATING PLANE
.004 [0.1]
4
B .150-.157
[3.81-3.98]
NOTE 4
5
8X .012-.020
.010 [0.25] | C | A | B |
[0.31-0.51]
4X (0 -15 )
.069 MAX
[1.75]
.005-.010 TYP
[0.13-0.25]
4X (0 -15 )
SEE DETAIL A
.010
[0.25]
0 - 8
.004-.010
[0.11-0.25]
.016-.050
[0.41-1.27]
(.041)
[1.04]
DETAIL A
TYPICAL
4214825/C 02/2019
NOTES:
Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches. Dimensioning and tolerancing per ASME Y14.5M.
This drawing is subject to change without notice.
This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed .006 [0.15] per side.
This dimension does not include interlead flash.
Reference JEDEC registration MS-012, variation AA.
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
1
8X (.024)
[0.6]
4
6X (.050 )
[1.27]
SYMM
(.213)
[5.4]
LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:8X
SEE DETAILS
8
SYMM
(R.002 ) TYP
5 [0.05]
METAL SOLDER MASK
SOLDER MASK METAL UNDER
OPENING
OPENING
SOLDER MASK
EXPOSED METAL
.0028 MAX
[0.07]
ALL AROUND
EXPOSED
METAL
.0028 MIN
[0.07]
ALL AROUND
NON SOLDER MASK DEFINED
SOLDER MASK DEFINED
SOLDER MASK DETAILS
4214825/C 02/2019
NOTES: (continued)
Publication IPC-7351 may have alternate designs.
Solder mask tolerances between and around signal pads can vary based on board fabrication site.
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
1
SYMM
8
8X (.024)
[0.6]
SYMM
4
6X (.050 )
[1.27]
(.213)
[5.4]
(R.002 ) TYP
5 [0.05]
SOLDER PASTE EXAMPLE
BASED ON .005 INCH [0.125 MM] THICK STENCIL SCALE:8X
4214825/C 02/2019
NOTES: (continued)
Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations.
Board assembly site may have different recommendations for stencil design.
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