n ± 500mA Minimum Output Current
n Independent Adjustment of Source and Sink Current Limits
n 1% Current Limit Accuracy
n Improved Reactive Load Driving Stability
n Operates with Single or Split Supplies
n Shutdown/Enable Control Input
n Open-Collector Status Flags: Sink Current Limit Source Current Limit Thermal Shutdown
n Fail-Safe Current Limit and Thermal Shutdown
n 1.6V/µs Slew Rate
n 3.6MHz Gain-Bandwidth Product
n Specified Temperature Range: –40°C to 85°C
n Available in a 20-Lead TSSOP Package
n Automatic Test Equipment n Laboratory Power Supplies n Motor Drivers
n Thermoelectric Cooler Driver
LT1970A
500mA Power Op Amp with Adjustable Precision Current Limit
The LT®1970A is a ± 500mA power op amp with precise externally controlled current limiting. Separate control voltages program the sourcing and sinking current limit sense thresholds with 1% accuracy. Output current may be boosted by adding external power transistors.
The circuit operates with single or split power supplies from 5V to 36V total supply voltage. In normal opera- tion, the input stage supplies and the output stage sup- plies are connected (VCC to V+ and VEE to V–). To reduce power dissipation it is possible to power the output stage (V+, V–) from independent, lower voltage rails. The amplifier is unity-gain stable witha 3.6MHzgain-bandwidthproduct and slews at 1.6V/µs. The LT1970A can drive capacitive and inductive loads directly.
Open-collector status flags signal current limit circuit activation, as well as thermal shutdown of the amplifier. An enable logic input puts the amplifier into a low power, high impedance output state when pulled low. Thermal shutdown and a ±800mA fixed current limit protect the chip under fault conditions.
The LT1970A is packaged in a 20-lead TSSOP package with
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners.
a thermally conductive copper bottom plate to facilitate heat sinking.
VLIMIT
0V TO 5V
20V
VCC V+
20V
6k
IOUT(MAX) = ± VLIMIT
CURRENT LIMIT = 500mA
VIN +IN
EN
VCSRC
VCSNK
ISNK
ISRC
IOUT
RCS 1Q
10 • RCS
TRACE R TRACE L
VLOAD, RLOAD = 100Q
VLOAD,
LT1970A
TSD
SENSE+ OUT
1/4W
100mQ
200nH
4.7µF
2V/DIV
RLOAD = 10Q
–IN
COMMON
VEE
–5V
SENSE– SENSE
V–
10k 100pF
ESR 0.1Q
1970A TA01
LOAD
VIN, 5V/DIV
0V
100µs/DIV
1970A TA01b
Supply Voltage (VCC to VEE) ..................................... 36V
20 VEE
19 V+
18 TSD
17 ISNK
16 ISRC
15 ENABLE
14 COMMON
13 VCSRC
12 VCSNK
11 VEE
Positive High Current Supply (V+)................... V– to VCC
Negative High Current Supply(V–) ....................VEE to V+ Amplifier Output (OUT) ..................................... V– to V+
Current Sense Pins
(SENSE+, SENSE–, FILTER)........................... V– to V+ Logic Outputs (ISRC, ISNK, TSD) ....... COMMON to VCC Input Voltage (–IN, +IN)............ VEE – 0.3V to VEE + 36V Input Current......................................................... 10mA
VEE 10
Current Control Inputs
(VCSRC, VCSNK).............. COMMON to COMMON + 7V Enable Logic Input .............................. COMMON to VCC COMMON....................................................... VEE to VCC
Output Short-Circuit Duration ......................... Indefinite
Operating Temperature Range (Note 2).... –40°C to 85°C Specified Temperature Range (Note 3)
LT1970AC ................................................ 0°C to 70°C
LT1970AI.............................................. –40°C to 85°C
Maximum Junction Temperature.......................... 150°C
Storage Temperature Range................... –65°C to 150°C
Lead Temperature (Soldering, 10 sec) .................. 300°C
TOP VIEW
VEE V–
OUT SENSE+
FILTER SENSE–
VCC
–IN
+IN
1
2
3
4
5
6
7
8
9
21
FE PACKAGE
20-LEAD PLASTIC TSSOP
TJMAX = 150°C, JA = 40°C/W (NOTE 8) EXPOSED PAD (PIN 21) IS CONNECTED TO VEE
LEAD FREE FINISH | TAPE AND REEL | PART MARKING* | PACKAGE DESCRIPTION | SPECIFIED TEMPERATURE RANGE |
LT1970ACFE#PBF | LT1970ACFE#TRPBF | LT1970AFE | 20-Lead Plastic TSSOP | 0°C to 70°C |
LT1970AIFE#PBF | LT1970AIFE#TRPBF | LT1970AFE | 20-Lead Plastic TSSOP | –40°C to 85°C |
Consult LTC Marketing for parts specified with wider operating temperature ranges.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/. Some packages are available in 500 unit reels through designated sales channels with #TRMPBF suffix.
SYMBOL | PARAMETER | CONDITIONS | MIN TYP MAX | UNITS |
Power Op Amp Characteristics
VOS | Input Offset Voltage | 0°C < TA < 70°C –40°C < TA < 85°C | l l | 200 | 600 1000 1300 | µV µV µV | |
Input Offset Voltage Drift (Note 4) | l | –10 | –4 | 10 | µV/°C | ||
IOS | Input Offset Current | VCM = 0V | l | –100 | 100 | nA | |
IB | Input Bias Current | VCM = 0V | l | –600 | –160 | nA | |
Input Noise Voltage | 0.1Hz to 10Hz | 3 | µVP-P |
SYMBOL | PARAMETER | CONDITIONS | MIN | TYP | MAX | UNITS | |
en | Input Noise Voltage Density | 1kHz | 15 | nV/√Hz | |||
in | Input Noise Current Density | 1kHz | 3 | pA/√Hz | |||
RIN | Input Resistance | Common Mode Differential Mode | 500 100 | kΩ kΩ | |||
CIN | Input Capacitance | Pin 8 and Pin 9 to Ground | 6 | pF | |||
VCM | Input Voltage Range | Typical Guaranteed by CMRR Test | l | –14.5 –12.0 | 13.6 12.0 | V V | |
CMRR | Common Mode Rejection Ratio | –12V < VCM < 12V | l | 92 | 105 | dB | |
PSRR | Power Supply Rejection Ratio | VEE = V– = –5V, VCC = V+ = 3V to 30V VEE = V– = –5V, VCC = 30V, V+ = 2.5V to 30V VEE = V– = –3V to – 30V, VCC = V+ = 5V VEE = –30V, V– = –2.5V to –30V, VCC = V+ = 5V | l l l l | 90 110 90 110 | 100 130 100 130 | dB dB dB dB | |
AVOL | Large-Signal Voltage Gain | RL = 1k, –12.5V < VOUT < 12.5V | l | 100 75 | 150 | V/mV V/mV | |
RL = 100Ω, –12.5V < VOUT < 12.5V | l | 80 40 | 120 | V/mV V/mV | |||
RL = 10Ω, –5V < VOUT < 5V, V+ = – V– = 8V | l | 20 5 | 45 | V/mV V/mV | |||
VOL | Output Sat Voltage Low | VOL = VOUT – V– RL = 100, VCC = V+ = 15V, VEE = V– = –15V RL = 10, VCC = – VEE = 15V, V+ = –V– = 5V | l | 1.9 0.8 | 2.5 | V V | |
VOH | Output Sat Voltage High | VOH = V+ – VOUT RL = 100, VCC = V+ = 15V, VEE = V– = –15V RL = 10, VCC = – VEE = 15V, V+ = –V– = 5V | l | 1.7 1.0 | 2.3 | V V | |
ISC | Output Short-Circuit Current | Output Low, RSENSE = 0Ω Output High, RSENSE = 0Ω | 500 –1000 | 800 –800 | 1200 –500 | mA mA | |
SR | Slew Rate | –10V < VOUT < 10V, RL = 1k | 0.7 | 1.6 | V/µs | ||
FPBW | Full Power Bandwidth | VOUT = 10VPEAK (Note 5) | 11 | kHz | |||
GBW | Gain-Bandwidth Product | f = 10kHz | 3.6 | MHz | |||
tS | Settling Time | 0.01%, VOUT = 0V to 10V, AV = –1, RL = 1k | 8 | µs |
Current Sense Characteristics
VSENSE(MIN) | Minimum Current Sense Voltage | VCSRC = VCSNK = 0V | l | 0.1 0.1 | 4 | 7 10 | mV mV |
VSENSE(4%) | Current Sense Voltage 4% of Full Scale | VCSRC = VCSNK = 0.2V | l | 15 | 20 | 25 | mV |
VSENSE(10%) | Current Sense Voltage 10% of Full Scale | VCSRC = VCSNK = 0.5V | l | 45 | 50 | 55 | mV |
VSENSE(FS) | Current Sense Voltage 100% of Full Scale | VCSRC = VCSNK = 5V | l | 495 480 | 500 500 | 505 520 | mV mV |
IBI | Current Limit Control Input Bias Current | VCSRC, VCSNK Pins | l | –1 | –0.2 | 0.1 | µA |
ISENSE– | SENSE– Input Current | 0V < (VCSRC, VCSNK) < 5V | l | –500 | 500 | nA | |
IFILTER | FILTER Input Current | 0V < (VCSRC, VCSNK) < 5V | l | –500 | 500 | nA | |
ISENSE+ | SENSE+ Input Current | VCSRC= VCSNK = 0V VCSRC = 5V, VCSNK = 0V VCSRC= 0V, VCSNK = 5V VCSRC = VCSNK = 5V | l l l l | –500 200 –300 –25 | 250 –250 | 500 300 –200 25 | nA µA µA µA |
Current Sense Change with Output Voltage | VCSRC = VCSNK = 5V, –12.5V < VOUT < 12.5V | ±0.1 | % | ||||
Current Sense Change with Supply Voltage | VCSRC = VCSNK = 5V, 6V < (VCC, V+) < 18V 2.5V < V+ < 18V, VCC = 18V –18V < (VEE, V–) < –2.5V –18V < V– < –2.5V, VEE = –18V | ±0.05 ±0.01 ±0.05 ±0.01 | % % % % |
SYMBOL | PARAMETER | CONDITIONS | MIN TYP MAX | UNITS | |
Current Sense Bandwidth | 2 | MHz | |||
RCSF | Resistance FILTER to SENSE– | l | 750 1000 1250 | Ω |
Logic I/O Characteristics
Logic Output Leakage ISRC, ISNK, TSD | V = 15V | l | 1 | µA | |
Logic Low Output Level | I = 5mA (Note 6) | l | 0.2 0.4 | V | |
Logic Output Current Limit | 25 | mA | |||
VENABLE | Enable Logic Threshold | l | 0.8 1.9 2.5 | V | |
IENABLE | Enable Pin Bias Current | l | –1 1 | µA | |
ISUPPLY | Total Supply Current | VCC, V+ and V–, VEE Connected | l | 7 13 | mA |
ICC | VCC Supply Current | VCC, V+ and V–, VEE Separate | l | 3 7 | mA |
ICC(STBY) | Supply Current Disabled | VCC, V+ and V–, VEE Connected, VENABLE ≤ 0.8V | l | 0.6 1.5 | mA |
tON | Turn-On Delay | (Note 7) | 10 | µs | |
tOFF | Turn-Off Delay | (Note 7) | 10 | µs |
Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reli- ability and lifetime.
Note 2: The LT1970AC is guaranteed functional over the operating tem- perature range of – 40°C and 85°C.
Note 3: The LT1970AC is guaranteed to meet specified performance from 0°C to 70°C. The LT1970AC is designed, characterized and expected to meet specified performance from –40°C to 85°C but is not tested or QA sampled at these temperatures. The LT1970AI is guaranteed to meet speci- fied performance from –40°C to 85°C.
Note 4: This parameter is not 100% tested.
Note 5: Full power bandwidth is calculated from slew rate measurements:
FPBW = SR/(2 • π • VP)
Note 6: The logic low output level of pin TSD is guaranteed by correlating the output level of pin ISRC and pin ISNK over temperature.
Note 7: Turn-on and turn-off delay are measured from VENABLE crossing 1.6V to the OUT pin at 90% of normal output voltage.
Note 8: Thermal resistance varies depending upon the amount of PC board metal attached to the device. If the maximum dissipation of the package is exceeded, the device will go into thermal shutdown and be protected.
VOS • 1000 (50mV/DIV)
0V
TIME (100ms/DIV) 1970A G01
–100
–120
INPUT BIAS CURRENT (nA)
–140
–160
–180
–200
–220
–240
–260
VS = ±15V
–IBIAS
V
+IBIAS
14
12
TOTAL SUPPLY CURRENT (mA)
10
8
6
4
2
0
–2
–4
–6
–8
–10
–12
–14
ICC + I +
IEE + I –
125°C
V
25°C
–55°C
–55°C 25°C
125°C
–15 –12 –9 –6 –3 0 3 6 9 12 15
0 2 4 6
8 10
12 14 16 18
COMMON MODE INPUT VOLTAGE (V)
1970A G02
SUPPLY VOLTAGE (±V)
1970A G03
V
GAIN
4.5
4.0
SUPPLY CURRENT (mA)
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
TA = 25°C
VCC = V+ = –VEE = –V–
I +
CC
V
I –
IV IVEE
70
60
OPEN-LOOP GAIN (dB)
50
40
30
20
10
0
–10
–20
–30
100 60
AV = –1 RF = RG = 1k TA = 25°C VOUT = VS/2 | ||||||||
90 58
PHASE
PHASE MARGIN (DEG)
PHASE MARGIN (DEG)
80 56
70 54
60 52
50 50
40 48
30 46
20 44
10 42
0 40
2 4 6
8 10 12
14 16 18 20
100 1k
10k 100k 1M 10M 100M
0 4 8
12 16 20
24 28 32 36
SUPPLY VOLTAGE (±V)
1870A G04
FREQUENCY (Hz)
1970A G05
TOTAL SUPPLY VOLTAGE (V)
1970A G06
AV = 1
AV = 100 | ||||||||
5 10
GAIN BANDWIDTH (MHz)
VOLTAGE GAIN (dB)
4 0
3 –10
2 –20
1 –30
10
VOLTAGE GAIN (dB)
0
–10
–20
–30
VS = ±15V
10nF
F
3
VS = ±5V
S = ±15V
V
AV = 1 0n
1nF
0
nF
0
0 4 8
12 16 20
24 28 32 36
–40
10k
100k
1M 10M
–40
10k
100k
1M 10M
TOTAL SUPPLY VOLTAGE (V)
1970A G07
FREQUENCY (Hz)
1970A G08
FREQUENCY (Hz)
1970A G09
100
OUTPUT IMPEDANCE (Q)
10
1
0.1
0.01
0.001
VS = ±15V
AV = 100
AV = 10
AV = 1
600k
100k
OUTPUT IMPEDANCE (Ω)
10k 1k 100
10
1
VS = ±15V VENABLE = 0.8V
1.8
1.7
SLEW RATE (V/µs)
1.6
1.5
1.4
1.3
1.2
1.1
1.0
AV = –1
RF = RG = 1k TA = 25°C
FALLING
RISING
1k 10k
100k 1M 10M 100M
1k 10k 100k 1M 10M 100M
4 6 8
10 12
14 16 18
FREQUENCY (Hz)
1970A G10
FREQUENCY (Hz)
1970A G11
SUPPLY VOLTAGE (±V)
1970A G12
VS = ±15V | FAL | LING | ||||
RISING | ||||||
2.5
SLEW RATE (V/µs)
2.0
1.5
1.0
10V
5V/DIV
0V
–10V
10V
5V/DIV
0V
–10V
0.5
0
–50 –25 0
25 50 75
100 125
RL = 1k
20µs/DIV 1970A G14
RL = 1k
CL = 1000pF
20µs/DIV
1970A G15
TEMPERATURE (°C)
1970A G13
20mV/DIV
20mV/DIV
0V
VOUT 5V/DIV
0V
VIN 5V/DIV
RL = 1k
500ns/DIV 1970A G16
RL = 1k
CL = 1000pF
2µs/DIV 1970A G17
VS = ±5V AV = 1
200µs/DIV 1970A G18
60
VS = ±15V
50
OVERSHOOT (%)
40
30
20
AV = 1
AV = –1
30
OUTPUT SWING (VP-P)
25
20
15
10
500
400
300
200
VSENSE (mV)
100
0
–100
–200
10
0
10 100 1k 10k
CLOAD (pF)
1970A G19
5 VS = ±15V AV = –5
1% THD
0
100
1k 10k 100k FREQUENCY (Hz)
1970A G20
–300
SOURCING CURRENT | ||||||||||
SINKING CURRENT | ||||||||||
–400
–500
0
1 2 3
VCSNK = VCSRC (V)
4 5
1970A G21
25
20
15
10
VSENSE (mV)
5
0
–5
–10
–15
–20
–25
1.0
0.9
LOGIC OUTPUT VOLTAGE (V)
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
V+ = 15V V– = –15V | |||||||||||||
25°C | |||||||||||||
125°C | |||||||||||||
–55°C | |||||||||||||
1600
1400
OUTPUT CURRENT (mA)
1200
1000
800
600
400
200
0
V+ = 15V V– = –15V
SOURCE
SINK
SOURCING CURRENT | ||||||||||
SINKING CURRENT | ||||||||||
0 25 50
75 100 125 150 175 200 225 250
0.001
0.01 0.1 1 10 100
–75
–50
–25 0
25 50
75 100
125
VCSNK = VCSRC (mV)
1970A G22
SINK CURRENT (mA)
1970A G23
TEMPERATURE (°C)
1970A G24
1200
IOUT AT 10% DUTY CYCLE
10
I
8
1000
IOUT PEAK (mA)
800
600
400
200
0
0
5 10 15 20
25 30
35 40
+
OUTPUT STAGE CURRENT (mA)
6 V
4
2
I
0 –
V
–2
–4
–6
–8
–10
0 2 4 6
125°C
25°C
–55°C
–55°C 25°C
125°C
8 10
12 14 16 18
SUPPLY VOLTAGE (V)
1970A G25
SUPPLY VOLTAGE (±V)
1970A G26
5°C
ICC
5
800
TOTAL SUPPLY CURRENT, ICC + IV+ (µA)
VENABLE = 0V
4 12
3 25°C
SUPPLY CURRENT (mA)
–55°C
2
1
IEE
0
–1 –55°C
25°C
–2
125°C
–3
–4
85°C
700
600 25°C
–55°C
500
400
300
200
100
–5
0 2 4 6
8 10
12 14 16 18
0
0 2 4 6
8 10
12 14
16 18
SUPPLY VOLTAGE (±V)
1970A G27
SUPPLY VOLTAGE (V)
1970A G28
VEE (Pins 1, 10, 11, 20, 21): Minus Supply Voltage. VEE connects to the substrate of the integrated circuit die, and therefore must always be the most negative voltage ap- plied to the part. Decouple VEE to ground with a low ESR capacitor. VEE may be a negative voltage or it may equal ground potential. Any or all of the VEE pins may be used. Unused VEE pins must remain open.
V– (Pin 2): Output Stage Negative Supply. V– may equal VEE or may be smaller in magnitude. Only output stage current flows out of V–, all other current flows out of VEE.
V– may be used to drive the base/gate of an external power
device to boost theamplifier’s output current to levelsabove the rated 500mA of the on-chip output devices. Unless used to drive boost transistors, V– should be decoupled to ground with a low ESR capacitor.
OUT (Pin 3): Amplifier Output. The OUT pin provides the force function as part of a Kelvin sensed load connection. OUT is normally connected directly to an external load cur- rent sense resistor and the SENSE+ pin. Amplifier feedback is directly connected to the load and the other end of the current sense resistor. The load connection is also wired directly to the SENSE– pin to monitor the load current.
The OUT pin is current limited to ±800mA typical. This current limit protects the output transistor in the event that connections to the external sense resistor are opened or shorted which disables the precision current limit function.
SENSE+ (Pin 4): Positive Current Sense Pin. This lead is normally connected to the driven end of the external sense resistor. Sourcing current limit operation is activatedwhen the voltage VSENSE (VSENSE+ – VSENSE–) equals 1/10 of the programming control voltage at VCSRC (Pin 13). Sink- ing current limit operation is activated when the voltage VSENSE equals –1/10 of the programming control voltage at VCSNK (Pin 12).
FILTER (Pin 5): Current Sense Filter Pin. This pin is normally not used and should be left open or shorted to the SENSE– pin. The FILTER pin can be used to adapt the response time of the current sense amplifiers with a 1nF to 100nF capacitor connected to the SENSE– input. An internal 1k resistor sets the filter time constant.
SENSE– (Pin 6): Negative Current Sense Pin. This pin is normally connected to the load end of the external sense resistor. Sourcing current limit operation is activated when the voltage VSENSE (VSENSE+ – VSENSE–) equals 1/10 of the programming control voltage at VCSRC (Pin 13). Sink- ing current limit operation is activated when the voltage VSENSE equals –1/10 of the programming control voltage at VCSNK (Pin 12).
VCC (Pin 7): Positive Supply Voltage. All circuitry except the output transistors draw power from VCC. Total supply voltage from VCC to VEE must be between 3.5V and 36V. VCC must always be greater than or equal to V+. VCCshould always be decoupled to ground with a low ESR capacitor.
–IN (Pin 8): Inverting Input of Amplifier. –IN may be any voltage from VEE – 0.3V to VEE + 36V. –IN and +IN remain high impedance at all times to prevent current flow into the inputs when current limit mode is active. Care must be taken to ensure that –IN or +IN can never go to a volt- age below VEE – 0.3V even during transient conditions or damage to the circuit may result. A Schottky diode from VEE to –IN can provide clamping if other elements in the circuit can allow –IN to go below VEE.
+IN (Pin 9): Noninverting Input of Amplifier. +IN may be any voltage from VEE – 0.3V to VEE + 36V. –IN and +IN remain high impedance at all times to prevent current flow into the inputs when current limit mode is active. Care must be taken to ensure that –IN or +IN can never go to a volt- age below VEE – 0.3V even during transient conditions or damage to the circuit may result. A Schottky diode from VEE to +IN can provide clamping if other elements in the circuit can allow + IN to go below VEE.
VCSNK (Pin 12): Sink Current Limit Control Voltage In- put. The current sink limit amplifier will activate when the sense voltage between SENSE+ and SENSE– equals
–1.0 • VVCSNK/10. VCSNK may be set between VCOMMON and VCOMMON + 6V. The transfer function between VCSNK and VSENSE is linear except for very small input voltages at VCSNK < 60mV. VSENSE limits at a minimum set point of 4mV typical to ensure that the sink and source limit amplifiers do not try to operate simultaneously. To force zero output current, the ENABLE pin can be taken low.
VCSRC (Pin 13): Source Current Limit Control Voltage Input. The current source limit amplifier will activate when the sense voltage between SENSE+ and SENSE– equals VVCSRC/10. VCSRC may be set between VCOMMON and VCOMMON + 6V. The transfer function between VCSRC and VSENSE is linear except for very small input voltages at VCSRC < 60mV. VSENSE limits at a minimum set point of 4mV typical to ensure that the sink and source limit amplifiers do not try to operate simultaneously. To force zero output current, the ENABLE pin can be taken low.
COMMON (Pin 14): Control and ENABLE inputs and flag outputs are referenced to the COMMON pin. COMMON may be at any potential between VEE and VCC – 3V. In typical applications, COMMON is connected to ground.
ENABLE (Pin 15): ENABLE Digital Input Control. When taken low this TTL-level digital input turns off the ampli- fier output and drops supply current to less than 1mA. Use the ENABLE pin to force zero output current. Setting VCSNK = VCSRC = 0V allows IOUT = ±4mV/RSENSE to flow in or out of VOUT.
current. The current limit flag is off when the source current limit is not active. ISRC, ISNK and TSD may be wired “OR” together if desired. ISRC may be left open if this function is not monitored.
V+ (Pin 19): Output Stage Positive Supply. V+ may equal VCC or may be smaller in magnitude. Only output stage current flows through V+, all other current flows into VCC.
V+ may be used to drive the base/gate of an external power
device to boost theamplifier’s output current to levelsabove the rated 500mA of the on-chip output devices. Unless used to drive boost transistors, V+ should be decoupled to ground with a low ESR capacitor.
Exposed Pad (Pin 21): The exposed backside of the pack- age is electrically connected to the VEE pins on the IC die. The package base should be soldered to a heat spreading pad on the PC board that is electrically connected to VEE.
RF
1k
+– VIN
RG
1k 10k
10k 10k
9 +IN
8 –IN
ISNK
17
ISRC
16
TSD
+
GM1
–
–
D1
+
ISNK +–
1
VSNK
VCC
7
V+
19
Q1
OUT
3
Q2
+
15V
RCS
15V
5V
18
15 ENABLE VCSNK
12
VCSRC
13
+
–
14 COMMON
ENABLE VCSNK
VCSRC
D2
ISRC
+– VSRC
RFIL
1k
SENSE
4
FILTER
5
SENSE–
6
V–
2
VEE
1Q
–15V
RLOAD
1k
1, 10, 11, 20
1970ATC
The LT1970A power op amp with precision controllable current limit is a flexible voltage and current source module. The drawing on the front page of this data sheet is representative of the basic application of the circuit, however many alternate uses are possible with proper understanding of the sub circuit capabilities.
Sub circuit block GM1, the 1X unity-gain current buf- fer and output transistors Q1 and Q2 form a standard operational amplifier. This amplifier has ± 500mA current output capability and a 3.6MHz gain-bandwidth product. Most applications of the LT1970A will use this op amp in the main signal path. All conventional op amp circuit configurations are supported. Inverting, noninverting, filter, summation or nonlinear circuits may be implemented in
a conventional manner. The output stage includes current limiting at ±800mA to protect against fault conditions. The input stage has high differential breakdown of 36V minimum between –IN and +IN. No current will flow at the inputs when differential input voltage is present. This feature is important when the precision current sense amplifiers “ISINK” and “ISRC” become active.
Amplifier stages “ISINK” and “ISRC” are very high transcon- ductance amplifier stages with independently controlled offset voltages. These amplifiers monitor the voltage between input pins SENSE+ and SENSE– which usually sense the voltage across a small external current sense resistor. The transconductance amplifiers outputs con- nect to the same high impedance node as the main input stage GM1 amplifier. Small voltage differences between SENSE+ and SENSE–, smaller than the user set VCSNK/10
and VCSRC/10 in magnitude, cause the current limit ampli- fiers to decouple from the signal path. This is functionally indicated by diodes D1 and D2 in the Block Diagram. When the voltage VSENSE increases in magnitude sufficient to equal or overcome one of the offset voltages VCSNK/10 or VCSRC/10, the appropriate current limit amplifierbecomes activeandbecauseofitsveryhightransconductance, takes control from the input stage, GM1. The output current is regulated to a value of IOUT = VSENSE/RSENSE = (VCSRC or VCSNK)/(10 • RSENSE). The time required for the current limit amplifiers to take control of the output is typically 4µs.
Linear operation of the current limit sense amplifier occurs with the inputs SENSE+ and SENSE– ranging be- tween VCC – 1.5V and VEE + 1.5V. Most applications will connect pins SENSE+ and OUT together, with the load on the opposite side of the external sense resistor and pin SENSE–. Feedback to the inverting input of GM1 should be connected from SENSE– to – IN. Ground side sensing of load current may be employed by connecting the load between pins OUT and SENSE+. Pin SENSE– would be connected to ground in this instance. Load current would be regulated in exactly the same way as the conventional connection. However, voltage mode accuracy would be degraded in this case due to the voltage across RSENSE.
Creative applications are possible where pins SENSE+ and SENSE– monitor a parameter other than load current. The operating principle that at most one of the current limit stages may be active at one time, and that when active, the current limit stages take control of the output from GM1, can be used for many different signals.
Input pins VCSNK and VCSRC are used to set the response thresholds of current limit amplifiers “ISINK” and “ISRC”. Each of these inputs may be independently driven by a voltage of 0V to 5V above the COMMON reference pin. The 0V to 5V input voltage is attenuated by a factor of 10 and applied as an offset to the appropriate current limit amplifier. AC signals may be applied to these pins. The AC bandwidth from a VC pin to the output is typically 2MHz. For proper operation of the LT1970A, these control inputs cannot be left floating.
For low VCC supply applications it is important to keep the maximum input control voltages, VCSRC and VCSNK, at least 2.5V below the VCC potential. This ensures linear control of the current limit threshold. Reducingthecurrent limit sense resistor value allows high output current from a smaller control voltage which may be necessary if the VCC supply is only 5V.
The transfer function from VC to the associated VOS is linear from about 0.1V to 5V in, or 10mV to 500mV at the current limit amplifier inputs. An intentional nonlinear- ity is built into the transfer functions at low levels. This nonlinearity ensures that both the sink and source limit amplifiers cannot become active simultaneously. Simul- taneous activation of the limit amplifiers could result in uncontrolled outputs. As shown in the Typical Performance Characteristics curves, the control inputs have a “hockey stick” shape, to keep the minimum limit threshold at 4mV for each limit amplifier.
Figure 1 illustrates an interesting use of the current sense input pins. Here the current limit control ampli- fiers are used to produce a symmetrically limited output voltage swing. Instead of monitoring the output current, the output voltage is divided down by a factor of 20 and applied to the SENSE+ input, with the SENSE– input grounded. When the threshold voltage between SENSE+ and SENSE– (VCLAMP/10) is reached, the current limit stage takes control of the output and clamps it a level of
±2 • VCLAMP. With control inputs VCSRC and VCSNK tied together, a single polarity input voltage sets the same + and – output limit voltage for symmetrical limiting. In this circuit the output will current limit at the built-in fail-safe level of typically 800mA.
The ENABLE input pin puts the LT1970A into a low sup- ply current, high impedance output state. The ENABLE pin responds to TTL threshold levels with respect to the COMMON pin. Pulling the ENABLE pin low is the best way to force zero current at the output. Setting VCSNK = VCSRC = 0V allows the output current to remain as high as ± 4mV/RSENSE.
VCLAMP OV TO 5V
VCSRC
12V
R3
3k
±CLAMP
80mV TO 10V
–80mV
TO
VOUT 1V/DIV
V VIN = 0.5V | VIN = –0.5V |
0V
EN
VCSNK VIN +IN
EN
VCC
V+
ISRC
ISNK
TSD
REACHED –10VOUTPUT CLAMPS
AT 2 VCLAMP
5V ENABLE
0V DISABLE
5V
10V/DIV 0
5µs/DIV
LT1970A
SENSE+ OUT SENSE–
R1
21.5k RL
VCSRC
12V
–IN COMMON
VEE
FILTER V–
R2 1.13k
VIN
VCSNK
EN
+IN
VCC V+
R
ISRC
ISNK S
TSD 1Q
–12V
RG RF
1970A F01
LT1970A
SENSE+ OUT
SENSE– RL
–IN COMMON
VEE
FILTER V–
10Q
In applications such as circuit testers (ATE), it may be preferable to apply a predetermined test voltage with a preset current limit to a test node simultaneously. The
RG
10k
–12V
RF
10k
1970A F02
ENABLE pin can be used to provide this gating action as shown in Figure 2. While the LT1970A is disabled, the load is essentially floating and the input voltage and current limit control voltages can be set to produce the load test levels. Enabling the LT1970A then drives the load. The LT1970A enables and disables in just a few microseconds. The actual enable and disable times at the load are a function of the load reactance.
The LT1970A has three digital output indicators; TSD, ISRC and ISNK. These outputs are open-collector drivers referred to the COMMON pin. The outputs have 36V ca- pabilities and can sink in excess of 10mA. ISRC and ISNK indicate activation of the associated current limit amplifier. The TSD output indicates excessive die temperature has caused the circuit to enter thermal shutdown. The three digital outputs may be wire “ORed” together, monitored individually or left open. These outputs do not affect circuit operation, but provide an indication of the present operational status of the chip.
Forslowvaryingoutputsignals, the assertion of alow level at the current limit output flags occurs when the current limit threshold is reached. For fast moving signals where the LT1970A output is moving at the slew limit, typically 1.6V/µs, the flag assertion can be somewhat premature at typically 75% of the actual current limit value.
The operating status flags are designed to drive LEDs to provide a visual indication of current limit and thermal conditions. As such, the transition edges to and from the active low state are not particularly sharp and may exhibit some uncertainty. Adding some positive feedback to the current limit control inputs helps to sharpen these transitions.
With the values shown in Figure 3, the current limit thresh- old is reduced by approximately 0.5% when either current limit status flag goes low. With sharp logic transitions, the status outputs can be used in a system control loop to take protective measures when a current limit condition is detected automatically.
CURRENT
LIMIT CONTROL
R2 100Q
R1 100Q
R3
20k
R4
20k
ISOURCE FLAG
500mA
50mA
IMAX
ILOW
VOLTAGE (0.1V TO 5V)
ISINK
FLAG
IOUT 0
VCSRC
VCSNK VIN +IN
EN
VCC
12V
V+
ISRC
WHEN CURRENT LIMIT IS FLAGGED, ILIMIT TRESHOLD IS REDUCED BY 0.5%
RS
–500mA
IMAX
≈ VCC • R2 (R1 + R2) • 10 • RS
VCC • (R2||R3)
LT1970A
ISNK
TSD 1Q
SENSE+ OUT
SENSE– RL
12V
R1 54.9k
R2 R3
ILOW ≈ [R1 + (R2||R3)] • 10 • RS
–IN COMMON
VEE
FILTER V–
39.2k
VCSRC
2.55k
RG –12V RF
1970A F03
VCSNK VIN +IN EN
VCC
V+
R
ISRC
ISNK S
TSD 1Q
LT1970A
SENSE+ OUT
SENSE– RL
The current limit status flag can also be used to produce a dramatic change in the current limit value of the ampli-
–IN COMMON
VEE
FILTER V–
fier. Figure 4 illustrates a “snap-back” current limiting characteristic. In this circuit, a simple resistor network initially sets a high value of current limit (500mA). The
RG
10k
–12V
RF
10k
1970A F04
circuit operates normally until the signal is large enough to enter current limit. When either current limit flag goes low, the current limit control voltage is reduced by a factor of
10. This then forces a low level of output current (50mA) until the signal is reduced in magnitude. When the load current drops below the lower level, the current limit is then restored to the higher value. This action is similar to a self resettable fuse that trips at dangerously high current levels and resets only when conditions are safe to do so.
The LT1970A can operate with up to 36V total supply volt- age with output currents up to ± 500mA. The amount of power dissipated in the chip could approach 18W under worst-case conditions. This amount of power will cause die temperature to rise until the circuit enters thermal
shutdown. While the thermal shutdown feature prevents damage to the circuit, normal operation is impaired. Thermal design of the LT1970A operating environment is essential to getting maximum utility from the circuit.
The first concern for thermal management is minimizing the heat which must be dissipated. The separate power pins V+ and V– can be a great aid in minimizing on-chip power. The output pin can swing to within 1.0V of V+ or V– even under maximum output current conditions. Using separate power supplies, or voltage regulators, to set V+ and V– to their minimum values for the required output swing will minimize power dissipation. The supplies VCC and VEE may also be reduced to a minimal value, but these supply pins do not carry high currents, and the power saving is much less. VCC and VEE must be greater than the maximum output swing by 1.5V or more.
When V– and V+ are provided separately from VCC and VEE, care must be taken to ensure that V– and V+ are always
less than or equal to the main supplies in magnitude. Protection Schottky diodes may be required to ensure this in all cases, including power on/off transients.
Operation with reduced V+ and V– supplies does not affect any performance parameters except maximum output swing. All DCaccuracyand ACperformancespecifications guaranteed with VCC = V+ and VEE = V– are still valid with the reduced output signal swing range.
The power dissipated in the LT1970A die must have a path to the environment. With 100°C/W thermal resistance in free air with no heat sink, the package power dissipation is limited to only 1W. The 20-pin TSSOP package with exposed copper underside is an efficient heat conductor if it is effectively mounted on a PC board. Thermal resis- tances as low as 40°C/W can be obtained by soldering the bottom of the package to a large copper pattern on the PC board. For operation at 85°C, this allows up to 1.625W of power to be dissipated on the LT1970A. At 25°C operation, up to 3.125W of power dissipation can be achieved. The PC board heat spreading copper area must be connected to VEE.
Figure 5 shows examples of PCB metal being used for heat spreading. These are provided as a reference for what might be expected when using different combina- tions of metal area on different layers of a PCB. These examples are with a 4-layer board using 1oz copper on each layer. The most effective layers for spreading heat are those closest to the LT1970A junction. Soldering the exposed thermal pad of the TSSOP package to the board produces a thermal resistance from junction-to-case of approximately 3°C/W.
As a minimum, the area directly beneath the package on all PCB layers can be used for heat spreading. However, limiting the area to that of the metal heat sinking pad is not very effective. Expanding the area on various layers significantly reduces the overall thermal resistance. The addition of vias (small 13 mil holes which fill during PCB
plating) connecting all layers of metal also helps reduce the operating temperature of the LT1970A. These are also shown in Figure 5.
It is important to note that the metal planes used for heat sinking are connecting electrically to VEE. These planes must be isolated from any other power planes used in the PCB design.
Another effective way to control the power amplifier operat- ing temperature is to use airflow over the board. Airflow can significantly reduce the total thermal resistance as also shown in Figure 5.
The LT1970A is much more tolerant of capacitive loading than most operational amplifiers. In a worst-case con- figuration as a voltage follower, the circuit is stable for capacitive loads less than 2.5nF. Higher gain configurations improve the CLOAD handling. If very large capacitive loads are to be driven, a resistive decoupling of the amplifier from the capacitive load is effective in maintaining stability and reducing peaking. The current sense resistor, usually
connected between the output pin and the load can serve as a part of the decoupling resistance.
Load inductance is usually not a problem at the outputs of operational amplifiers, but the LT1970A can be used as a high output impedance current source. This condition may be the main operating mode, or when the circuit enters a protective current limit mode. Just as load capacitance degrades the phase margin of normal op amps, load inductance causes a peaking in the loop response of the feedback controlled current source. The inductive load may be caused by long lead lengths at the amplifier output. If the amplifier will be driving inductive loads or long lead lengths (greater than 4 inches) a 500pF capacitor from the SENSE– pin to the ground plane will cancel the inductive
load and ensure stability.
STILL AIR JA | PACKAGE | TOP LAYER | 2ND LAYER | 3RD LAYER | BOTTOM LAYER |
TSSOP 100°C/W | |||||
TSSOP 50°C/W | |||||
TSSOP 45°C/W |
0
REDUCTION IN JA (%)
–10
–20
–30
–40
–50
% REDUCTION RELATIVE TO JA IN STILL AIR | |||||||||
1970A F05a
–60
0 100 200 300 400 500 600 700 800 900 1000
AIRFLOW (LINEAR FEET PER MINUTE, lfpm)
1970A F05b
5V
VIN
0V
5V
VCSRC
12V
SOURCING SINKING
VCSNK
+IN EN
VCC V+
ISRC
ISNK
TSD
D1 1N4001
RS
1
±500mA
12V
R1
LT1970A
SENSE+ OUT SENSE–
MAGNETIC
95.3K
LT1634-2.5
2.5V
–IN COMMON
VEE
FILTER V–
C1
D2 1N4001
1970A F06
TRANSDUCER
–12V
500pF
OPTIONAL TEST PIN ON/OFF CONTROL
APPLY LOAD DRIVE
5V
1024
0V Hi-Z 5V
VOUT = 15V (CODE C – CODE D)≈ ±15V
VCC
CLR
VREF
ISOURCE(MAX)
= 0.5 • CODE B ≈ –4mA TO –500mA
1024 • RS
DAC A
ISINK(MAX) = 0.5 • CODE A ≈ 4mA TO 500mA
1024 • R
S
CS/LD SCK DI
3-WIRE SERIAL INTERFACE
DECODER
DAC B
DAC C
R1 3.4k
R2 10.2k
VCSRC
VCSNK
+IN
18V
R5
3k
EN
+
VCC
V
ISRC
R6 +
3k 10µF 0.1µF
RS
LT1970A
R3
ISNK
TSD
SENSE+ OUT
SENSE–
1Ω FORCE
TEST PIN
DAC D
3.4k
–IN COMMON
VEE
FILTER V–
+
10µF 0.1µF
SENSE
LOAD
LTC1664 QUAD 10-BIT DAC
R4 10.2k
–18V
1970A F07
1970afc
Figure 6 shows the LT1970A driving an inductive load with a controlled amount of current. This load is shown as a generic magnetic transducer, which could be used to create and modulate a magnetic field. Driving the current limit control inputs directly forces a current through the load that could range up to 2MHz in modulation. Clamp diodes are added to protect the LT1970A output from large inductive flyback potentials causedbyrapiddi/dtchanges.
The LT1970A can supply large currents from the power supplies to a load at frequencies up to 4MHz. Power supply impedance must be kept low enough to deliver these currents without causing supply rails to droop. Low ESR capacitors, such as 0.1µF or 1µF ceramics, located close to the pins are essential in all applications. When large, high speed transient currents are present additional capacitance may be needed near the chip. Check supply rails with a scope and if signal related ripple is seen on the supply rail, increase the decoupling capacitor as needed.
To ensure proper start-up biasing of the LT1970A, it is recommended that the rate of change of the supply volt- ages at turn-on be limited to be no faster than 6V/µs.
The digitally controlled analog pin driver is shown in Figure 7. All of the control signals are provided by an LTC®1664 quad, 10-bit DAC by way of a 3-wire serial interface. The LT1970A is configured as a simple differ- ence amplifier with a gain of 3. This gain is required to produce ±15V from the 0V to 5V outputs from DACs C and D. To provide voltage headroom, the supplies for the LT1970A are set to the maximum value of ±18V. As ±18V is the absolute maximum rating of supply voltage for the LT1970A, care must be taken to not allow the supply voltage to increase. DACs A and B separately control the sinking and sourcing current limit to the load over the range of
± 4mA to ±500mA. An optional on/off control for the pin driver using the ENABLE input is shown. If always enabled the ENABLE pin should be tied to VCC.
In some applications it may be necessary to know what the current into the load is at any time. Figure 8 shows an
LT1787 high side current sense amplifier monitoring the current through sense resistor RS. The LT1787 is biased from the VEE supply to accommodate the common mode input range of ±10V. The sense resistor is scaled down to provide a 100mV maximum differential signal to the current sense amplifier to preserve linearity. The LT1880 amplifier provides gain and level shifting to produce a 0V to 5V output signal (2.5V DC ±5mV/mA) with up to 1kHz full-scale bandwidth. An A/D converter could then digi- tize this instantaneous current reading to provide digital feedback from the circuit.
The LT1970A is just as easy to use as a standard opera- tional amplifier. Basic amplification of a precision reference voltage creates a very simple bench DC power supply as shown in Figure 9. The built-in power stage produces an adjustable 0V to 25V at 4mA to 100mA of output current. Voltage and current adjustments are derived from the LT1634-5 5V reference. The output current capability is 500mA, but this supply is restricted to 100mA for power dissipation reasons. The worst-case output voltage for maximum power dissipated in the LT1970A output stage occurs if the output is shorted to ground or set to a voltage near zero. Limiting the output current to 100mA sets the maximum power dissipation to 3W. To allow the output to range all the way to 0V, an LTC1046 charge pump inverter is used to develop a –5V supply. This produces a negative rail for the LT1970A which has to sink only the quiescent current of the amplifier, typically 7mA.
Usingasecond LT1970A, a 0Vto±12Vdualtrackingpower supply is shown in Figure 10. The midpoint of two 10k resistors connected between the + and – outputs is held at 0V by the LT1881 dual op amp servo feedback loop. To maintain 0V, both outputs must be equal and opposite in polarity, thus they track each other. If one output reaches current limit and drops in voltage, the other output fol- lows to maintain a symmetrical + and – voltage across a common load. Again, the output current limit is less than the full capability of the LT1970A due to thermal reasons. Separate current limit indicators are used on each LT1970A because one output only sources current and the other only sinks current. Both devices can share the same thermal shutdown indicator, as the output flags can be ORed together.
VCC 0V TO 1V
VCSRC
VCSNK
+IN
EN
VCC
12V
V+
ISRC
ISNK
TSD
RS 0.2Ω
LT1970A
SENSE+ OUT SENSE–
RLOAD
–IN COMMON
VEE
FILTER V–
LT1787
V – V +
R4 255k
RG RF
–12V
–12V
S
VEE
S BIAS
20k
R1 –12V
60.4k
R2
10k
R3
20k
12V
LT1880
–12V
VOUT 2.5V
±5mV/mA
1kHz FULL CURRENT BANDWIDTH
0V TO 5V A/D
1970A F08
OPTIONAL DIGITAL FEEDBACK
R1 2.1k
R2 40k
R3
10k
R4 10k OUTPUT VOLTAGE ADJUST
CURRENT LIMIT ADJUST
VCSRC
VCSNK
+IN
EN
VCC V+
ISRC
R5 5.49k
30V DC
LOAD FAULT
RS
LT1634-5
LT1970A
ISNK
TSD
SENSE+ OUT SENSE–
1Q VOUT
0V TO 25V
+
4mA TO 100mA C3
–IN COMMON
VEE
FILTER
V–
–5V
10µF
GND
RG 2.55k
RF 10.2k
LTC1046
+
+
C1 10µF
C2 10µF
1970A F09
15V R7
3k
R6 18.2k
R8 +
3k 0.1 10µF
R5
13k
VCSRC
VCSNK
–IN EN
VCC V+
ISRC
+OUT CURRENT LIMIT
THERMAL FAULT
RS1
LT1970A
ISNK
TSD
SENSE+ OUT SENSE–
1Ω
+ C2 10µF
+OUT
0V TO 12V
4mA TO 150mA
18V
R1 5V
+IN COMMON
VEE
FILTER V–
C1
R9
10k
6.19k
R3
REF
VOUT
–15V
1%
1µF
LT1634-5
23.2k
R4
R2
10k
ADJUST
15V
OPTIONAL SYMMETRY
10k
CURRENT LIMIT ADJUST
1/2 LT1881 R12
10k
R11
10k
R13 25.5k
1/2 LT1881
–15V
ADJUST 100Ω
+
–
GROUND
R14 10.7k
R15
3k
15V
TO TSD PIN OF +OUT
R10
10k 1%
VCSRC
VCSNK
–IN EN
VCC V+
ISRC
–OUT CURRENT LIMIT
RS2
LT1970A
ISNK
TSD 1Ω
SENSE+ OUT SENSE–
+
C3 10µF
–OUT
0V TO –12V
4mA TO 150mA
+IN COMMON
VEE
FILTER V–
1970A F10
+
10µF 0.1µF
–15V
Another simple linear power amplifier circuit is shown in Figure 11. This uses the LT1970A as a linear driver of a DC motor with speed control. The ability to source and sink the same amount of output current provides for bidirectional rotation of the motor. Speed control is managed by sensing the output of a tachometer built on to the motor. A typi- cal feedback signal of 3V/1000rpm is compared with the desired speed-set input voltage. Because the LT1970A is unity-gain stable, it can be configured as an integrator to force whatever voltage across the motor as necessary to match the feedback speed signal with the set input signal.
Additionally, the current limit of the amplifier can be ad- justed to control the torque and stall current of the motor. For reliability, a feedback scheme similar to that shown in Figure 4 can be used. Assuming that a stalled rotor will generate a current limit condition, the stall current limit can be significantly reduced to prevent excessive power dissipation in the motor windings.
OV TO 5V TORQUE/STALL CURRENT CONTROL
15V
VCSRC
VCSNK
For motor speed control without using a tachometer, the circuit in Figure 12 shows an approach. Using the enable feature of the LT1970A, the drive to the motor can be removed periodically. With no drive applied, the spinning motor presents a back EMF voltage proportional to its rotational speed. The LT1782 is a tiny rail-to-rail amplifier with a shutdown pin. The amplifier is enabled during this interval to sample the back EMF voltage across the motor. This voltage is then buffered by one-half of an LT1638 dual op amp and used to provide the feedback to the LT1970A integrator. When re-enabled the LT1970A will adjust the drive to the motor until the speed feedback voltage, com- pared to the speed-set input voltage, settles the output to a fixed value. A 0V to 5V signal for the motor speed input controls both rotational speed and direction.
The other half of the LT1638 is used as a simple pulse oscillator to control the periodic sampling of the motor back EMF.
Figure 13 shows how easy it is to boost the output current of the LT1970A. This ±5A power stage uses complemen- tary external N- and P-channel MOSFETs to provide the additional current. The output stage power supply inputs,
V+ and V–, are used to provide gate drive as needed. With
+IN
EN
VCC
LT1970A
V+
R
ISRC
ISNK S
TSD 1Ω
SENSE+ OUT SENSE–
12V DC
higher output currents, the sense resistor RCS, is reduced in value to maintain the same easy current limit control.
This Class B power stage is intended for DC and low frequency, <1kHz, applications as crossover distortion
15V
–IN COMMON
VEE
FILTER
V–
MOTOR
GND
becomes evident at higher frequencies.
Figure 13 shows some optional resistor dividers between
R1 1.2k
R2
10k
R3 1.2k
REVERSE R4 49.9k
FORWARD
–15V
R5 49.9k
C1
1µF
TACH FEEDBACK
3V/1000rpm
1970A F11
the output connections and the current sense inputs. They are required only if the load of this power stage is removed or at a very low current level. Large power devices with no load on them can saturate and pull the output voltage very close to the power supply rails. The current sense amplifiers operate properly with input voltages at least
–15V
1V away from the VCC and VEE supply rails. In boosted current applications, it may be necessary to attenuate the maximum output voltage levels by 1V before connecting to the sense input pins. This only slightly deceases the current limit thresholds.
OV TO 5V TORQUE/STALL CURRENT CONTROL
12V
R3
2k
FAULT/STALL
FWD
5V
R1
10k
VCSRC
VCSNK
MOTOR SPEED CONTROL
0V
REV
STOP
R2
20k
+IN
VCC V+
ISRC
ISNK
RS
TSD 1Ω
LT1970A
SENSE+ OUT SENSE–
12V DC
–IN COM
VEE
EN
FILTER V–
C1
MOTOR
2.5V AT 10mA
1µF
R14
10k
–12V
–
12V
+
1/2 LT1638
–12V
4.7µF
R6 49.9k
R15 100Ω
C2 0.01µF
SHDN
–
LT1782
+
–12V
R7
R4 100k
R5 120k
12V
12V
R13
10k
R12
10k
10k
1/2 LT1638
R8
20k
R10 D1
R9
20k
82.5k 1N4148
C3
R11 D2
µF
1970A F12
9.09k 1N4148
–12V
6.07
(.239)
4.95
(.195)
6.40 – 6.60* (.252 – .260)
4.95
(.195)
DETAIL A
6.60 0.10
4.50 0.10
2.74 (.108)
20 1918 17 16 15 14 1312 11
DETAIL A
2.74
BSC
6.40
1.98 (.078) REF
0.56 (.022)
SEE NOTE 4
0.45 0.05
1.05 0.10
0.65 BSC RECOMMENDED SOLDER PAD LAYOUT
1 2 3 4 5 6 7 8 9 10
(.108) (.252)
REF DETAIL A IS THE PART OF THE LEAD FRAME FEATURE
FOR REFERENCE ONLY
NO MEASUREMENT PURPOSE
4.30 – 4.50* (.169 – .177)
0.25
REF
0 – 8
6.07
(.239)
1.20
(.047) MAX
0.09 – 0.20
(.0035 – .0079)
NOTE:
0.50 – 0.75
(.020 – .030)
0.65
(.0256) BSC
0.195 – 0.30
(.0077 – .0118) TYP
0.05 – 0.15
(.002 – .006)
FE20 (CA) TSSOP REV K 0913
CONTROLLING DIMENSION: MILLIMETERS
DIMENSIONS ARE IN MILLIMETERS
4. RECOMMENDED MINIMUM PCB METAL SIZE FOR EXPOSED PAD ATTACHMENT
(INCHES) *DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH
3. DRAWING NOT TO SCALE
SHALL NOT EXCEED 0.150mm (.006") PER SIDE
REV | DATE | DESCRIPTION | PAGE NUMBER |
A | 06/12 | Corrected D1, D2 orientation in Block Diagram Changed supply voltage in Figure 12 | 10 21 |
B | 09/14 | Corrected TSD pin description | 9 |
C | 11/15 | Updated Package Drawing | 22 |
Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa- tion that the interconnecFtoiornmofoitrseciinrcfuoitrsmasatdieosncrwibwedwh.elirneienawr.cillonmot/iLnTfr1in9g7e0oAn existing patent rights.
1970afc
23
VCC
CURRENT LIMIT CONTROL VOLTAGE
0V TO 5V
15V
R1
1k
VCC ENABLE
R2 100Q
IRF9530
10µF
0.1µF
+IN
VCSRC
VCSNK
LT1970A
V+ SENSE+OUT
R4 100Q
R5
VIN
RG 2.2k
–IN VEE
SENSE–
COMMON *
V–
*
RF * *
2.2k
100Q
RCS 0.1Q
5W LOAD
IRF530
VEE
–15V
R3 100Q
*OPTIONAL, SEE TEXT
10µF
0.1µF
1970A F13
PART NUMBER | DESCRIPTION | COMMENTS |
Fast ±150mA Power Buffer | 20MHz Bandwidth, 75V/µs Slew Rate | |
250mA/60MHz Current Feedback Amplifier | Shutdown Mode, Adjustable Supply Current | |
1.1A/35MHz Current Feedback Amplifier | Stable with CL = 10,000pF | |
High Voltage Bidirectional Current Sense Amplifier | –5V to 80V Input Voltage Range |
24
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 950Fo3r5m-7o4re1i7nformation www.linear.com/LT1970A (408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com/LT1970A
1970afc
LT 1115 REV C • PRINTED IN USA
LINEAR TECHNOLOGY CORPORATION 2011
Mouser Electronics
Authorized Distributor
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