TSV991, TSV992, TSV994 TSV991A

TSV992A, TSV994A

Datasheet


Rail-to-rail input/output 20 MHz GBP operational amplifiers



Pin connections (top view)

Features

SOT23-5


DFN6 1.3x1.6x0.55

DFN8 2x2


MiniSO8, SO8, DFN8 2x2


Description

TSV991, TSV992, TSV994, TSV991A, TSV992A, TSV994A

Product status link

Related products

See TSV911, TSV912, TSV914, TSV911A, TSV912A, TSV914A


For unity-gain stable amplifiers

The TSV99x and TSV99xA family of single, dual, and quad operational amplifiers offers low voltage operation and rail-to-rail input and output. These devices feature an excellent speed/power consumption ratio, offering a 20 MHz gain-bandwidth, stable for gains above 4 (100 pF capacitive load), while consuming only 1.1 mA maximum at 5 V. They also feature an ultra-low input bias current. These characteristics make the TSV99x family ideal for sensor interfaces, battery-supplied and portable applications, as well as active filtering. These characteristics make the TSV99x, TSV99xA family ideal for sensor interfaces, battery-supplied and portable applications, as well as active filtering.



DS4975 - Rev 14 - June 2019

For further information contact your local STMicroelectronics sales office.


www.st.com


  1. Absolute maximum ratings and operating conditions


    Table 1. Absolute maximum ratings (AMR)


    Symbol

    Parameter

    Value

    Unit

    VCC

    Supply voltage (1)

    6


    V

    Vid

    Differential input voltage (2)

    ±VCC

    Vin

    Input voltage (3)

    (VCC-) - 0.2 to (VCC+) + 0.2

    Iin

    Input current (4)

    10

    mA

    Tstg

    Storage temperature

    -65 to 150


    °C

    Tj

    Maximum junction temperature

    150


    Rthja


    Thermal resistance junction to ambient (5) (6)

    DFN8 2x2

    57


    °C/W

    DFN6 1.3x1.6x0.55

    230

    SOT23-5

    250

    SO8

    125

    MiniSO8

    190

    SO14

    103

    TSSOP14

    100


    Rthjc


    Thermal resistance junction to case

    SOT23-5

    81

    SO8

    40

    MiniSO8

    39

    SO14

    31

    TSSOP14

    32


    ESD

    HBM: human body model (7)

    5

    kV

    MM: machine model (8)

    400


    V


    CDM: charged device model (9)

    SOT23-5, SO8, MiniSO8, DFN8 2x2

    1500

    DFN6 1.3x1.6x0.55

    TBD

    TSSOP14

    750

    SO14

    500


    Latch-up immunity

    200

    mA

    1. Value is with respect to the VCC- pin.

    2. Differential voltages are the non-inverting input terminal with respect to the inverting input terminal.

    3. VCC - VIN must not exceed 6 V.

    4. Input current must be limited by a resistor in series with the inputs.

    5. Short-circuits can cause excessive heating and destructive dissipation.

    6. Rth are typical values.

    7. Human body model: 100 pF discharged through a 1.5 kΩ resistor between two pins of the device, done for all couples of pin combinations with other pins floating.

    8. Machine model: 200 pF charged to the specified voltage, then discharged directly between two pins of the device with no external series resistor (internal resistor < 5 Ω), done for all couples of pin combinations with other pins floating.

    9. Charged device model: all pins plus packages are charged together to the specified voltage and then discharged directly to the ground.


      Table 2. Operating conditions


      Symbol

      Parameter

      Value

      Unit

      VCC

      Supply voltage

      2.5 to 5.5


      V

      Vicm

      Common mode input voltage range

      (VCC-) - 0.1 to (VCC+) + 0.1

      Top

      Operating free air temperature range

      -40 to 125

      °C


  2. Electrical characteristics


    Note: In the electrical characteristic tables below, all parameter limits at temperatures other than 25 °C are guaranteed by correlation.


    Table 3. Electrical characteristics at VCC+ = 2.5 V, VCC- = 0 V, Vicm = VCC/2, with RL connected to VCC/2, full temperature range (unless otherwise specified)


    Symbol

    Parameter

    Conditions

    Min.

    Typ.

    Max.

    Unit

    DC performance


    Vio


    Offset voltage, TSV99x

    Top = 25 °C


    0.1

    4.5


    mV

    Tmin < Top < Tmax



    7.5


    Offset voltage, TSV99xA

    Top = 25 °C



    1.5

    Tmin < Top < Tmax



    3

    ∆Vio/∆T

    Input offset voltage drift



    2


    μV/°C


    Iio

    Input offset current, Vout = VCC/2 (1)

    Top = 25 °C


    1

    10


    pA

    Tmin < Top < Tmax



    100


    Iib

    Input bias current, Vout = VCC/2

    Section 2 (1)

    Top = 25 °C


    1

    10

    Tmin < Top < Tmax



    100


    CMR

    Common mode rejection ratio, 20 log (ΔVic/ΔVio)

    0 V to 2.5 V, Vout = 1.25 V, Top = 25 °C

    58

    75



    dB

    Tmin < Top < Tmax

    53




    Avd


    Large signal voltage gain

    RL = 10 kΩ, Vout = 0.5 V to 2 V,

    Top = 25 °C


    80


    89


    Tmin < Top < Tmax

    75




    VCC - VOH


    High-level output voltage

    RL = 10 kΩ, Tmin < Top < Tmax


    15

    40


    mV

    RL = 600 Ω, Tmin < Top < Tmax


    45

    150


    VOL


    Low-level output voltage

    RL = 10 kΩ, Tmin < Top < Tmax


    15

    40

    RL = 600 Ω, Tmin < Top < Tmax


    45

    150


    Iout


    Isink

    Vo = 2.5 V, Top = 25 °C

    18

    32



    mA

    Tmin < Top < Tmax

    16




    Isource

    Vo = 0 V, Top = 25 °C

    18

    35


    Tmin < Top < Tmax

    16



    ICC


    Supply current (per channel)

    No load, Vout = VCC/2, Tmin < Top < Tmax



    0.78


    1.1

    AC performance


    GBP


    Gain bandwidth product

    RL = 2 kΩ, CL = 100 pF, f = 100 kHz, Top = 25 °C



    20



    MHz


    Gain


    Minimum gain for stability

    Phase margin = 45 °, Rf = 10 kΩ, RL = 2 kΩ, CL = 100 pF, Top = 25 °C,

    positive gain configuration



    4



    V/V


    Symbol

    Parameter

    Conditions

    Min.

    Typ.

    Max.

    Unit


    Gain


    Minimum gain for stability

    Phase margin = 45 °, Rf = 10 kΩ, RL = 2 kΩ, CL = 100 pF, Top = 25 °C,

    negative gain configuration



    -3



    V/V

    SR

    Slew rate

    RL = 2 kΩ, CL = 100 pF, Top = 25 °C


    10


    V/μs

    en

    Equivalent input noise voltage

    f = 10 kHz, Top = 25 °C


    21


    nV/√Hz


    THD+N


    Total harmonic distortion

    G = -3, f = 1 kHz, RL = 2 kΩ, Bw = 22

    kHz, Vicm = VCC/2, Vout = 2 Vpp, Top=25 °C



    0.0025



    %

    1. Guaranteed by design


    Table 4. Electrical characteristics at VCC+ = 3.3 V, VCC- = 0 V, Vicm = VCC/2, with RL connected to VCC/2, full temperature range (unless otherwise specified)


    Symbol

    Parameter

    Conditions

    Min.

    Typ.

    Max.

    Unit

    DC performance


    Vio


    Offset voltage, TSV99x

    Top = 25 °C


    0.1

    4.5


    mV

    Tmin < Top < Tmax



    7.5


    Offset voltage, TSV99xA

    Top = 25 °C



    1.5

    Tmin < Top < Tmax



    3

    ∆Vio/∆T

    Input offset voltage drift



    2


    μV/°C


    Iio

    Input offset current, Vout = VCC/2 (1)

    Top = 25 °C


    1

    10


    pA

    Tmin < Top < Tmax



    100


    Iib

    Input bias current, Vout = VCC/2

    Section 2 (1)

    Top = 25 °C


    1

    10

    Tmin < Top < Tmax



    100


    CMR

    Common mode rejection ratio, 20 log (ΔVic/ΔVio)

    0 V to 3.3 V, Vout = 1.65 V, Top = 25 °C

    60

    78



    dB

    Tmin < Top < Tmax

    55




    Avd


    Large signal voltage gain

    RL = 10 kΩ, Vout = 0.5 V to 2.8 V,

    Top = 25 °C


    80


    89


    Tmin < Top < Tmax

    75




    VCC - VOH


    High-level output voltage

    RL = 10 kΩ, Tmin < Top < Tmax


    15

    40


    mV

    RL = 600 Ω, Tmin < Top < Tmax


    45

    150


    VOL


    Low-level output voltage

    RL = 10 kΩ, Tmin < Top < Tmax


    15

    40

    RL = 600 Ω, Tmin < Top < Tmax


    45

    150


    Iout


    Isink

    Vo = 3.3 V, Top = 25 °C

    18

    32



    mA

    Tmin < Top < Tmax

    16




    Isource

    Vo = 0 V, Top = 25 °C

    18

    35


    Tmin < Top < Tmax

    16



    ICC


    Supply current (per channel)

    No load, Vout = VCC/2, Tmin < Top < Tmax



    0.8


    1.1

    AC performance


    Symbol

    Parameter

    Conditions

    Min.

    Typ.

    Max.

    Unit


    GBP


    Gain bandwidth product

    RL = 2 kΩ, CL = 100 pF, f = 100 kHz, Top = 25 °C



    20



    MHz


    Gain


    Minimum gain for stability

    Phase margin = 45 °, Rf = 10 kΩ, RL = 2 kΩ, CL = 100 pF, Top = 25 °C,

    positive gain configuration



    4



    V/V

    Phase margin = 45 °, Rf = 10 kΩ, RL = 2 kΩ, CL = 100 pF, Top = 25 °C,

    negative gain configuration



    -3



    SR


    Slew rate

    RL = 2 kΩ, CL = 100 pF, f = 100 kHz, Top = 25 °C



    10



    V/μs

    en

    Equivalent input noise voltage

    f = 10 kHz, Top = 25 °C


    21


    nV/√Hz


    THD+N


    Total harmonic distortion

    G = -3, f = 1 kHz, RL = 2 kΩ, Bw = 22

    kHz, Vicm = VCC/2, Vout = 2.8 Vpp,

    Top = 25 °C



    0.0018



    %

    1. Guaranteed by design.


    Table 5. Electrical characteristics at VCC+ = 5 V, VCC- = 0 V, Vicm = VCC/2, with RL connected to VCC/2, full temperature range (unless otherwise specified)


    Symbol

    Parameter

    Conditions

    Min.

    Typ.

    Max.

    Unit

    DC performance


    Vio


    Offset voltage, TSV99x

    Top = 25 °C


    0.1

    4.5


    mV

    Tmin < Top < Tmax



    7.5


    Offset voltage, TSV99xA

    Top = 25 °C



    1.5

    Tmin < Top < Tmax



    3

    ∆Vio/∆T

    Input offset voltage drift



    2


    μV/°C


    Iio

    Input offset current, Vout = VCC/2 (1)

    Top = 25 °C


    1

    10


    pA

    Tmin < Top < Tmax



    100


    Iib

    Input bias current, Vout = VCC/2

    Section 2 (1)

    Top = 25 °C


    1

    10

    Tmin < Top < Tmax



    100


    CMR


    Common mode rejection ratio, 20 log (ΔVic/ΔVio)

    0 V to 5 V, Vout = 2.5 V,

    Top = 25 °C


    62


    82



    dB

    Tmin < Top < Tmax

    57



    SVR

    Supply voltage rejection ratio, 20 log (ΔVcc/ΔVio)

    VCC = 2.5 V to 5 V

    70

    86



    Avd


    Large signal voltage gain

    RL = 10 kΩ, Vout = 0.5 V to 4.5 V,

    Top = 25 °C


    80


    91


    Tmin < Top < Tmax

    75




    VCC - VOH


    High-level output voltage

    RL = 10 kΩ, Tmin < Top < Tmax


    15

    40


    mV

    RL = 600 Ω, Tmin < Top < Tmax


    45

    150


    VOL


    Low-level output voltage

    RL = 10 kΩ, Tmin < Top < Tmax


    15

    40

    RL = 600 Ω, Tmin < Top < Tmax


    45

    150


    Symbol

    Parameter

    Conditions

    Min.

    Typ.

    Max.

    Unit


    Iout


    Isink

    Vo = 5 V, Top = 25 °C

    18

    32



    mA

    Tmin < Top < Tmax

    16




    Isource

    Vo = 0 V, Top = 25 °C

    18

    35


    Tmin < Top < Tmax

    16



    ICC


    Supply current (per channel)

    No load, Vout = 2.5 V, Tmin < Top < Tmax



    0.82


    1.1

    AC performance


    GBP


    Gain bandwidth product

    RL = 2 kΩ, CL = 100 pF, f = 100 kHz,

    Top = 25 °C



    20



    MHz


    Gain


    Minimum gain for stability

    Phase margin = 45 °, Rf = 10 kΩ, RL = 2 kΩ, CL = 100 pF, Top = 25 °C,

    positive gain configuration



    4



    V/V

    Phase margin = 45 °, Rf = 10 kΩ, RL = 2 kΩ, CL = 100 pF, Top=25 °C,

    negative gain configuration



    -3



    SR


    Slew rate

    RL = 2 kΩ, CL = 100 pF, f = 100 kHz,

    Top = 25 °C



    10



    V/μs

    en

    Equivalent input noise voltage

    f = 10 kHz, Top = 25 °C


    21


    nV/√Hz


    THD+N


    Total harmonic distortion

    G = -3, f = 1 kHz, RL = 2 kΩ, Bw = 22

    kHz, Vicm = VCC/2, Vout = 4.4 Vpp,

    Top = 25 °C



    0.0014



    %

    1. Guaranteed by design.


    Figure 5. Output current vs. output voltage at VCC = 2.5 V

    Figure 3. Supply current vs. input common-mode voltage at VCC = 2.5 V

    0

    10

    20

    30

    140


    120


    100


    80


    60


    40


    20


    0

    Quan tity of pa rts

    Quan tity of pa rts

  3. Electrical characteristic curves



    Figure 1. Input offset voltage distribution at T = 25 °C

    Figure 2. Input offset voltage distribution at T = 125 °C


    40


    Vcc= 5V Vicm =2.5V Ta mb =25°C

    °


    -5 -4 -3 -2 -1 0 1 2 3 4 5

    Input o ffs et Vo ltag e (mV)

    -5 -4 -3 -2 -1 0 1 2 3 4 5

    Input o ffs et Vo ltag e (mV)














































    Figure 4. Supply current vs. input common-mode voltage at VCC = 5 V



    Figure 6. Output current vs. output voltage at VCC = 5 V

    Phase (°)

    Phase (°)

    Figure 8. Voltage gain and phase vs. frequency at VCC = 5 V and Vicm = 2.5 V


    Figure 7. Voltage gain and phase vs. frequency at VCC = 5 V and Vicm = 0.5 V


    Figure 9. Positive slew rate

    Figure 10. Negative slew rate



    Vin : from 0. 5V to Vcc- 0. 5V

    S R : ca lculat ed from 10% to 90%











































    Vin : from 0. 5V to Vcc- 0. 5V

    S R : ca lculat ed from 10 % to 90 %










    Figure 11. Distortion + noise vs. frequency

    Figure 12. Distortion + noise vs. output voltage



    Figure 13. Noise vs. frequency

    Figure 14. Supply current vs. supply voltage

    Application information


  4. Application information


    1. Driving resistive and capacitive loads


      These products are low-voltage, low-power operational amplifiers optimized to drive rather large resistive loads above 2 kΩ.

      The TSV99x products are not unity gain stable. To ensure proper stability they must be used in a gain configuration, with a minimum gain of -3 or 4.

      However, they can be used in a “follower“ configuration by adding a small, in-series resistor at the output, which drastically improves the stability of the device (Figure 15. In-series resistor vs. capacitive load when TSV99x is used in follower configuration shows the recommended in-series resistor values). Once the in-series resistor value has been selected, the stability of the circuit should be tested on the bench and simulated with the simulation model.

      Another way to improve stability and reduce peaking is to add a capacitor in parallel with the feedback resistor. As shown in Figure 16. Peaking versus capacitive load, with or without feedback capacitor in inverting gain configuration, the feedback capacitor drastically reduces the peaking versus capacitive load (inverting gain configuration, gain = -2).



      Figure 16. Peaking versus capacitive load, with or without feedback capacitor in inverting gain configuration

      Figure 15. In-series resistor vs. capacitive load when TSV99x is used in follower configuration

    2. PCB layouts


      For correct operation, it is advised to add 10 nF decoupling capacitors as close as possible to the power supply pins.

    3. Macromodel


      An accurate macromodel of the TSV99x is available on STMicroelectronics’ web site at www.st.com. This model is a trade-off between accuracy and complexity (that is, time simulation) of the TSV99x operational amplifiers. It emulates the nominal performance of a typical device within the specified operating conditions mentioned in the datasheet. It helps to validate a design approach and to select the right operational amplifier, however, it does not replace on-board measurements.

      Package information


  1. Package information


    In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com. ECOPACK is an ST trademark.

    SOT23-5 package information



    1. SOT23-5 package information


      Figure 17. SOT23-5 package outline


      Table 6. SOT23-5 mechanical data



      Ref.

      Dimensions

      Millimeters

      Inches

      Min.

      Typ.

      Max.

      Min.

      Typ.

      Max.

      A

      0.90

      1.20

      1.45

      0.035

      0.047

      0.057

      A1



      0.15



      0.006

      A2

      0.90

      1.05

      1.30

      0.035

      0.041

      0.051

      B

      0.35

      0.40

      0.50

      0.014

      0.016

      0.020

      C

      0.09

      0.15

      0.20

      0.004

      0.006

      0.008

      D

      2.80

      2.90

      3.00

      0.110

      0.114

      0.118

      D1


      1.90



      0.075


      e


      0.95



      0.037


      E

      2.60

      2.80

      3.00

      0.102

      0.110

      0.118

      F

      1.50

      1.60

      1.75

      0.059

      0.063

      0.069

      L

      0.10

      0.35

      0.60

      0.004

      0.014

      0.024

      K

      0 degrees


      10 degrees

      0 degrees


      10 degrees


    2. DFN8 2 x 2 package information


      Figure 18. DFN8 2 x 2 package outline


      Table 7. DFN8 2 x 2 mechanical data



      Ref.

      Dimensions

      Millimeters

      Inches

      Min.

      Typ.

      Max.

      Min.

      Typ.

      Max.

      A

      0.51

      0.55

      0.60

      0.020

      0.022

      0.024

      A1



      0.05



      0.002

      A3


      0.15



      0.006


      b

      0.18

      0.25

      0.30

      0.007

      0.010

      0.012

      D

      1.85

      2.00

      2.15

      0.073

      0.079

      0.085

      D2

      1.45

      1.60

      1.70

      0.057

      0.063

      0.067

      E

      1.85

      2.00

      2.15

      0.073

      0.079

      0.085

      E2

      0.75

      0.90

      1.00

      0.030

      0.035

      0.039

      e


      0.50



      0.020


      L



      0.425



      0.017

      ddd



      0.08



      0.003


      Figure 19. DFN8 2 x 2 recommended footprint


      Note: The exposed pad of the DFN8 2x2 package is not internally connected. It can be set to ground or left floating.


    3. DFN6 1.3 x 1.6 x 0.55 package information


      Figure 20. DFN6 1.3 x 1.6 x 0.55 package outline


      Table 8. DFN6 1.3 x 1.6 x 0.55 mechanical data



      Ref.

      Dimensions

      Millimeters

      Inches

      Min.

      Typ.

      Max.

      Min.

      Typ.

      Max.

      A

      0.50

      0.55

      0.60

      0.020

      0.022

      0.024

      A1

      0.00

      0.02

      0.05

      0.000

      0.001

      0.002

      A3


      0.15



      0.006


      B

      0.15

      0.20

      0.25

      0.006

      0.008

      0.010

      D


      1.30



      0.051


      E


      1.60



      0.063


      e


      0.40



      0.016


      L

      0.453

      0.553

      0.653

      0.018

      0.022

      0.026

      N


      6



      0.236


      aaa


      0.05



      0.002


      bbb


      0.07



      0.003


      ccc


      0.10



      0.004


      ddd


      0.05



      0.002


      eee


      0.08



      0.003



      Figure 21. DFN6 1.3 x 1.6 x 0.55 recommended footprint

      MiniSO8 package information



    4. MiniSO8 package information


      Figure 22. MiniSO8 package outline


      Table 9. MiniSO8 package mechanical data



      Ref.

      Dimensions

      Millimeters

      Inches

      Min.

      Typ.

      Max.

      Min.

      Typ.

      Max.

      A



      1.1



      0.043

      A1

      0


      0.15

      0


      0.0006

      A2

      0.75

      0.85

      0.95

      0.030

      0.033

      0.037

      b

      0.22


      0.40

      0.009


      0.016

      c

      0.08


      0.23

      0.003


      0.009

      D

      2.80

      3.00

      3.20

      0.11

      0.118

      0.126

      E

      4.65

      4.90

      5.15

      0.183

      0.193

      0.203

      E1

      2.80

      3.00

      3.10

      0.11

      0.118

      0.122

      e


      0.65



      0.026


      L

      0.40

      0.60

      0.80

      0.016

      0.024

      0.031

      L1


      0.95



      0.037


      L2


      0.25



      0.010


      k



      ccc



      0.10



      0.004


    5. SO8 package information


      Figure 23. SO8 package outline



      Table 10. SO8 package mechanical data



      Ref.

      Dimensions

      Millimeters

      Inches

      Min.

      Typ.

      Max.

      Min.

      Typ.

      Max.

      A



      1.75



      0.069

      A1

      0.10


      0.25

      0.004


      0.010

      A2

      1.25



      0.049



      b

      0.28


      0.48

      0.011


      0.019

      c

      0.17


      0.23

      0.007


      0.010

      D

      4.80

      4.90

      5.00

      0.189

      0.193

      0.197

      E

      5.80

      6.00

      6.20

      0.228

      0.236

      0.244

      E1

      3.80

      3.90

      4.00

      0.150

      0.154

      0.157

      e


      1.27



      0.050


      h

      0.25


      0.50

      0.010


      0.020

      L

      0.40


      1.27

      0.016


      0.050

      L1


      1.04



      0.040


      k



      ccc



      0.10



      0.004

      SO14 package information



    6. SO14 package information


      Figure 24. SO14 package outline



      Table 11. SO14 package mechanical data



      Ref.

      Dimensions

      Millimeters

      Inches

      Min.

      Typ.

      Max.

      Min.

      Typ.

      Max.




      1.75



      0.069

      A

      1.35


      1.75

      0.05


      0.068

      A1

      0.10


      0.25

      0.004


      0.009

      A2

      1.10


      1.65

      0.04


      0.06

      B

      0.33


      0.51

      0.01


      0.02

      C

      0.19


      0.25

      0.007


      0.009

      D

      8.55


      8.75

      0.33


      0.34

      E

      3.80


      4.0

      0.15


      0.15

      e


      1.27



      0.05


      H

      5.80


      6.20

      0.22


      0.24

      h

      0.25


      0.50

      0.009


      0.02

      L

      0.40


      1.27

      0.015


      0.05

      k

      8° (max.)

      ddd



      0.10



      0.004

      TSSOP14 package information



    7. TSSOP14 package information


      Figure 25. TSSOP14 package outline


      aaa


      Table 12. TSSOP14 package mechanical data



      Ref.

      Dimensions

      Millimeters

      Inches

      Min.

      Typ.

      Max.

      Min.

      Typ.

      Max.

      A



      1.20



      0.047

      A1

      0.05


      0.15

      0.002

      0.004

      0.006

      A2

      0.80

      1.00

      1.05

      0.031

      0.039

      0.041

      b

      0.19


      0.30

      0.007


      0.012

      c

      0.09


      0.20

      0.004


      0.0089

      D

      4.90

      5.00

      5.10

      0.193

      0.197

      0.201

      E

      6.20

      6.40

      6.60

      0.244

      0.252

      0.260

      E1

      4.30

      4.40

      4.50

      0.169

      0.173

      0.176

      e


      0.65



      0.0256


      L

      0.45

      0.60

      0.75

      0.018

      0.024

      0.030

      L1


      1.00



      0.039


      k



      aaa



      0.10



      0.004

      Ordering information


  2. Ordering information


Table 13. Order code


Order code

Temperature range

Package

Packing

Marking

TSV991ILT


-40 °C to 125 °C


SOT23-5


Tape and reel

K130

TSV991AILT

K129

TSV991IQ2T


DFN8 2x2

K1F

TSV991AIQ2T

K1E

TSV991AIQ1T

DFN6 1.3x1.6x0.55

K5

TSV992IST


MiniSO8

K132

TSV992AIST

K135

TSV992IDT


SO8

V992I

TSV992AIDT

V992AI

TSV992IQ2T

DFN8 2x2

K38

TSV994IPT


TSSOP14

V994I

TSV994AIPT

V994AI

TSV994IDT


SO14

V994I

TSV994AIDT

V994AI

TSV991IYLT (1)


-40 °C to 125 °C

automotive grade


SOT23-5

K149

TSV991AIYLT (1)

K150

TSV992IYDT (1)


SO8

V992IY

TSV992AIYDT (1)

V992AY

TSV992IYST (1)


MiniSO8

K149

TSV992AIYST (1)

K150

TSV994IYDT (1)


SO14

V994IY

TSV994AIYDT (1)

V994AY

TSV994IYPT (1)


TSSOP14

V994IY

TSV994AIYPT (1)

V994AY

1. Qualified and characterized according to AEC Q100 and Q003 or equivalent, advanced screening according to AEC Q001 & Q 002 or equivalent.


Note: In the table above, all packages except the SO14 are "moisture sensitivity level 1" as per JEDEC J-STD-020-C. SO14 is JEDEC level 3.


Revision history



Table 14. Document revision history


Date

Revision

Changes

31-Jul-2006

1

Preliminary data release for product under development.

07-Nov-2006

2

Final version of datasheet.

12-Dec-2006

3

Noise and distortion figures added.


07-Jun-2007


4

ESD tolerance modified for SO14, CDM in Table 1: "Absolute maximum ratings (AMR)".

Automotive grade commercial products added in Table 13: "Order codes". Note about SO14 added in Table 13: "Order codes".

Limits in temperature added in Section 2: "Electrical characteristics".


11-Feb-2008


5

Corrected MiniSO8 package information.

Corrected footnote for automotive grade order codes in order code table. Improved presentation of package information.


25-May-2009


6

Added input current information in Table 1: "Absolute maximum ratings (AMR)". Added Section 3: "Application information".

Updated all packages in Section 4: "Package information".

Added new order codes: TSV991IYLT, TSV991AIYLT, TSV992IYST, TSV992AIYST,

TSV994IYPT, TSV994AIYPT in Table 13: "Order codes".


19-Oct-2009


7

Added A versions of devices in title on cover page.

Added parameters for full temperature range in Table 3, Table 4, and Table 5.

Removed gain margin and phase margin parameters in Table 3, Table 4, and Table 5. These parameters have been replaced by the gain parameter (minimum gain for stability).

Added Figure 14 and Figure 16.


14-Jan-2010


8

Added parameters for full temperature range in Table 3, Table 4, and Table 5.

Modified note relative to automotive grade in Table 13: "Order codes".


22-Oct-2012


9

Document status changed to production data. Modified gain value in Features and Description. Added DFN8 2x2 pin connection diagram.

Table 1: "Absolute maximum ratings (AMR)": added package DFN8 2x2 to rows Rthja and ESD.

Table 3, Table 4, and Table 5: replaced “DVio” with ΔVio/ΔT; modified “Gain” and “THD

+N” conditions and typical values.

Figure 7 and Figure 8: added arrows indicating “Gain” and ‘Phase”.


22-Oct-2012


9 cont’d

Figure 11 and Figure 12: updated.

Added Figure 18: "DFN8 2 x 2 mm (NB) package outline" and Figure 19: "DFN8 2 x 2 mm (NB) recommended footprint".

Table 13: "Order codes": updated automotive grade qualification and added order code of DFN8 package.

10-Mar-2014

10

Table 13: "Order codes": added new commercial product TSV991AIQ2T; corrected “Marking” error for TSV991IQ2T from K1E to K1F.


12-Jun-2015


11

Added DFN6 1.3 x 1.6 x 0.55 package for new order code TSV991AIQ1T. Updated "L" dimension of Section 4: "DFN8 2 x 2 mm (NB) package information".

Updated min "k" value of Section 4.5: "SO8 package information".


Date

Revision

Changes


27-Nov-2015


12

Table 3, Table 4, and Table 5: modified that RL = 600 Ω (not 600 kΩ) for the high-level and low-level output voltage parameters.

Section 5.2: updated name of package and titles of drawings and table; added note about exposed pad.

Section 5.3: updated name of package.

03-Apr-2018

13

Updated cover image and Table 13. Order code.

19-Jun-2019

14

Updated the related product table in cover page.

Contents


Contents

  1. Absolute maximum ratings and operating conditions 2

  2. Electrical characteristics 4

  3. Electrical characteristic curves 8

  4. Application information 11

    1. Driving resistive and capacitive loads 11

    2. PCB layouts 11

    3. Macromodel 11

  5. Package information 12

    1. SOT23-5 package information 13

    2. DFN8 2 x 2 package information 14

    3. DFN6 1.3 x 1.6 x 0.55 package information 15

    4. MiniSO8 package information 17

    5. SO8 package information 19

    6. SO14 package information 20

    7. TSSOP14 package information 21

  6. Ordering information 22

Revision history 23

@NA 28

List of tables


List of tables

Table 1. Absolute maximum ratings (AMR) 2

Table 2. Operating conditions 3

Table 3. Electrical characteristics at VCC+ = 2.5 V, VCC- = 0 V, Vicm = VCC/2, with RL connected to VCC/2, full temperature range (unless otherwise specified) 4

Table 4. Electrical characteristics at VCC+ = 3.3 V, VCC- = 0 V, Vicm = VCC/2, with RL connected to VCC/2, full temperature range (unless otherwise specified) 5

Table 5. Electrical characteristics at VCC+ = 5 V, VCC- = 0 V, Vicm = VCC/2, with RL connected to VCC/2, full temperature range (unless otherwise specified) 6

Table 6. SOT23-5 mechanical data 13

Table 7. DFN8 2 x 2 mechanical data 14

Table 8. DFN6 1.3 x 1.6 x 0.55 mechanical data 17

Table 9. MiniSO8 package mechanical data 18

Table 10. SO8 package mechanical data 19

Table 11. SO14 package mechanical data 20

Table 12. TSSOP14 package mechanical data 21

Table 13. Order code 22

Table 14. Document revision history 23

List of figures


List of figures

Figure 1. Input offset voltage distribution at T = 25 °C 8

Figure 2. Input offset voltage distribution at T = 125 °C 8

Figure 3. Supply current vs. input common-mode voltage at VCC = 2.5 V 8

Figure 4. Supply current vs. input common-mode voltage at VCC = 5 V 8

Figure 5. Output current vs. output voltage at VCC = 2.5 V 8

Figure 6. Output current vs. output voltage at VCC = 5 V 8

Figure 7. Voltage gain and phase vs. frequency at VCC = 5 V and Vicm = 0.5 V 9

Figure 8. Voltage gain and phase vs. frequency at VCC = 5 V and Vicm = 2.5 V 9

Figure 9. Positive slew rate 9

Figure 10. Negative slew rate 9

Figure 11. Distortion + noise vs. frequency 9

Figure 12. Distortion + noise vs. output voltage 9

Figure 13. Noise vs. frequency 10

Figure 14. Supply current vs. supply voltage 10

Figure 15. In-series resistor vs. capacitive load when TSV99x is used in follower configuration 11

Figure 16. Peaking versus capacitive load, with or without feedback capacitor in inverting gain configuration 11

Figure 17. SOT23-5 package outline 13

Figure 18. DFN8 2 x 2 package outline 14

Figure 19. DFN8 2 x 2 recommended footprint 15

Figure 20. DFN6 1.3 x 1.6 x 0.55 package outline 16

Figure 21. DFN6 1.3 x 1.6 x 0.55 recommended footprint 17

Figure 22. MiniSO8 package outline 18

Figure 23. SO8 package outline 19

Figure 24. SO14 package outline 20

Figure 25. TSSOP14 package outline 21


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TSV994AIPT TSV992AIDT TSV992AIST TSV992IST TSV992IDT TSV994IPT TSV994ID TSV994AID TSV991ILT TSV991AILT TSV992AID TSV992ID TSV994AIDT TSV994IDT TSV992AIYST TSV992IYST TSV991IYLT TSV991AIQ2T TSV991IQ2T TSV992IYDT TSV994IYDT TSV994AIYDT TSV991AIQ1T TSV994IYPT

TSV991AIYDT TSV994AIYPT TSV991AIYLT TSV992AIYDT TSV991IYDT TSV992AIDT/LIT