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TLV6003

SLOS981 – OCTOBER 2019

TLV6003 980-nA, 16-V, Precision, Rail-to-Rail Input and Output, Operational Amplifier

  1. Features

  2. Applications

  3. Description

    The TLV6003 is a nanopower operational amplifier consuming only 980 nA per channel, while offering very low maximum offset. Reverse battery protection guards the amplifier from an overcurrent condition due to improper battery installation. For harsh environments, the inputs can be taken 5 V greater than the positive supply rail without damage to the device.

    The low supply current is coupled with a low input bias current, enabling the device to be used with high series resistance input sources, such as PIR motion detectors and carbon monoxide sensors. DC accuracy is maintained with a low max offset voltage of 550 μV (25°C), a typical CMRR of 120 dB, and a minimum open-loop gain of 112 dB at 2.7 V.

    The maximum operating supply voltage is specified from 2.5 V to 16 V, with electrical characteristics specified at 2.7 V, 5 V, and 15 V. The 2.5-V operation makes this device compatible with Li-Ion battery- powered systems, making the TLV6003 a good choice for input signal gain and buffering into low- power microcontrollers, such as TI’s MSP430.

    The TLV6003 is available in a small SOT-23 package.

    Device Information(1)

    PART NUMBER

    PACKAGE

    BODY SIZE (NOM)

    TLV6003

    SOT-23 (5)

    2.90 mm x 1.60 mm

    1. For all available packages, see the package option addendum at the end of the data sheet.


PIR Motion Detector Buffer Offset Voltage vs Temperature

5 Typical Units Shown











































































































































800

700

600

500

Offset Voltage (V)

400

300

200


IR


+ TLV6003

VOUT

100

0

-100

-200

-300

-400

-500

-600

-700

-800

-55 -35 -15 5 25 45 65 85 105 125

Temperature (C)

C00


An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA.

Table of Contents

  1. Features 1

  2. Applications 1

  3. Description 1

  4. Revision History 2

  5. Pin Configuration and Functions 3

  6. Specifications 4

    1. Absolute Maximum Ratings 4

    2. ESD Ratings 4

    3. Recommended Operating Conditions 4

    4. Thermal Information – TLV6003 4

    5. Electrical Characteristics 5

    6. Typical Characteristics 7

  7. Detailed Description 12

    1. Overview 12

    2. Functional Block Diagram 12

    3. Feature Description 13

    4. Device Functional Modes 13

  8. Application and Implementation 14

    1. Application Information 14

    2. Typical Application 15

  9. Power Supply Recommendations 18

  10. Layout 18

    1. Layout Guidelines 18

    2. Layout Example 18

  11. Device and Documentation Support 19

    1. Device Support 19

    2. Documentation Support 19

    3. Receiving Notification of Documentation Updates 19 11.4 Community Resources 19

    1. Trademarks 19

    2. Electrostatic Discharge Caution 19

    3. Glossary 19

  1. Mechanical, Packaging, and Orderable Information 19

  1. Revision History


    DATE

    REVISION

    NOTES

    October 2019

    *

    Initial release.

  2. Pin Configuration and Functions


    DBV Package 5-pin SOT-23

    Top View


    OUT 1

    5 VCC

    +

    GND 2

    +IN 3

    4 IN

    Not to scale

    Pin Functions

    PIN


    I/O


    DESCRIPTION

    NAME

    DBV

    OUT

    1

    O

    Output

    GND

    2

    Negative (lowest) power supply

    +IN

    3

    I

    Noninverting input

    –IN

    4

    I

    Inverting input

    VCC

    5

    Positive (highest) power supply

  3. Specifications

    1. Absolute Maximum Ratings

      over operating free-air temperature range (unless otherwise noted)(1)


      MIN MAX

      UNIT

      VCC

      Supply voltage(2)

      –18 17

      V


      VIN+, VIN–


      Input voltage

      Singe-ended and common-mode input voltage, VICR

      –0.3 VCC + 5


      V

      Differential, VID

      ±20


      Input current (any input)

      ±10

      mA

      IO

      Output current

      ±10

      mA


      Continuous total power dissipation

      See Dissipation Rating


      TJ

      Maximum junction temperature

      –55 150

      °C

      Tstg

      Storage temperature

      –65 150

      °C

      1. Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

      2. All voltage values, except differential voltages, are with respect to GND


    2. ESD Ratings


      VALUE

      UNIT

      V(ESD)

      Electrostatic discharge

      Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)

      ±450


      V

      Charged-device model (CDM), per JEDEC specification JESD22-C101(2)

      ±1000

      1. JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

      2. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.


    3. Recommended Operating Conditions

      over operating free-air temperature range (unless otherwise noted)



      MIN NOM MAX

      UNIT

      VCC


      Supply Voltage

      Single Supply

      2.5 16


      V

      Split Supply

      ±1.25 ±8

      TA

      Operating free-air temperature

      –55 125

      °C


    4. Thermal Information – TLV6003


      THERMAL METRIC(1)

      TLV6003


      UNIT

      DBV

      5 PINS

      RθJA

      Junction-to-ambient thermal resistance

      166.0

      °C/W

      RθJC(top)

      Junction-to-case (top) thermal resistance

      89.9

      °C/W

      RθJB

      Junction-to-board thermal resistance

      36.5

      °C/W

      ψJT

      Junction-to-top characterization parameter

      14.0

      °C/W

      ψJB

      Junction-to-board characterization parameter

      36.3

      °C/W

      RθJC(bot)

      Junction-to-case (bottom) thermal resistance

      N/A

      °C/W

      (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.

    5. Electrical Characteristics

      at TA = 25°C, VCC = 2.7 V, 5 V, and 15 V, VICR = VO = VCC/2 (unless otherwise noted)

      PARAMETER

      TEST CONDITIONS

      MIN TYP MAX

      UNIT

      DC PERFORMANCE

      VIO

      Input offset voltage(1)


      390 ±550


      µV

      TA = –55°C to +125°C

      1500

      dVIO/dT

      Offset voltage drift

      TA = –55°C to +125°C

      2

      µV/°C


      CMRR


      Common-mode rejection ratio


      VICR = 0 V to VCC

      VCC = 2.7 V

      63 120


      dB

      VCC = 2.7 V,

      TA = –40°C to +125°C

      60

      VCC = 5 V

      66 120

      VCC = 5 V,

      TA = –40°C to +125°C

      63

      VCC = 15 V

      76 120

      VCC = 15 V,

      TA = –40°C to +125°C

      75

      AOL


      Open-loop gain

      VCC = 2.7 V, 0.2 V < VO < VCC – 0.2 V, RL = 500 kΩ

      112

      dB

      VCC = 15 V, 0.2 V < VO < VCC – 0.2 V, RL = 500 kΩ

      123

      dB

      INPUT


      IIO


      Input offset current


      25 250


      pA

      TA = –40°C to +125°C

      1200


      IIB


      Input bias current


      100 250


      pA

      TA = –40°C to +125°C

      2000

      ri(d)

      Differential input resistance


      300

      MΩ

      Ci(c)

      Common-mode input capacitance

      f = 100 kHz

      3

      pF

      DYNAMIC PERFORMANCE

      UGBW

      Unity gain bandwidth

      RL = 500 kΩ, CL = 100 pF

      5.5

      kHz

      SR

      Slew rate at unity gain

      VO(pp) = 0.8 V, RL = 500 kΩ, CL = 100 pF

      2.5

      V/ms

      PM

      Phase margin

      RL = 500 kΩ, CL = 100 pF

      60

      °


      Gain margin

      RL = 500 kΩ, CL = 100 pF

      15

      dB


      ts


      Settling time

      VCC = 2.7 or 5 V, V(STEP)PP = 1 V, AV = –1, CL = 100 pF, RL = 100 kΩ

      0.1%

      1.84


      ms

      VCC = 15 V, V(STEP)PP = 1 V,

      AV = –1, CL = 100 pF, RL = 100 kΩ

      0.1%

      6.1

      0.01%

      32

      NOISE PERFORMANCE

      Vn

      Equivalent input noise voltage

      f = 10 Hz

      800


      nV/√Hz

      f = 100 Hz

      500

      In

      Equivalent input noise current

      f = 100 Hz

      8

      fA/√Hz

      OUTPUT


      VOL


      Voltage output swing from the positive rail

      IOL = 2 µA (sourcing)


      VCC – 0.05 VCC – 0.02


      V

      TA = –40°C to +125°C

      VCC – 0.07

      IOL = 50 µA (sourcing)


      VCC – 0.08 VCC – 0.05

      TA = –40°C to +125°C

      VCC – 0.1


      VOH


      Voltage output swing from the negative rail

      IOH = 2 µA (sinking)


      0.090 0.150

      TA = –40°C to +125°C

      0.180

      IOH = 50 µA (sinking)


      0.180 0.230

      TA = –40°C to +125°C

      0.260

      IO

      Output current

      VO = 0.5 V from rail

      ±200

      μA

      (1) Input offset voltage and offset voltage drift are specified by characterization from TA = –55°C to +125°C. All other temperature specifications cover the range of TA = –40°C to +125°C, as listed in the test conditions column.

      Electrical Characteristics (continued)

      at TA = 25°C, VCC = 2.7 V, 5 V, and 15 V, VICR = VO = VCC/2 (unless otherwise noted)

      PARAMETER

      TEST CONDITIONS

      MIN TYP MAX

      UNIT

      POWER SUPPLY


      ICC


      Supply current

      VCC = 2.7 V and 5 V


      980 1200


      nA

      TA = –40°C to +125°C

      1350

      VCC = 15 V


      1000 1250

      TA = –40°C to +125°C

      1400


      Reverse supply current

      VCC = –18 V, VIN = 0 V, VO = open current

      50

      nA


      PSRR


      Power supply rejection ratio (ΔVCC/ΔVOS)

      VCC = 2.7 to 5 V, no load


      90 100


      dB

      TA = –40°C to 125°C

      85

      VCC = 5 to 15 V, no load


      100 110

      TA = –40°C to 125°C

      95

    6. Typical Characteristics

      at TA = 25°C and VCC = 5 V (unless otherwise noted)



      6


      5


      Frequency - %

      4


      3


      2


      1


      -600 -400 -200 0 200 400 600

      C002

      VIO - Input Offset Voltage - V


      Figure 1. Input Offset Voltage Histogram


      1400


      V IO – Input Offset Voltage – V

































































      1200


      1000


      800


      600


      400


      200


      0


      –200

      ––00.2.10 0.20 0.60 1.00 1.40 1.80 2.20 2.60 2.9

      VICR – Common-Mode Input Voltage – V

      VCC = 2.7 V

      Figure 2. Input Offset Voltage vs Common-Mode Input Voltage

      100


      V IO – Input Offset Voltage – V

      0


      –100


      –200


      –300

      400


      V IO – Input Offset Voltage – V

























































      300


      200


      100


      0


      –100


      –200


      –300















































      –400

      – 0.21 0.4 1.0 1.6 2.2 2.8 3.4 4.0 4.6 5.2


      –400

      – 0.21


      2.0 4.2 6.4 8.6 10.8 13.0 15.2

      VICR – Common-Mode Input Voltage – V

      VCC = 5 V

      Figure 3. Input Offset Voltage vs Common-Mode Input Voltage

      600

      VICR – Common-Mode Input Voltage – V

      VCC = 15 V

      Figure 4. Input Offset Voltage vs Common-Mode Input Voltage

      600


      I IB/ I IO – Input Bias / Offset Current – pA

      I IB/ I IO – Input Bias / Offset Current – pA

      500 500


      400 400


      300 300


      200 200


      100


      0


      –100


      IIO IIB


      100


      0


      –100


      IIO IIB

      –200

      –40 –25 –10 5 20 35 50 65 80 95 110 125

      TA – Free-Air Temperature – °C

      VCC = 2.7 V

      Figure 5. Input Bias Current and Offset Current vs Free-Air Temperature

      –200

      –40 –25 –10 5 20 35 50 65 80 95 110 125

      TA – Free-Air Temperature – °C

      VCC = 5.0 V

      Figure 6. Input Bias Current and Offset Current vs Common- Mode Input Voltage

      Typical Characteristics (continued)

      at TA = 25°C and VCC = 5 V (unless otherwise noted)

      I IB/ I IO – Input Bias / Offset Current – pA

      700


      600


      500


      400


      300


      200


      100

      IIO


      400

      I IB/ I IO – Input Bias / Offset Current – pA

      350

      300

      250

      200

      150

      100

      50

      0


      IIO

      0


      IIB

      –100


      –200

      –40 –25 –10 5 20 35 50 65 80 95 110 125

      –50

      –100

      –150

      –00..21


      IIB


      0.2 0.6 1.0 1.4 1.8 2.2 2.6 2.9

      TA – Free-Air Temperature – °C

      VCC = 15 V

      Figure 7. Input Bias Current and Offset Current vs Free-Air Temperature

      I IB/ I IO – Input Bias / Offset Current – pA

      200


      150

      VICR – Common Mode Input Voltage – V

      VCC = 2.7 V

      Figure 8. Input Bias Current and Offset Current vs Common- Mode Input Voltage

      I IB/ I IO – Input Bias / Offset Current – pA































      IIO













      IIB













      250


      200


      100


      50


      0


      –50


      –100


      IIO


      IIB


      150


      100


      50


      0


      –50


      –100


      –150

      0.12 0.4 1.0 1.6 2.2 2.8 3.4 4.0 4.6 5.2


      –150

      – 0.21


      2.0 4.2 6.4 8.6 10.8 13.0 15.2

      VICR – Common Mode Input Voltage – V

      VCC = 5.0 V

      Figure 9. Input Bias Current and Offset Current vs Common- Mode Input Voltage


      V


      , 15


      , 5


      2.


      =


      VCC

      CMRR – Common-Mode Rejection Ratio – dB

      120

      W

      7

      VICR – Common-Mode Input Voltage –V

      VCC = 15.0 V

      Figure 10. Input Bias Current and Offset Current vs Common-Mode Input Voltage

      2.7

      0

      10

      RF=

      100 k

      k

      RI=1

      W

      80


      60


      40


      20


      2.4


      V OH – High-Level Output Voltage – V

      2.1


      1.8


      1.5


      TA = –40°C


      TA = –0°C TA = 25 °C TA = 70 °C TA = 125 °C



      0

      1 10 100 1k 10k

      f – Frequency – Hz

      1.2


      0 50 100 150 200

      IOH – High-Level Output Current – A


      Figure 11. Common-Mode Rejection Ratio vs Frequency Figure 12. High-Level Output Voltage vs High-Level Output

      Current

      Typical Characteristics (continued)

      at TA = 25°C and VCC = 5 V (unless otherwise noted)

      1.50


      5.0



      VOL – Low-Level Output Voltage – V

      1.25


      1.00


      TA = 25 °C TA = 0 °C TA = –40°C


      V OH – High-Level Output Voltage – V

      4.5

      TA = –40°C



      0.75


      0.50


      0.25


      TA = 70 °C TA = 125 °C


      4.0


      3.5

      TA = –0°C TA = 25 °C TA = 70 °C TA = 125 °C


      0

      0 50 100 150 200

      IOL – Low-Level Output Current – A

      3.0


      0 50 100 150 200

      IOH – High-Level Output Current – A


      Figure 13. Low-Level Output Voltage vs Low-Level Output Current

      1.50

      Figure 14. High-Level Output Voltage vs High-Level Output Current

      15.0


      VOL – Low-Level Output Voltage – V

      1.25


      1.00


      0.75


      0.50


      0.25


      TA = 0 °C TA = –40°C


      TA = 25 °C TA = 70 °C TA = 125 °C


      14.5


      V OH – High-Level Output Voltage – V

      14.0


      13.5


      TA = –0°C TA = 25 °C TA = 70 °C TA = 125 °C


      TA = –40°C


      0

      0 50 100 150 200

      IOL – Low-Level Output Current – A

      13

      0 50 100 150 200

      IOH – High-Level Output Current – A


      Figure 15. Low-Level Output Voltage vs Low-Level Output Current

      1.50

      Figure 16. High-Level Output Voltage vs High-Level Output Current

      V O(PP) – Output voltage Peak–to–Peak – V

      16


      VOL – Low-Level Output Voltage – V

      1.25


      1.00


      0.75


      0.50


      0.25


      TA = –40°C


      TA = –0°C TA = 25 °C TA = 70 °C TA = 125 °C


      14


      12


      10


      8


      6


      VCC = 2.7 V

      4 VCC = 5 V 2

      0


      0

      0 50 100 150 200

      IOL – Low-Level Output Current – A


      –2

      10 100 1k

      f – Frequency – Hz


      Figure 17. Low-Level Output Voltage vs Low-Level Output Current

      Figure 18. Output Voltage Peak-to-Peak vs Frequency

      Typical Characteristics (continued)

      at TA = 25°C and VCC = 5 V (unless otherwise noted)

      10k


      1.4


      I CC – Supply Current – A/Ch

      1.2



      AV = 10

      Z o – Output Impedance –

      1k

      AV = 1

      1.0


      0.8


      100


      10

      100 1k 10k

      f – Frequency – Hz


      0.6


      0.4


      0.2


      0


      TA = 125°C TA = 70 °C TA = 25 °C TA = 0 °C TA = –40°C


      0 2 4 6 8 10 12 14 16

      VCC – Supply Voltage – V


      Figure 19. Output Impedance vs Frequency Figure 20. Supply Current vs Supply Voltage

      PSRR – Power Supply Rejection Ratio – dB

















































































































































      120 60 135

      110 50


      100


      90


      80


      70


      60


      50


      40

      10 100 1k 10k

      f – Frequency – Hz


      40


      AOL – Open-Loop Gain – dB

      30


      20


      10


      0


      –10


      –20


      90


      Phase – °

      45


      0


      –45

      10 100 1k 10k

      f – Frequency – Hz


      Figure 21. Power Supply Rejection Ratio vs Frequency Figure 22. Open-Loop Gain and Phase vs Frequency









































































      7 3.5


      GBWP –Gain Bandwidth Product – kHz

      SR – Slew Rate – V/ ms

      6 3.0


      5 2.5


      4 2.0


      3 1.5


      2 1.0


      1 0.5


      VCC = 5, 15 V


      SR–


      SR+


      VCC = 2.7 V


      VCC = 2.7, 5, & 15 V


      0

      2.5 4.0 5.5 7.0 8.5 10.0 11.5 13.0 14.5 16.0

      VCC – Supply Voltage –V

      0

      –40 –25 –10 5 20 35 50 65 80 95 110 125

      TA – Free-Air Temperature – °C


      Figure 23. Gain Bandwidth Product vs Supply Voltage Figure 24. Slew Rate vs Free-Air Temperature

      Typical Characteristics (continued)

      at TA = 25°C and VCC = 5 V (unless otherwise noted)

















































































































































      80 4


      Input Referred Voltage Noise – V

      70 3


      Phase Margin – °

      60 2


      50 1


      40 0


      30 –1


      20 –2


      10 –3


      0

      10 100


      1k 10k


      –4

      0 1 2 3 4 5 6


      7 8 9 10

      CL – Capacitive Load – pF

      t – Time – s


      Figure 25. Phase Margin vs Capacitive Load Figure 26. Voltage Noise Over a 10-Second Period

      8 4


      7 3

      6

      VIN

      V – Output Voltage – V

      V IN – Input Voltage – V

      2

      5 1

      4 0


      3 –1


      2 VO

      O

      1


      0

      2.0


      1.5


      V – Output Voltage – V

      1.0


      0.5


      0.0


      –0.5


      O

      –1.0


      –1.5

      3

      VIN 2


      V IN – Input Voltage – V

      1


      0


      –1


      VO


      –1

      –1 0 1 2 3 4 5 6

      t – Time – ms

      AV = 1

      Figure 27. Large-Signal Step Response


      –2

      –1 0 1 2 3 4 5 6 7

      t – Time – ms

      AV = –1

      Figure 28. Large-Signal Step Response

      180

      160

      V – Output Voltage – mV

      140

      120

      100

      80

      60

      O

      40

      20

      0


      VIN


      VO


      300

      150


      0

      –150

      200


      VO – Output Voltage – mV

      150


      100


      50


      0


      –50


      –100


      200


      V IN – Input Voltage – mV








      VIN































      VO











      100


      0


      –100

      V IN – Input Voltage – mV

      –20

      –50 0 50 100 150 200 250 300 350 400 450 500

      t – Time – ms

      AV = 1

      Figure 29. Small-Signal Step Response

      –150

      –200 0 200 400 600 800 1000 1200

      t – Time – ms

      AV = –1

      Figure 30. Small-Signal Step Response

  4. Detailed Description


    1. Overview

      The TLV6003 is a nanopower operational amplifier consuming only 980 nA per channel, while offering very low maximum offset. Reverse battery protection guards the amplifier from overcurrent conditions due to improper battery installation. The TLV6003 is based on a rail-to-rail bipolar technology that is specifically designed to allow high common-mode-range functionality. For harsh environments, the inputs can be taken 5 V greater than the positive supply rail without damage to the device. Offset is specified by characterization to an ambient temperature of –55°C, making the TLV6003 a good choice for low-temperature industrial automation.


    2. Functional Block Diagram


      VCC




      Class AB Control Circuitry

      VBIAS1


      IN+ IN-


      OUT

      VBIAS2


      GND

    3. Feature Description

      1. Reverse-Battery Protection

        The TLV6003 is protected against reverse-battery voltage up to 18 V. When subjected to reverse-battery conditions, the supply current is typically 50 nA at 25°C (inputs grounded and outputs open). This current is determined by the leakage of internal Schottky diodes, and therefore increases as the ambient temperature increases.

        When subjected to reverse-battery conditions, and negative voltages are applied to the inputs or outputs, the input ESD structure conducts current; limit this current to less than 10 mA. If the inputs or outputs are referred to ground rather than midrail, no extra precautions are required.


      2. Common-Mode Input Range

        The TLV6003 has rail-to-rail inputs and outputs. For common-mode inputs from –0.1 V to VCC – 0.8 V, a PNP differential pair provides the gain.

        For inputs between VCC – 0.8 V and VCC, two NPN emitter followers buffering a second PNP differential pair provide the gain.

        This special combination of a NPN and PNP differential pair enables the inputs to be taken 5 V greater than VCC. As the inputs rise to greater than VCC, the NPNs change from functioning as transistors to functioning as diodes. This change leads to an increase in input bias current. The second PNP differential pair continues to function normally as the inputs exceed VCC.

        The TLV6003 has a negative common-mode input voltage range that can fall to less than VGND by 100 mV. If the inputs are taken to less than VGND – 0.1, reduced open-loop gain will be observed.

        7.4 Device Functional Modes

        The TLV6003 has a single functional mode and is operational when the power-supply voltage is greater than 2.5

        V. The maximum specified power-supply voltage for the TLV6003 is 16 V.

  5. Application and Implementation


    NOTE

    Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.


    1. Application Information

      1. Drive a Capacitive Load

        The TLV6003 is internally compensated for stable unity-gain operation, with a 5.5-kHz typical gain bandwidth. However, the unity gain follower is the most sensitive configuration to capacitive load. The combination of a capacitive load placed directly on the output of an amplifier along with the amplifier output impedance creates a phase lag, which reduces the phase margin of the amplifier. If the phase margin is significantly reduced, the response will be underdamped, which causes peaking in the transfer function. This condition creates very low phase margin, and leads to excessive ringing or oscillations.

        In order to drive heavy (> 50 pF) capacitive loads, an isolation resistor (RISO) must be used, as shown in Figure 31. By using this isolation resistor, the capacitive load is isolated from the amplifier output. The higher the value of RISO, the more stable the amplifier. If the value of RISO is sufficiently high, the feedback loop is stable, independent of the value of CL. However, larger values of RISO result in reduced output swing and reduced output current drive. The recommended value for RISO is 30 kΩ to 50 kΩ.


        -


        VIN +

        RISO


        CL


        VOUT



        Figure 31. Resistive Isolation of Capacitive Load

    2. Typical Application

      Figure 32 shows a simple micropower potentiostat circuit for use with three-terminal unbiased CO sensors; although, the design is applicable to many other type of three-terminal gas sensors or electrochemical cells.

      The basic sensor has three electrodes: the sense or working electrode (WE), counter electrode (CE) and reference electrode (RE). A current flows between the CE and WE proportional to the detected concentration.

      The RE monitors the potential of the internal reference point. For an unbiased sensor, the WE and RE electrodes must be maintained at the same potential by adjusting the bias on CE. Through the potentiostat circuit formed by U1, the servo feedback action maintains the RE pin at a potential set by VREF.

      R1 maintains stability due to the large capacitance of the sensor.

      C1 and R2 form the potentiostat integrator and set the feedback time constant.

      U2 forms a transimpedance amplifier (TIA) to convert the resulting sensor current into a proportional voltage. The transimpedance gain, and resulting sensitivity, is set by RF according to Equation 1.

      VTIA = (–I * RF) + VREF (1)

      RL is a load resistor with a value that is normally specified by the sensor manufacturer (typically, 10 Ω). The potential at WE is set by the applied VREF.

      Riso provides capacitive isolation and, combined with C2, form the output filter and ADC reservoir capacitor to drive the ADC.


      R1 10 kO



      CE


      CO Sensor


      Potentiostat (Bias Loop) R2

      RE 10 kO


      VREF

      C1 0.1µF


      2.5V


      U1

      +


      WE


      ISENS


      Transimpedance Amplifier (I to V conversion)


      RF


      RL Riso

      49.9 kO

      U2


      VTIA

      VREF +


      C2

      1µF


      Figure 32. Three Terminal CO Gas Sensor

      Typical Application (continued)

      1. Design Requirements

        For this example, an electrical model of a CO sensor is used to simulate the sensor performance, as shown in Figure 33. The simulation is designed to model a CO sensor with a sensitivity of 69 nA/ppm. The supply voltage and maximum ADC input voltage is 2.5 V, and the maximum concentration is 300 ppm.



        260 mF

        CO Sensor Model


        CE


        300 0


        VCE



        µF



        2.5 V

        10 k0



        2 0 10 k0

        RE


        2 0

        10


        VREF +


        TLV6003


        130 mF

        300 0



        ISENS

        0 - 20 µA 110 k0

        VTIA


        10 0

        WE


        VREF +


        2.5 V


        TLV6003


        DESIGN PARAMETER

        EXAMPLE VALUE

        Supply voltage

        2.5 V

        Amplifier quiescent current

        < 2 µA

        Transimpedance amplifier sensitivity

        110 mV/µA

        Figure 33. CO Sensor Simulation Schematic Table 1. Design Parameters

      2. Detailed Design Procedure

        First, determine the VREF voltage. This voltage is a compromise between maximum headroom and resolution, as well as allowance for the minimum swing on the CE terminal because the CE terminal generally goes negative in relation to the RE potential as the concentration (sensor current) increases. Bench measurements found the difference between CE and RE to be 180 mV at 300 ppm for this particular sensor.

        To allow for negative CE swing, footroom, and voltage drop across the 10-kΩ resistor, 300 mV is chosen for VREF.

        Therefore, 300 mV is used as the minimum VZERO to add some headroom.

        VZERO = VREF = 300 mV

        where

        • VZERO is the zero concentration voltage.

        • VREF is the reference voltage (300 mV). (2)

          Next, calculate the maximum sensor current at highest expected concentration:

          ISENSMAX = IPERPPM * ppmMAX = 69 nA * 300 ppm = 20.7 µA

          where

        • ISENSMAX is the maximum expected sensor current.

        • IPERPPM is the manufacturer specified sensor current in Amps per ppm.

        • ppmMAX is the maximum required ppm reading. (3)

          Then, find the available output swing range greater than the reference voltage available for the measurement:

          VSWING = VOUTMAX – VZERO = 2.5 V – 0.3 V = 2.2 V

          where

        • VSWING is the expected change in output voltage

        • VOUTMAX is the maximum amplifer output swing (usually near VCC) (4)

          Finally, calculate the transimpedance resistor (RF) value using the maximum swing and the maximum sensor current:

          RF = VSWING / ISENSMAX = 2.2 V / 20.7 µA = 106.28 kΩ (use 110 kΩ for a common value) (5)


      3. Application Curve


        VTIA VCE ISENS

        2.5 V



        Voltage (1 V/div)

        Current (10 /div)

        0.3 V


        20 A


        Time (10 ms/div)


        C012

        Figure 34. Sensor Transient Response to Simulated 300-ppm CO Exposure

  6. Power Supply Recommendations

    The TLV6003 is specified for operation from 2.5 V to 16 V (±1.25 V to ±8 V) over a –40°C to +125°C temperature range.


    CAUTION

    Supply voltages larger than 17 V can permanently damage the device.


    For proper operation, the power supplies must be properly decoupled. For decoupling the supply lines, place 100 nF capacitors as close as possible to the operational amplifier power supply pins. For single-supply operation, place a capacitor between VCC and GND supply leads. For dual supplies, place one capacitor between VCC and ground, and one capacitor between GND and ground.

    Low-bandwidth nanopower devices do not have good high-frequency (> 1 kHz) AC PSRR rejection against high- frequency switching supplies and other 1-kHz and greater noise sources. Therefore, use extra supply filtering if kilohertz or greater noise is expected on the power supply lines.


  7. Layout


    1. Layout Guidelines

      • Bypass the VCC pin to ground with a low ESR capacitor.

      • The best placement is closest to the VCC and ground pins.

      • Take care to minimize the loop area formed by the bypass capacitor connection between VCC and ground.

      • Connect the ground pin to the PCB ground plane at the pin of the device.

      • Place the feedback components as close as possible to the device to minimize strays.


    2. Layout Example


      VOUT


      VCC


      CBYPASS


      Minimize parasitic inductance by placing bypass capacitor close to VCC.


      OUT


      VCC


      GND



      Keep high impedance input signal away from noisy traces.


      VIN

      -IN


      +IN

      RF

      Route trace under package for output to feedback resistor connection.

      Figure 35. SOT-23 Layout Example (Top View)

  8. Device and Documentation Support


    1. Device Support

      1. Development Support

    2. Documentation Support

      1. Related Documentation

For related documentation see the following:


    1. Receiving Notification of Documentation Updates

      To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper right corner, click on Alert me to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document.


    2. Community Resources

      TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight from the experts. Search existing answers or ask your own question to get the quick design help you need.

      Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use.

    3. Trademarks

      E2E is a trademark of Texas Instruments.

      All other trademarks are the property of their respective owners.

    4. Electrostatic Discharge Caution

      This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

      ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.


    5. Glossary

      SLYZ022 TI Glossary.

      This glossary lists and explains terms, acronyms, and definitions.


  1. Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

PACKAGE OPTION ADDENDUM


www.ti.com 6-Feb-2020


PACKAGING INFORMATION


Orderable Device

Status

(1)

Package Type

Package Drawing

Pins

Package Qty

Eco Plan

(2)

Lead/Ball Finish

(6)

MSL Peak Temp

(3)

Op Temp (°C)

Device Marking

(4/5)

Samples

TLV6003DBVR

ACTIVE

SOT-23

DBV

5

3000

Green (RoHS & no Sb/Br)

NIPDAU

Level-1-260C-UNLIM

-40 to 125

1NE9


(1) The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.


(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free".

RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.

Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement.


(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.


(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.


(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device.


(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width.


Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.


In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.


Addendum-Page 1

PACKAGE MATERIALS INFORMATION


www.ti.com 24-Oct-2019


TAPE AND REEL INFORMATION


*All dimensions are nominal

Device

Package Type

Package Drawing

Pins

SPQ

Reel Diameter (mm)

Reel Width W1 (mm)

A0

(mm)

B0

(mm)

K0

(mm)

P1

(mm)

W

(mm)

Pin1 Quadrant

TLV6003DBVR

SOT-23

DBV

5

3000

180.0

8.4

3.2

3.2

1.4

4.0

8.0

Q3


Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION


www.ti.com 24-Oct-2019



*All dimensions are nominal

Device

Package Type

Package Drawing

Pins

SPQ

Length (mm)

Width (mm)

Height (mm)

TLV6003DBVR

SOT-23

DBV

5

3000

210.0

185.0

35.0


Pack Materials-Page 2


DBV0005A

PACKAGE OUTLINE

SOT-23 - 1.45 mm max height


SCALE 4.000

SMALL OUTLINE TRANSISTOR



PIN 1 INDEX AREA


3.0

2.6

B

1.75

1.45 A

C


0.1

C

1.45

0.90


1 5


0.95

2X

3.05

1.9

1.9

2.75

2


4

5X

0.5 3

0.3


0.2

C

A

B


(1.1)


0.15

TYP

0.00


0.25

GAGE PLANE

0.22

TYP

TYP

0.08



0

8 TYP


0.6

0.3


SEATING PLANE


4214839/E 09/2019

NOTES:


  1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M.

  2. This drawing is subject to change without notice.

  3. Refernce JEDEC MO-178.

  4. Body dimensions do not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side.


    DBV0005A

    EXAMPLE BOARD LAYOUT

    SOT-23 - 1.45 mm max height

    SMALL OUTLINE TRANSISTOR



    1


    5X (0.6)


    5X (1.1)


    PKG


    5



    2

    2X (0.95)


    SYMM


    (1.9)


    3 4


    (R0.05) TYP

    (2.6)


    LAND PATTERN EXAMPLE

    EXPOSED METAL SHOWN SCALE:15X



    SOLDER MASK OPENING


    METAL


    METAL UNDER SOLDER MASK


    SOLDER MASK OPENING


    EXPOSED METAL


    0.07 MAX ARROUND

    EXPOSED METAL


    0.07 MIN ARROUND


    NON SOLDER MASK DEFINED (PREFERRED)


    SOLDER MASK DEFINED


    SOLDER MASK DETAILS


    4214839/E 09/2019

    NOTES: (continued)


  5. Publication IPC-7351 may have alternate designs.

  6. Solder mask tolerances between and around signal pads can vary based on board fabrication site.


    www.ti.com


    DBV0005A

    EXAMPLE STENCIL DESIGN

    SOT-23 - 1.45 mm max height

    SMALL OUTLINE TRANSISTOR



    1


    5X (0.6)


    5X (1.1)

    PKG


    5



    2

    2X(0.95)


    SYMM


    (1.9)



    (R0.05) TYP

    3 4


    (2.6)


    SOLDER PASTE EXAMPLE

    BASED ON 0.125 mm THICK STENCIL SCALE:15X



    4214839/E 09/2019

    NOTES: (continued)


  7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations.

  8. Board assembly site may have different recommendations for stencil design.

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