a

Dual Low Power Operational Amplifier,

Single or Dual Supply

OP221

FEATURES

Excellent TCVOS Match, 2 µV/°C Max Low Input Offset Voltage, 150 µV Max Low Supply Current, 550 µA Max Single Supply Operation, 5 V to 30 V

Low Input Offset Voltage Drift, 0.75 µV/°C

PIN CONNECTIONS


1

8-Lead SOIC (S-Suffix)

High Open-Loop Gain, 1500 V/mV Min High PSRR, 3 µV/V

Wide Common-Mode Voltage

Range, V– to within 1.5 V of V+

Pin Compatible with 1458, LM158, LM2904 Available in Die Form

+IN A

V–

+IN B

–IN B


2

3


4


NC = NO CONNECT

–IN A

5

6

7

8

OUT A V+ OUT B


GENERAL DESCRIPTION

The OP221 is a monolithic dual operational amplifier that can be used either in single or dual supply operation. The wide supply voltage range, wide input voltage range, and low supply current drain of the OP221 make it well-suited for operation from batteries or unregulated power supplies.


The excellent specifications of the individual amplifiers combined with the tight matching and temperature tracking between channels


provide high performance in instrumentation amplifier designs. The individual amplifiers feature very low input offset voltage, low offset voltage drift, low noise voltage, and low bias current. They are fully compensated and protected.


Matching between channels is provided on all critical parameters including input offset voltage, tracking of offset voltage vs. tem- perature, non-inverting bias currents, and common-mode rejection.



SIMPLIFIED SCHEMATIC



–IN Q1


Q3 Q4


Q2


Q11


Q12


Q26


Q28

V+


OUTPUT


+IN

Q9 Q10


Q7 Q4

Q27


Q29


Q6

Q5


NULL*


Q13


Q33


V–


*ACCESSIBLE IN CHIP FORM ONLY


REV. C

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.


One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 www.analog.com

Fax: 781/326-8703 © Analog Devices, Inc., 2002

OP221–SPECIFICATIONS (Electrical Characteristics at Vs = ±2.5 V to ±15 V, TA = 25°C, unless otherwise noted.)

OP221G

Parameter

Symbol

Conditions

Min

Typ

Max

Unit

Input Offset Voltage

VOS



250

500

V

Input Offset Current

Ios

VCM = 0

1.5 7

nA

Input Bias Current

IB

VCM = 0


70

120

nA

Input Voltage Range

IVR

V+ = 5 V, V– = 0 V1 VS = 15 V

0/3.5

–15/13.5

V

Common-Mode Rejection Ratio

CMRR

V+ = –5 V, V– = 0 V 0 V VCM 3.5 V VS = 15 V

–15 V VCM 13.5 V


75


80


85


90



dB

Power Supply Rejection Ratio

PSRR

VS = 2.5 V to 15 V

V– = 0 V, V+ = 5 V to 30 V


32

57

100

180

V/V

Large-Signal Voltage Gain

Avo

VS = 15 V, RL = 10 k VO = 10 V


800


V/mV

Output Voltage Swing

VO

V+ = 5 V, V– = 0 V RL = 10 k

VS = 15 V, RL = 10 k

0.8/4


13.5

V

Slew Rate

SR

RL = 10 k2

0.2

0.3


V/S

Bandwidth

BW


600

kHz

Supply Current (Both Amplifiers)

ISY

VS = 2.5 V, No Load VS = 15 V, No Load


550

850

650

900

A

OP221

SPECIFICATIONS (Electrical Characteristics at VS = ±2.5 V to ±15 V, –40°C TA +85°C, unless otherwise noted.)

OP221G

Parameter

Symbol

Conditions

Min

Typ

Max

Unit

Average Input Offset Voltage Drift1

TCVOS



2

3

V/C

Input Offset Voltage

VOS



400

700

V

Input Offset Current

IOS

VCM = 0


2

10

nA

Input Bias Current

IB

VCM = 0


80

140

nA

Input Voltage Range

IVR

V+ = 5 V, V– = 0 V2 VS = 15 V

0/3.2

–15/13.2

V

Common-Mode Rejection Ratio

CMRR

V+ = –5 V, V– = 0 V 0 V VCM 3.5 V VS = 15 V

–15 V VCM 13.5 V


70


75


80


85



dB

Power Supply Rejection Ratio

PSRR

VS = 2.5 V to 15 V

V– = 0 V, V+ = 5 V to 30 V


57

100

180

320

V/V

Large-Signal Voltage Gain

AVO

VS = 15 V, RL = 10 k VO = 10 V


600

V/mV

Output Voltage Swing

VO

V+ = 5 V, V– = 0 V RL = 10 k

VS = 15 V, RL = 10 k

0.9/3.7


13.2


V

Supply Current (Both Amplifiers)

ISY

VS = 2.5 V, No Load VS = 15 V, No Load


600

950

750

1000

A

NOTES

1Sample tested.

2Guaranteed by CMRR test limits.


Matching Characteristics at Vs = ±15 V, TA = 25°C, unless otherwise noted.

OP221G

Parameter

Symbol

Conditions

Min

Typ

Max

Unit

Input Offset Voltage Match


VOS



250


600


V

Average Noninverting Bias Current


IB+



120


nA

Noninverting Input Offset Current

IOS+


4

10

nA

Common-Mode Rejection Ratio Match1


CMRR


VCM = –15 V to 13.5 V


72


dB

Power Supply Rejection Ratio Match2

PSRR

VS = 2.5 V to 15 V


140

V/V

NOTES

1CMRR is 20 log10 VCM/CME, where VCM is the voltage applied to both noninverting inputs and CME is the difference in common-mode input-referred error.

2PSRR is: Input-Referred Differential Error

VS

OP221–SPECIFICATIONS

(Matching Characteristics at Vs = ±15 V, –40°C TA +85°C for OP221G, unless other- wise noted. G is sample tested.)



.

OP221G

Parameter

Symbol

Conditions

Min

Typ

Max

Unit

Input Offset Voltage Match


VOS




400


800


V

Average Noninverting Bias Current

IB+

VCM = 0

140

nA

Input Offset Voltage Tracking

ICVOS



3

5

VC

Noninverting Input Offset Current

IOS+

VCM = 0


6

12

nA

Common-Mode Rejection Ratio Match1


CMRR


VCM = –15 V to 13.2 V


72


80



dB

Power Supply Rejection Ratio Match2

PSRR



140

V/V

NOTES

1CMRR is 20 log10 VCM/CME, where VCM is the voltage applied to both noninverting inputs and CME is the difference in common-mode input-referred error.

2PSRR is: Input-Referred Differential Error

VS

OP221


ABSOLUTE MAXIMUM RATINGS (Note 1)

Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 V

Differential Input Voltage . . . . . . . . . . 30 V or Supply Voltage Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . Supply Voltage Output Short-Circuit Duration . . . . . . . . . . . . . . . . Indefinite Storage Temperature Range . . . . . . . . . . . . –65C to +150C Operating Temperature Range

OP221G . . . . . . . . . . . . . . . . . . . . . . . . . . . . –40C to +85C

Lead Temperature (Soldering 60 sec) . . . . . . . . . . . . . . 300C

Junction Temperature (TJ) . . . . . . . . . . . . . –65C to +150C


Package Type

6JA (Note 2)

6JC

Unit

8-Lead SOIC(S)

158

43

C/W

NOTES

1Absolute maximum ratings apply to both DICE and packaged parts, unless otherwise noted.

20JA is specified for device soldered to printed circuit board for SOIC package.


TA = +25°C VOS MAX (µV)


Plastic 8-Lead

Operating Temperature Range

Package Options

150

150

300

500

500

500


OP221GS


XIND


RN-8

ORDERING GUIDE


Figure 1. Dice Characteristics


CAUTION

WARNING!


ESD SENSITIVE DEVICE

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the OP221 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.

OP221–Typical Perfomance Characteristics


140


140




dc








10Hz












100Hz




1kHz












VS = ±15V












140


120


OPEN-LOOP GAIN – dB

100


80


60


40


20

120


OPEN-LOOP GAIN – dB

100


80


60


40


20

120


OPEN-LOOP GAIN – dB

100


80


60


40


20


TA = 25°C

RL = 15kfi




dc








10Hz












100Hz




1kHz












VS = ±15V












0

–50


–25 0 25 50 75 100 125

TEMPERATURE – °C


0

–50


0

–25 0 25 50 75 100 125 0

TEMPERATURE – °C


±5 ±10 ±15

SUPPLY VOLTAGE – V


TPC 1. Open-Loop Gain at 15 V vs. Temperature

TPC 2. Open-Loop Gain at 5 V vs. Temperature

TPC 3. Open-Loop Gain at vs. Supply Voltage



120

70 25


60 20


TA = 25°C

80


100

OPEN-LOOP GAIN – dB

100


80


60


VS = ±5V


50


CLOSED-LOOP GAIN – dB

40

VS = ±15V

30


15

VOLTAGE GAIN – dB

0m = 42°

10


5

VS = ±15V


PHASE SHIFT – Degrees

120


140


160

40 20

10

20

0

0

–10


0


–5


–10

GAIN PHASE


180


200


220

0.1

1 10 100 1k 10k 100k 1M 10M

1 10 100

1k 10k 100k 1M 10M

100k 1M 10M

FREQUENCY – Hz

FREQUENCY – Hz

FREQUENCY – Hz


TPC 4. Open-Loop Gain at 15 V vs. Frequency

TPC 5. Closed-Loop Gain vs. Frequency

TPC 6. Gain and Phase Shift vs. Frequency


PHASE MARGIN –

Degrees

55

50 PHASE MARGIN


VS = ±15V

120

120


TA = 25°C

45


40


SLEW RATE –

V/µsec

0.35


0.30


0.25

0.20


SLEW RATE


GAIN BANDWIDTH

850k


800k


750k


700k


650k

100


GAIN BANDWIDTH – Hz

PSRR – dB

80


60


40


20


0


TA = 25°C VS = ±15V


–PSRR

+PSRR

100


CMRR – Hz

80


60


40


20


0

VS = ±15V

–50

–25 0 25 50 75 100 125

TEMPERATURE – °C

10 100 1k 10k 100k

FREQUENCY – Hz

1 10 100 1k 10k 100k

FREQUENCY – Hz


TPC 7. Phase Margin, Gain Bandwidth, and Slew Rate vs. Temperature

TPC 8. PSRR vs. Frequency

TPC 9. CMRR vs. Frequency

OP221

30

PEAK-TO-PEAK AMPLITUTDE – V

28 TA = 25°C

VS = ±15V

24 RL = 10kfi


20


16


12


8


4

16

14 TA = 25°C VS = ±15V

MAXIMUM OUTPUT – V

12

POSITIVE

10


8


6


4


2


NEGATIVE


2.0


MAXIMUM OUTPUT – V

1.0


TA = 25°C

VS = ±2.5V NEGATIVE POSITIVE


0

1K 10k 100k 1M FREQUENCY – Hz


0

100


1k 10k

LOAD RESISTANCE – fi


100k


0

100


1k 10k

LOAD RESISTANCE – fi


100k

TPC 10. Maximum Output Swing vs. Frequency

TPC 11. Maximum Output Voltage vs. Load Resistance

TPC 12. Maximum Output Voltage vs. Load Resistance


100

80

70

VOLTAGE NOISE – nV/ Hz

60

50

40


30

10


CURRENT NOISE – pA Hz

1.0


20


10

1 10 100 1k FREQUENCY – Hz

0.1

1


10 100 1k FREQUENCY – Hz

TPC 13. Voltage Noise Density vs. Frequency

TPC 13. Current Noise Density vs. Frequency

OP221



Figure 2a. Noninverting Step Response


Figure 3a. Inverting Step Response



Figure 2b. Noninverting Step Response


Figure 3b. Inverting Step Response



INPUT


OUTPUT


10kfi


INPUT


10kfi


10kfi


OUTPUT


Figure 4. Noninverting Test Circuit Figure 5. Inverting Test Circuit

OP221


SPECIAL NOTES ON THE APPLICATION OF DUAL MATCHED OPERATIONAL AMPLIFIERS

Advantages of Dual Monolithic Operational Amplifiers

Dual matched operational amplifiers provide the engineer with a powerful tool for designing instrumentation amplifiers and many other differential-input circuits. These designs are based on the principle that careful matching between two operational amplifiers can minimize the effect of dc errors in the individual amplifiers.

Reference to the circuit shown in Figure 6, a differential-in, differential-out amplifier, shows how the reductions in error can be accomplished. Assuming the resistors used are ideally matched, the gain of each side will be identical. If the offset voltages of each amplifier are perfectly matched, then the net differential voltage at the amplifier’s output will be zero. Note that the output offset error of this amplifier is not a function of the offset voltage of the individual amplifiers, but only a function of the difference (degree of matching) between the amplifiers’ offset voltages. This error-cancellation principle holds for a considerable number of input referred error parameters—offset voltage, offset voltage

INSTRUMENTATION AMPLIFIER APPLICATIONS

Two-Op Amp Configuration

The two-op amp circuit (Figure 7) is recommended where the common-mode input voltage range is relatively limited; the common-mode and differential voltage both appear at V1. The

high open-loop gain of the OP221 is very important in achieving good CMRR in this configuration. Finite open-loop gain of A1 (Ao1) causes undesired feedthrough of the common-mode input. For Ad/Ao, << 1, the common-mode error (CME) at the out- put due to this effect is approximately (2 Ad/Ao1) x VCM. This circuit features independent adjustment of CMRR and differ- ential gain.

Three-Op Amp Configuration

The three-op amp circuit (Figure 8) has increased common- mode voltage range because the common-mode voltage is not amplified as it is in Figure 7. The CMR of this amplifier is directly proportional to the match of the CMR of the input op amps. CMRR can be raised even further by trimming the output stage resistors.

drift, inverting and noninverting bias currents, common mode R0

and power supply rejection ratios. Note also that the impedances of each input, both common-mode and differential-mode, are


GAIN ADJ

R0

high and tightly matched, an important feature not practical with single operation amplifier circuits.

R1 R2


1/2

OP221

AD = 2 1+ R1


R3


R1

SIDE +

+ ‘A’


VCM – 1/2VD


Vd

+ VCM + 1/2VD

A1 V1

R3

R4


1/2

OP221


A2


VO – ADVD


INPUT OUTPUT

V = R4

1 + 1

R2 + R3

+ R2 + R3

Vd + R4

R3 R2

VCM

OP221

O R3

2 R1 R4 R0

R3 R4 R1

R1

SIDE

R2 ‘R’


R4

IF R1 = R2 = R3 = R4, THEN VO = 2 1 + R0 VD


Figure 7. Two-Op Amp Circuit


R1

Figure 6. Differential-In, Differential-Out Amplifier

V = 2 1 + 2R1

O

V

R0 D


VCM – 1/2VD


R2 R2

V1

A1

1/2 V+

OP221

R0

R1

Vd

V+

OP221

A3 VO


– VCM + 1/2VD

R2

A2

R2

1/2 V2 V–

OP221

V–

Figure 8. Three-Op Amp Circuit

OP221


OUTLINE DIMENSIONS


8-Lead Standard Small Outline Package [SOIC]

Narrow Body (RN-8)

Dimensions shown in millimeters and (inches)



5.00 (0.1968)

4.80 (0.1890)


8

5

4.00 (0.1574)

3.80 (0.1497)

6.20 (0.2440)

4

1

5.80 (0.2284)


1.27 (0.0500) BSC


1.75 (0.0688)

0.50 (0.0196)

0.25 (0.0099) X 45°

0.25 (0.0098)

0.10 (0.0040)

1.35 (0.0532)


COPLANARITY 0.10


SEATING PLANE

0.51 (0.0201)

0.33 (0.0130)

8°

0.25 (0.0098) 0°

0.19 (0.0075)


1.27 (0.0500)

0.41 (0.0160)


COMPLIANT TO JEDEC STANDARDS MS-012AA CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN

C00324–0–10/02(C)

PRINTED IN U.S.A.

OP221

Revision History

Location Page

10/02—Data Sheet changed from REV. B to REV. C.

Deleted 8-Lead CERDIP Package (Q-8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Universal

Edits to SPECIFICATIONS 2–4

Edits to ABSOLUTE MAXIMUM RATINGS 5

Edits to ORDERING GUIDE 5

Updated OUTLINE DIMENSIONS 10

6/02—Data Sheet changed from REV. A to REV. B.

Edits to 8-Lead SOIC Package (R-8) 10

09/01—Data Sheet changed from REV. 0 to REV. A.

Edits to PIN CONNECTIONS 1

Global deletion of references to OP221B and OP221C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2, 3, 4

Edits to WAFER TEST LIMITS 4

Edits to ABSOLUTE MAXIMUM RATINGS 5

Edits to ORDERING GUIDE 5

Edits to PACKAGE TYPE 5

Mouser Electronics


Authorized Distributor


Click to View Pricing, Inventory, Delivery & Lifecycle Information:


Analog Devices Inc.:

OP221GSZ-REEL7 OP221GSZ OP221GSZ-REEL