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OPA810

SBOS799A – AUGUST 2019 – REVISED DECEMBER 2019

OPA810 140-MHz, Rail-to-Rail Input/Output, FET-Input Operational Amplifier

  1. Features

  2. Applications

  3. Description

    The OPA810 is a single-channel, field-effect transistor (FET)-input, voltage-feedback operational amplifier with bias current in the picoampere (pA) range. The OPA810 is unity-gain stable with a small- signal, unity-gain bandwidth of 140 MHz, and offers excellent DC precision and dynamic AC performance at a low quiescent current (IQ) of 3.7 mA per channel. The OPA810 is fabricated on Texas Instrument's proprietary, high-speed SiGe BiCMOS process and achieves significant performance improvements over comparable FET-input amplifiers at similar levels of quiescent power. With a gain-bandwidth product (GBWP) of 70 MHz, slew rate of 200 V/µs, and low- noise voltage of 6.3 nV/√Hz, the OPA810 is well suited for use in a wide range of high-fidelity data acquisition and signal processing applications.

    The OPA810 features rail-to-rail inputs and outputs and delivers 75 mA of linear output current, suitable for driving optoelectronics components and analog-to- digital converter (ADC) inputs or buffering digital-to- analog converter (DAC) outputs into heavy loads.

    The OPA810 is rated over the extended industrial temperature range of –40°C to +125°C. The OPA2810 is a dual-channel variant of this device, available in 8-pin SOIC, SOT23, and VSSOP packages.


    Device Information(1)

    PART NUMBER

    PACKAGE

    BODY SIZE (NOM)


    OPA810

    SOIC (8)

    4.90 mm × 3.91 mm

    SOT-23 (5)(2)

    2.90 mm × 1.60 mm

    SC70 (5)(2)

    2.00 mm × 1.25 mm

    1. For all available packages, see the orderable addendum at the end of the data sheet.

    2. Preview package.


      High-Z Input Data Acquisition Front-End


      CF

      12V

      RF


      VIN+

      R C


      OPA810

      +


      -12V


      12V


      RG

      12V


      VOCM

      THS456 1

      +

      RG

      -0.2V


      RS


      CCB


      CCB


      1.8V 1.8V


      AVDD DVDD

      ADS911 0

      18-bit 2 MSPS

      VREF


      VIN-

      R C

      OPA810

      +


      -12V


      12V


      RF R'

      R'

      5V

      CF

      5V


      REF505 0

      5.0 V

      Reference


      RFILT


      CFILT

      OPA378

      +

      OPA837

      +


      An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA.

      Table of Contents

      1. Features 1

      2. Applications 1

      3. Description 1

      4. Revision History 2

      5. Device Comparison Table 3

      6. Pin Configuration and Functions 3

      7. Specifications 4

        1. Absolute Maximum Ratings 4

        2. ESD Ratings 4

        3. Recommended Operating Conditions 4

        4. Thermal Information 4

        5. Electrical Characteristics: 10 V 5

        6. Electrical Characteristics: 24 V 7

        7. Electrical Characteristics: 5 V 9

        8. Typical Characteristics: VS = 10 V 11

        9. Typical Characteristics: VS = 24 V 14

        10. Typical Characteristics: VS = 5 V 17

        11. Typical Characteristics: ±2.375-V to ±12-V Split Supply 19

      8. Detailed Description 22

        1. Overview 22

        2. Functional Block Diagram 22

        3. Feature Description 23

        4. Device Functional Modes 24

      9. Application and Implementation 25

        1. Application Information 25

        2. Typical Applications 30

      10. Power Supply Recommendations 34

      11. Layout 34

        1. Layout Guidelines 34

        2. Layout Example 36

      12. Device and Documentation Support 37

        1. Documentation Support 37

        2. Receiving Notification of Documentation Updates 37 12.3 Community Resources 37

            1. Trademarks 37

            2. Electrostatic Discharge Caution 37

            3. Glossary 37

          1. Mechanical, Packaging, and Orderable Information 38


  4. Revision History

    NOTE: Page numbers for previous revisions may differ from page numbers in the current version.


    Changes from Original (August 2019) to Revision A Page


  5. Device Comparison Table



    DEVICE


    VS± (V)

    IQ / CHANNEL (mA)

    GBWP (MHz)

    SLEW RATE

    (V/μs)

    VOLTAGE NOISE

    (nV/√Hz)


    AMPLIFIER DESCRIPTION

    OPA2810

    ±12

    3.6

    70

    192

    6

    Unity-gain stable FET input

    OPA607

    ±2.5

    0.9

    50

    24

    3.8

    Gain of 6, stable, low-cost CMOS amplifier

    THS4631

    ±15

    13

    210

    900

    7

    Unity-gain stable FET input

    OPA859

    ±2.625

    20.5

    1800

    1150

    3.3

    Unity-gain stable FET input

    OPA818

    ±6.5

    27.7

    2700

    1400

    2.2

    Gain of 7, stable FET input


  6. Pin Configuration and Functions


    D Package 8-Pin SOIC

    Top View

    DBV and DCK Package (Preview) 5-Pin SOT-23 and SC70

    Top View










    NC


    1


    8


    NC

    VO

    1




    5

    VS+


    VIN-


    2


    7


    VS+


    VS-

    2






    VIN+

    3

    6

    VO

    VI N+

    3




    4

    VI N-

    VS-

    4

    5

    NC










    Not to scale


    Pin Functions

    PIN

    TYPE(1)


    DESCRIPTION

    NAME

    SOIC

    SOT-23, SC70

    NC

    1

    No internal connection

    VIN–

    2

    4

    I

    Inverting input pin

    VIN+

    3

    3

    I

    Noninverting input pin

    VS–

    4

    2

    P

    Negative power-supply pin

    NC

    5

    No internal connection

    VO

    6

    1

    O

    Output pin

    VS+

    7

    5

    P

    Positive power-supply pin

    NC

    8

    No internal connection

    (1) I = input, O = output, and P = power.

  7. Specifications

    1. Absolute Maximum Ratings

      over operating free-air temperature range (unless otherwise noted)(1)


      MIN MAX

      UNIT

      VS

      Supply voltage (total bipolar supplies)(2)


      ±14

      V

      VIN

      Input voltage


      VS– – 0.5 VS+ + 0.5

      V

      VIN,Diff

      Differential input voltage(3)


      ±7

      V

      II

      Continuous input current


      ±10

      mA

      IO

      Continuous output current(4)

      TA = –40to +85

      ±40

      mA

      TA = 125

      ±15

      mA

      PD

      Continuous power dissipation


      See Thermal Information


      TJ

      Junction temperature


      150

      °C

      Tstg

      Storage temperature


      –65 125

      °C

      1. Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Theseare stress ratings only, which do not imply functional operation of the device at these or anyother conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

      2. VS is the total supply voltage given by VS = VS+ – VS– .

      3. Equal to the lower of ±7 V or total supply voltage.

      4. Long-term continuous output current for electromigration limits.


    2. ESD Ratings


      VALUE

      UNIT

      V(ESD)


      Electrostatic discharge

      Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)

      ±2500


      V

      Charged-device model (CDM), per JEDEC specification JESD22-C101(2)

      ±1500

      1. JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

      2. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.


    3. Recommended Operating Conditions

      over operating free-air temperature range (unless otherwise noted)


      MIN NOM MAX

      UNIT

      VS

      Total supply voltage

      4.75 27

      V

      TA

      Ambient temperature

      –40 25 125

      °C


    4. Thermal Information


      THERMAL METRIC(1)

      OPA810


      UNIT

      D (SOIC)

      DBV (SOT-23)

      DCK (SC70)

      8 PINS

      5 PINS

      5 PINS

      RθJA

      Junction-to-ambient thermal resistance

      134.8

      174.3

      190.8

      °C/W

      RθJC(top)

      Junction-to-case (top) thermal resistance

      75.2

      94.7

      140.1

      °C/W

      RθJB

      Junction-to-board thermal resistance

      78.2

      45.4

      69.0

      °C/W

      ψJT

      Junction-to-top characterization parameter

      25.2

      21.6

      45.9

      °C/W

      ψJB

      Junction-to-board characterization parameter

      77.4

      45.0

      68.8

      °C/W

      (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.

    5. Electrical Characteristics: 10 V

      Test conditions unless otherwise noted: TA = 25°C, VS+ = 5 V, VS– = –5 V, common-mode voltage (VCM) = mid-supply, RL = 1 kΩ connected to mid-supply(1).

      PARAMETER

      TEST CONDITIONS

      MIN TYP MAX

      UNIT

      TEST LEVEL(2)

      AC PERFORMANCE


      SSBW


      Small-signal bandwidth

      G = 1, VO = 20 mVPP, RF = 0 Ω

      135


      MHz

      C

      G = 1, VO = 20 mVPP, RF = 0 Ω, CL = 10 pF

      140

      C

      G = –1, VO = 20 mVPP

      68

      C

      LSBW

      Large-signal bandwidth

      G = 2, VO = 2 VPP

      41

      MHz

      C

      GBWP

      Gain-bandwidth product


      70

      MHz

      C


      Bandwdith for 0.1-dB flatness

      G = 2, VO = 20 mVPP

      16

      MHz

      C

      SR

      Slew rate (20%-80%)(3)

      G = 2, VO = –2-V to 2-V step

      200

      V/µs

      C


      Rise time

      VO = 200-mV step

      4

      ns

      C


      Fall time

      VO = 200-mV step

      4

      ns

      C



      Settling time to 0.1%

      G = 2, VO = 2-V step

      47


      ns

      C

      G = 2, VO = 8-V step

      65

      C



      Settling time to 0.001%

      G = 2, VO = 2-V step

      330


      ns

      C

      G = 2, VO = 8-V step

      230

      C


      Input overdrive recovery

      G = 1, RF = 0 Ω, (VS– – 0.5 V) to (VS+

      + 0.5 V) input

      55

      ns

      C


      Output overdrive recovery

      G = –1, (VS– – 0.5 V) to (VS+ + 0.5 V)

      input

      55

      ns

      C


      HD2

      Second-order harmonic distortion

      f = 100 kHz, RL = 1 kΩ, VO = 2 VPP

      –120


      dBc

      C

      f = 1 MHz, RL = 1 kΩ, VO = 2 VPP

      –101

      C


      HD3

      Third-order harmonic distortion

      f = 100 kHz, RL = 1 kΩ, VO = 2 VPP

      –137


      dBc

      C

      f = 1 MHz, RL = 1 kΩ, VO = 2 VPP

      –101

      C

      en

      Input-referred voltage noise

      f = 500 kHz, flatband

      6.3

      nV/√Hz

      C

      in

      Input-referred current noise

      f = 10 kHz

      5

      fA/√Hz

      C

      zO

      Closed-loop output impedance

      f = 100 kHz

      0.007

      Ω

      C

      DC PERFORMANCE

      AOL

      Open-loop voltage gain

      f = DC, VO = ±2.5 V

      108 120

      dB

      A

      VOS

      Input offset voltage


      100 500

      µV

      A


      Input offset voltage drift

      TA = –40°C to +125°C

      2.5 10

      µV/°C

      B


      Input bias current


      2 20

      pA

      A


      Input offset current


      1 20

      pA

      A


      CMRR

      Common-mode rejection ratio

      f = DC, VCM = –3 V to 1 V

      80 100


      dB

      A

      TA = –40°C to +125°C

      80

      B

      INPUT


      Allowable input differential voltage

      See Figure 54

      ±7

      V

      C


      Common-mode input impedance

      In closed-loop configuration

      12 || 2

      GΩ||pF

      C


      Differential input capacitance

      In open-loop configuration

      0.5

      pF

      C


      Most positive input voltage

      ΔVOS < 5 mV(4)

      VS+ + 0.2 VS+ + 0.3

      V

      A


      1. For AC specifications, G = 2 V/V, RF = 1 kΩ and CL = 4.7 pF (unless otherwise noted).

      2. Test levels (all values set by characterization and simulation): (A) 100% tested at 25°C, overtemperature limits by characterization and simulation; (B) Not tested in production, limits set by characterization and simulation; (C) Typical value only for information.

      3. Lower of the measured positive and negative slew rate.

      4. Change in input offset from its value when input is biased to midsupply.

        Electrical Characteristics: 10 V (continued)

        Test conditions unless otherwise noted: TA = 25°C, VS+ = 5 V, VS– = –5 V, common-mode voltage (VCM) = mid-supply, RL = 1 kΩ connected to mid-supply(1).

        PARAMETER

        TEST CONDITIONS

        MIN TYP MAX

        UNIT

        TEST LEVEL(2)


        Most negative input voltage

        ΔVOS < 5 mV(4)

        VS– – 0.2 VS– – 0.3

        V

        A


        Most positive input voltage for main-JFET stage

        See Figure 17

        VS+ – 2.9 VS+ – 2.5

        V

        C

        OUTPUT

        VOCRH

        Output voltage range high

        RL = 667 Ω

        VS+ – 0.18 VS+ – 0.11

        V

        A

        VOCRH

        Output voltage range high

        TA = –40°C to +125°C, RL = 667 Ω

        VS+ – 0.2

        V

        B

        VOCRL

        Output voltage range low

        RL = 667 Ω

        VS– + 0.08 VS– + 0.15

        V

        A

        VOCRL

        Output voltage range low

        TA = –40°C to +125°C, RL = 667 Ω

        VS– + 0.2

        V

        B

        IO(max)

        Linear output drive (sourcing and sinking)

        VO = 2.65 V, RL = 51 Ω, ΔVOS < 1 mV

        52 75

        mA

        A

        ISC

        Output short-circuit current


        100

        mA

        B

        CL

        Capacitive load drive

        < 3-dB peaking, RS = 0 Ω

        10

        pF

        C

        POWER SUPPLY

        IQ

        Quiescent current per channel


        3.7 4.6

        mA

        A


        PSRR


        Power-supply rejection ratio

        ΔVS = ±2 V(5)

        79 100


        dB

        A

        TA = –40°C to +125°C

        79

        B

        AUXILIARY CMOS INPUT STAGE


        Gain-bandwidth product


        27

        MHz

        C


        Input-referred voltage noise

        f = 1 MHz

        20

        nV/√Hz

        C


        Input offset voltage

        VCM = VS+ – 1.5 V, no load

        1.6

        mV

        A


        Input bias current

        VCM = VS+ – 1.5 V

        2 20

        pA

        A

      5. Change in supply voltage from the default test condition with only one of the positive or negative supplies changing corresponding to

      +PSRR and –PSRR.

    6. Electrical Characteristics: 24 V

      Test conditions unless otherwise noted: TA = 25°C, VS+ = 12 V, VS– = –12 V, common-mode voltage (VCM) = mid-supply, RL = 1 kΩ connected to mid-supply(1).

      PARAMETER

      TEST CONDITIONS

      MIN TYP MAX

      UNIT

      Test Level (2)

      AC PERFORMANCE


      SSBW


      Small-signal bandwidth

      G = 1, Vo = 20 mVPP, RF = 0 Ω

      135


      MHz

      C

      G = 1, Vo = 20 mVPP, RF = 0 Ω, CL= 10 pF

      140

      C

      G = –1, Vo = 20 mVPP

      68

      C


      LSBW


      Large-signal bandwidth

      G = 2 Vo = 2 VPP

      44


      MHz

      C

      G = 2 Vo = 10 VPP

      14

      C

      GBWP

      Gain-bandwidth product


      70

      MHz

      C


      Bandwdith for 0.1-dB flatness

      G = 2, Vo = 20 mVPP

      16

      MHz

      C


      SR


      Slew rate (20%-80%)(3)

      G = 2, Vo = –2-V to 2-V step

      237


      V/µs

      C

      G = –1, Vo = –2-V to 2-V step

      222

      C

      G = 2, Vo = –4.5-V to 3.5-V step

      254

      C


      Rise time

      Vo = 200-mV step

      4

      ns

      C


      Fall time

      Vo = 200-mV step

      4

      ns

      C



      Settling time to 0.1%

      G = 2, Vo = 2-V step

      47


      ns

      C

      G = 2, Vo = 10-V step

      70

      C



      Settling time to 0.001%

      G = 2, Vo = 2-V step

      320


      ns

      C

      G = 2, Vo = 10-V step

      200

      C


      Input overdrive recovery

      G = 1, RF = 0 Ω, (VS– – 0.5 V) to (VS+

      + 0.5 V) input

      35

      ns

      C


      Output overdrive recovery

      G = –1, (VS– – 0.5 V) to (VS+ + 0.5 V)

      input

      45

      ns

      C


      HD2


      Second-order harmonic distortion

      f = 100 kHz, RL = 1 kΩ, Vo = 2 VPP

      –118


      dBc

      C

      f = 100 kHz, RL =1 kΩ, Vo = 10 VPP

      –108

      C

      f = 1 MHz, RL = 1 kΩ, Vo = 2 VPP

      –112

      C

      f = 1 MHz, RL=1 kΩ, Vo = 10 VPP

      –91

      C


      HD3


      Third-order harmonic distortion

      f = 100 kHz, RL = 1 kΩ, Vo = 2 VPP

      –136


      dBc

      C

      f = 100 kHz, RL =1 kΩ, Vo = 10 VPP

      –130

      C

      f = 1 MHz, RL = 1 kΩ, Vo = 2 VPP

      –104

      C

      f = 1 MHz, RL =1 kΩ, Vo = 10 VPP

      –91

      C

      en

      Input-referred voltage noise

      f = 500 kHz, flatband

      6.3

      nV/√Hz

      C

      in

      Input-referred current noise

      f = 10 kHz

      5

      fA/√Hz

      C

      zO

      Closed-loop output impedance

      f = 100 kHz

      0.007

      Ω

      C

      DC PERFORMANCE

      AOL

      Open-loop voltage gain

      f = DC, Vo = ±8 V

      108 120

      dB

      A

      VOS

      Input offset voltage


      100 500

      µV

      A


      Input offset voltage drift

      TA = –40°C to +125°C

      2.5 10

      µV/°C

      B


      Input bias current


      2 20

      pA

      A


      Input offset current


      1 20

      pA

      A


      CMRR

      Common-mode rejection ratio

      f = DC, VCM = ±5 V

      90 105


      dB

      A

      TA = –40°C to +125°C

      90

      B


      1. For AC specifications, G = 2 V/V, RF = 1 kΩ and CL = 4.7 pF (unless otherwise noted).

      2. Test levels (all values set by characterization and simulation): (A) 100% tested at 25°C, overtemperature limits by characterization and simulation; (B) Not tested in production, limits set by characterization and simulation; (C) Typical value only for information.

      3. Lower of the measured positive and negative slew rate.

        Electrical Characteristics: 24 V (continued)

        Test conditions unless otherwise noted: TA = 25°C, VS+ = 12 V, VS– = –12 V, common-mode voltage (VCM) = mid-supply, RL = 1 kΩ connected to mid-supply(1).

        PARAMETER

        TEST CONDITIONS

        MIN TYP MAX

        UNIT

        Test Level (2)

        INPUT


        Allowable input differential voltage

        see Figure 54

        ±7

        V

        C


        Common-mode input impedance

        In closed-loop configuration

        12 || 2.5

        GΩ||pF

        C


        Differential input capacitance

        In open-loop configuration

        0.5

        pF

        C


        Most positive input voltage

        ΔVOS < 5 mV(4)

        VS+ + 0.2 VS+ + 0.3

        V

        A


        Most negative input voltage

        ΔVOS < 5 mV(4)

        VS– – 0.2 VS– – 0.3

        V

        A


        Most positive input voltage for main-JFET stage

        See Figure 33

        VS+ – 2.9 VS+ – 2.5

        V

        C

        OUTPUT

        VOCRH


        Output voltage range high

        RL = 667 Ω

        VS+ – 0.33 VS+ – 0.22


        V

        A

        TA = –40°C to +125°C, RL = 667 Ω

        VS+ – 0.36

        B


        VOCRL


        Output voltage range low

        RL = 667 Ω

        VS– + 0.15 VS– + 0.23


        V

        A

        TA = –40°C to +125°C, RL = 667 Ω

        VS– + 0.33

        B

        IO(max)

        Linear output drive (sourcing and sinking)

        Vo = 7.25 V, RL = 151 Ω, ΔVOS < 1 mV

        48 64

        mA

        A

        ISC

        Output short-circuit current


        108

        mA

        B

        CL

        Capacitive load drive

        < 3-dB peaking, RS = 0 Ω

        10

        pF

        C

        POWER SUPPLY

        IQ

        Quiescent current per channel


        3.8 4.7

        mA

        A


        PSRR


        Power supply rejection ratio

        ΔVS = ±2 V(5)

        90 105


        dB

        A

        TA = –40°C to +125°C

        90

        B

        AUXILIARY CMOS INPUT STAGE


        Gain-bandwidth product


        27

        MHz

        C


        Input-referred voltage noise

        f = 1 MHz

        20

        nV/√Hz

        C


        Input offset voltage

        VCM = VS+ – 1.5 V, no load

        1.6

        mV

        A


        Input bias current

        VCM = VS+ – 1.5 V

        2 24

        pA

        A

      4. Change in input offset from its value when input is biased to midsupply.

      5. Change in supply voltage from the default test condition with only one of the positive or negative supplies changing corresponding to

      +PSRR and -PSRR.

    7. Electrical Characteristics: 5 V

      Test conditions unless otherwise noted: TA = 25°C, VS+ = 5 V, VS– = 0 V, common-mode voltage (VCM) = 1.25 V, RL = 1 kΩ connected to 1.25 V(1).

      PARAMETER

      TEST CONDITIONS

      MIN TYP MAX

      UNIT

      Test Level (2)

      AC PERFORMANCE


      SSBW


      Small-signal bandwidth

      G = 1, Vo = 20 mVPP, RF = 0 Ω

      133


      MHz

      C

      G = 1, Vo = 20 mVPP, RF= 0 Ω, CL= 10 pF

      135

      C

      G = –1, Vo = 20 mVPP

      65

      C

      LSBW

      Large-signal bandwidth

      G = 2 Vo = 2 VPP

      36

      MHz

      C

      GBWP

      Gain-bandwidth product


      70

      MHz

      C


      Bandwdith for 0.1-dB flatness

      G = 2, Vo = 20 mVPP

      16

      MHz

      C


      SR


      Slew rate (20%-80%)(3)

      G = 2, Vo = –1-V to 1-V step

      134


      V/µs

      C

      G = 2, Vo = –2-V to 2-V step, VS = ±2.5 V

      78

      C


      Rise time

      Vo = 200-mV step

      4

      ns

      C


      Fall time

      Vo = 200-mV step

      4

      ns

      C


      Settling time to 0.1%

      G = 2, Vo = –2-V to 0-V step, VS = ±2.5 V

      100

      ns

      C


      Settling time to 0.001%

      G = 2, Vo = –2-V to 0-V step, VS = ±2.5 V

      565

      ns

      C


      Input overdrive recovery

      G = 1, (VS– – 0.5 V) to (VS+ + 0.5 V)

      input, VS = ±2.5 V

      76

      ns

      C


      Output overdrive recovery

      G = –1, (VS– – 0.5 V) to (VS+ + 0.5 V)

      input, VS = ±2.5 V

      93

      ns

      C


      HD2

      Second-order harmonic distortion

      f = 100 kHz, RL = 1 kΩ, Vo = 2 VPP

      –102


      dBc

      C

      f = 1 MHz, RL = 1 kΩ, Vo = 2 VPP

      –81

      C


      HD3

      Third-order harmonic distortion

      f = 100 kHz, RL = 1 kΩ, Vo = 2 VPP

      –114


      dBc

      C

      f = 1 MHz, RL = 1 kΩ, Vo = 2 VPP

      –92

      C

      en

      Input-referred voltage noise

      f = 500 kHz, flatband

      6.3

      nV/√Hz

      C

      in

      Input-referred current noise

      f = 10 kHz

      5

      fA/√Hz

      C

      zO

      Closed-loop output impedance

      f = 100 kHz

      0.007

      Ω

      C

      DC PERFORMANCE

      AOL

      Open-loop voltage gain

      f = DC, Vo = 1.25 V to 3.25 V

      104 118

      dB

      A

      VOS

      Input offset voltage


      100 550

      µV

      A


      Input offset voltage drift

      TA = –40°C to +125°C

      2.5 10

      µV/°C

      B


      Input bias current


      2 20

      pA

      A


      Input offset current


      1 20

      pA

      A


      CMRR

      Common-mode rejection ratio

      f = DC, VCM = 0.75 V to 1.75 V

      73 92


      dB

      A

      TA = –40°C to +125°C

      73

      B

      INPUT


      Allowable input differential voltage

      See Figure 54

      ±5

      V

      C


      Common-mode input impedance

      In closed-loop configuration

      12 || 2.5

      GΩ||pF

      C


      Differential input capacitance

      In open-loop configuration

      0.5

      pF

      C


      1. For AC specifications, VS+ = 3.5 V, VS– = –1.5 V, G = 2 V/V, RF = 1 kΩ, CL = 4.7 pF, VCM = 0 V (unless otherwise noted).

      2. Test levels (all values set by characterization and simulation): (A) 100% tested at 25°C, overtemperature limits by characterization and simulation; (B) Not tested in production, limits set by characterization and simulation; (C) Typical value only for information.

      3. Lower of the measured positive and negative slew rate.

        Electrical Characteristics: 5 V (continued)

        Test conditions unless otherwise noted: TA = 25°C, VS+ = 5 V, VS– = 0 V, common-mode voltage (VCM) = 1.25 V, RL = 1 kΩ connected to 1.25 V(1).

        PARAMETER

        TEST CONDITIONS

        MIN TYP MAX

        UNIT

        Test Level (2)


        Most positive input voltage

        ΔVOS < 5 mV(4)

        VS+ + 0.2 VS+ + 0.3

        V

        A


        Most negative input voltage

        ΔVOS < 5 mV(4)

        VS- – 0.2 VS- – 0.3

        V

        A


        Most positive input voltage for main-JFET stage

        See Figure 41

        VS+ – 2.9 VS+ – 2.5

        V

        C

        OUTPUT

        VOCRH


        Output voltage range high

        RL = 667 Ω

        VS+ – 0.12 VS+ – 0.09


        V

        A

        TA = –40°C to +125°C, RLOAD = 667 Ω

        VS+ – 0.15

        B


        VOCRL


        Output voltage range low

        RL = 667 Ω

        VS–+ 0.06 VS– + 0.11


        V

        A

        TA = –40°C to +125°C, RL = 667 Ω

        VS– + 0.15

        B

        IO(max)

        Linear output drive (sourcing and sinking)

        VO = 1.4 V, RL = 27.5 Ω, ΔVOS < 1 mV, VS+ = 3 V and VS– = –2 V

        50 64

        mA

        A

        ISC

        Output short-circuit current


        96

        mA

        B

        CL

        Capacitive load drive

        < 3-dB peaking, RS = 0 Ω

        10

        pF

        C

        POWER SUPPLY

        IQ

        Quiescent current per channel


        3.15 3.7 4.5

        mA

        A


        PSRR


        Power-supply rejection ratio

        ΔVS = ±0.5 V(5)

        78 100


        dB

        A

        TA = –40°C to +125°C

        78

        B

        AUXILIARY CMOS INPUT STAGE


        Gain-bandwidth product


        27

        MHz

        C


        Input-referred voltage noise

        f = 1 MHz

        20

        nV/√Hz

        C


        Input offset voltage

        VCM = VS+ – 1.5 V, no load

        1.6

        mV

        A


        Input bias current

        VCM = VS+ – 1.5 V

        2 20

        pA

        A

      4. Change in input offset from its value when input is biased to 0 V.

      5. Change in supply voltage from the default test condition with only one of the positive or negative supplies changing corresponding to

        +PSRR and -PSRR.

    8. Typical Characteristics: VS = 10 V

      at VS+ = 5 V, VS– = –5 V, RL = 1 kΩ, input and output are biased to midsupply, and TA ≈ 25°C. For AC specifications, VO = 2 VPP, G = 2 V/V, RF = 1 kΩ, and CL = 4.7 pF (unless otherwise noted)


      3


      0


      Normalized Gain (dB)

      -3


      -6


      -9


      -12


      -15


      -18

      3


      Normalized Gain (dB)




















      RL = 500

      RL = 1 k














      0


      -3


      -6


      -9


      -12


      Gain = 1 V/V

      Gain = 1 V/V Gain = 2 V/V

      Gain = 5 V/V Gain = 10 V/V

      -21

      100k 1M 10M 100M

      Frequency (Hz)

      See Figure 62 and Figure 63, VO = 20 mVPP


      D041


      -15

      100k 1M 10M 100M

      Frequency (Hz)

      See Figure 62, VO = 20 mVPP, gain = 1 V/V, RF = 0 Ω


      D042


      6


      3


      Normalized Gain (dB)

      0


      -3


      -6


      -9


      -12


      -15


      -18


      Figure 1. Small-Signal Frequency Response vs Gain

      Figure 2. Small-Signal Frequency Response vs Output Load

      6


      3


      Normalized Gain (dB)

      0


      -3


      -6


      -9


      RS = 0 , CL = 4.7 pF RS = 0 , CL = 10 pF RS = 0 , CL = 22 pF RS = 56 , CL = 47 pF

      -12


      -15


      -18





















      RS = 0 , CL = 4.7 pF RS = 0 , CL = 10 pF RS = 56 , CL = 22 pF RS = 40 , CL = 33 pF RS = 47 , CL = 47 pF































      -21

      100k 1M 10M 100M

      Frequency (Hz)


      D044


      -21

      100k 1M 10M 100M

      Frequency (Hz)


      D045

      See Figure 62 and Figure 60,

      VO = 20 mVPP, gain = 1 V/V, RF = 0 Ω

      Figure 3. Small-Signal Frequency Response vs CL

      3

      See Figure 62and Figure 60, VO = 20 mVPP, gain = 2 V/V


      Figure 4. Small-Signal Frequency Response vs CL




















      VO = 200 mVPP

      VO = 1 VPP

      VO = 2 VPP

      VO = 4 VPP


























      3


      0


      Normalized Gain (dB)

      -3


      -6


      -9


      -12


      VO = 200 mVPP VO = 1 VPP

      VO = 2 VPP

      VO = 4 VPP

      -15


      -18


      -21

      100k 1M 10M 100M

      Frequency (Hz)

      See Figure 62, gain = 1 V/V, RF = 0 Ω


      D046


      0


      Normalized Gain (dB)

      -3


      -6


      -9


      -12


      -15


      -18


      -21

      100k 1M 10M 100M

      Frequency (Hz)

      See Figure 62, gain = 2 V/V


      D047

      Figure 5. Large-Signal Frequency Response vs Output Voltage


      Figure 6. Large-Signal Frequency Response vs Output Voltage

      Typical Characteristics: VS = 10 V (continued)

      at VS+ = 5 V, VS– = –5 V, RL = 1 kΩ, input and output are biased to midsupply, and TA ≈ 25°C. For AC specifications, VO = 2 VPP, G = 2 V/V, RF = 1 kΩ, and CL = 4.7 pF (unless otherwise noted)

      Gain = 1 V/V

      Gain = 1 V/V Gain = 2 V/V Gain = 5 V/V Gain = 10 V/V

      1

      0.8

      Normalized Gain (dB)

      0.6

      0.4

      0.2

      0

      -0.2

      -0.4

      -0.6

      -0.8

      -1

      100k 1M 10M 100M

      Frequency (Hz)

      See Figure 62 and Figure 63, VO = 20 mVPP


      D05

      -60

      HD2, RL = 1 k

      HD3, RL = 1 k HD2, RL = 500 HD3, RL = 500

      -70

      Harmonic Distortion (dBc)

      -80

      -90

      -100

      -110

      -120

      -130

      -140

      -150

      -160

      1k 10k 100k 1M

      Frequency (Hz)

      See Figure 62, gain = 2 V/V


      D048


      -60

      -70

      Harmonic Distortion (dBc)

      -80

      -90

      -100

      -110

      -120

      -130

      -140

      -150

      -160


      Figure 7. Small-Signal Response Flatness vs Gain


      HD2, RL = 1 k

      HD3, RL = 1 k HD2, RL = 500 HD3, RL = 500


      -60

      -70

      Harmonic Distortion (dBc)

      -80

      -90

      -100

      -110

      -120

      -130

      -140

      -150

      -160

      Figure 8. Harmonic Distortion vs Frequency


      HD2, Gain = 1

      HD3, Gain = 1 HD2, Gain = 2 HD3, Gain = 2 HD2, Gain = -1 HD3, Gain = -1

      1k 10k 100k 1M

      Frequency (Hz)

      See Figure 63, gain = –1 V/V


      Figure 9. Harmonic Distortion vs Frequency





















      0.15


      0.1


      D049

      1k 10k 100k 1M

      Frequency (Hz)

      See Figure 62 and Figure 63, RF = 0 Ω

      Figure 10. Harmonic Distortion vs Gain

      Overshoot, VO = 2 VPP

      Undershoot, VO = 2 VPP Overshoot, VO = 200 mVPP

      Undershoot, VO = 200 mVPP









































































      45


      40


      Overshoot/Undershoot (%)

      35


      D050


      Output Voltage (V)

      30

      0.05

      25


      0


      -0.05


      -0.1


      Time (100 ns/div)


      See Figure 62, gain = 1 V/V, RF = 0 Ω, CL = 10 pF

      Figure 11. Small-Signal Transient Response


      D052


      20


      15


      10


      5


      0

      5 10 15 20 25 30 35 40 45 50

      Load Capacitance (pF) D053

      See Figure 62, gain = 1 V/V, RF = 0 Ω

      Figure 12. Overshoot and Undershoot vs CL

      Typical Characteristics: VS = 10 V (continued)

      at VS+ = 5 V, VS– = –5 V, RL = 1 kΩ, input and output are biased to midsupply, and TA ≈ 25°C. For AC specifications, VO = 2 VPP, G = 2 V/V, RF = 1 kΩ, and CL = 4.7 pF (unless otherwise noted)






























      VIN VOUT

      6 6


      Input and Output Voltage (V)

      Input and Output Voltage (V)

      4 4


      2 2


      0 0


      -2 -2


      VIN x -1 Gain VO

      -4 -4


      -6

      0 200 400 600 800 1000 1200 1400 1600

      -6

      0 200 400 600 800 1000 1200 1400

      Time (nsec)

      See Figure 62, gain = 1 V/V, RF = 0 Ω

      Figure 13. Input Overdrive Recovery



























































































      Sourcing

      Sinking





















































































































      6


      D054


      120

      Time (nsec)

      See Figure 63, gain = –1 V/V


      Figure 14. Output Overdrive Recovery


      D055


      Output Short-Circuit Current (mA)





































      Sourcing

      Sinking













































      90

      4

      60


      Output Voltage (V)

      2 30


      0

      0

      -30


      -2 -60


      -90

      -4

      -120


      -6

      0 10 20 30 40 50 60 70 80 90


      -150

      -40 -20 0 20 40 60 80 100 120 140

      Output Current (mA)


      D056

      Ambient Temperature (C)

      Output saturated and then short-circuited


      D057


      Figure 15. Output Voltage vs Load Current


















































































































































      1200


      Figure 16. Output Short-Circuit Current vs Ambient Temperature


      Input Offset Voltage (V)

      800


      400


      0


      -400


      -800


      -1200

      -6 -4 -2 0 2 4 6

      Input Common-Mode Voltage (V)

      Measured for 12 units


      D058


      Figure 17. Input Offset Voltage vs Input Common-Mode Voltage

    9. Typical Characteristics: VS = 24 V

      at VS+ = 12 V, VS– = –12 V, RL = 1 kΩ, input and output are biased to midsupply, and TA ≈ 25°C. For AC specifications, VO = 2 VPP, G = 2 V/V, RF = 1 kΩ, and CL = 4.7 pF (unless otherwise noted)


      3 3


      0 0


      Normalized Gain (dB)

      Normalized Gain (dB)

      -3 -3


      -6 -6


      -9 -9


      -12 -12


      -15


      -15


      VCM = 0 V

      -18

      -18 VCM = 9 V

      VCM = 11 V

      Gain = 1 V/V Gain = 1 V/V

      Gain = 2 V/V Gain = 5 V/V

      -21

      100k 1M 10M 100M

      Frequency (Hz)


      D071

      -21

      100k 1M 10M 100M

      Frequency (Hz)


      D072

      See Figure 62 and Figure 63, VO = 20 mVPP

      Figure 18. Noninverting Small-Signal Frequency Response vs Gain

      3

      See Figure 62, VO = 20 mVPP, gain = 1 V/V, CL = 4.7 pF, RF = 0 Ω

      Figure 19. Small-Signal Frequency Response vs Output Common-Mode Voltage

      3


      0 0


      Normalized Gain (dB)

      Normalized Gain (dB)

      -3 -3


      -6 -6


      -9 -9


      VO = 200 mVPP

      VO = 1 VPP

      VO = 2 VPP

      VO = 4 VPP

      VO = 10 VPP

      -12 -12


      -15


      -18


      -15


      -18


      VO = 200 mVPP VO = 1 VPP

      VO = 2 VPP

      VO = 4 VPP

      -21

      100k 1M 10M 100M

      Frequency (Hz)

      See Figure 62, gain = 1 V/V, RF = 0 Ω


      D074


      -21

      100k 1M 10M 100M

      Frequency (Hz)

      See Figure 62, gain = 2 V/V


      D075


      Figure 20. Large-Signal Frequency Response vs Output Voltage

      HD2, VO = 2 VPP

      HD3, VO = 2 VPP HD2, VO = 10 VPP HD3, VO = 10 VPP

      HD2, VO = 20 VPP HD3, VO = 20 VPP

      -20


      Harmonic Distortion (dBc)

      -40


      -60


      -80


      -100


      -120


      -140


      -40


      Harmonic Distortion (dBc)

      -60


      -80


      -100


      -120


      -140

      Figure 21. Large-Signal Frequency Response vs Vo


      HD2, VO = 2 VPP

      HD3, VO = 2 VPP

      HD2, VO = 10 VPP HD3, VO = 10 VPP

      HD2, VO = 20 VPP


      -160

      1k 10k 100k 1M

      Frequency (Hz)

      See Figure 62, gain = 2 V/V


      D076

      -160

      HD3, VO = 20 VPP

      1k 10k 100k 1M

      Frequency (Hz)

      See Figure 63, gain = –1 V/V


      D077

      Figure 22. Harmonic Distortion vs Frequency vs Vo Figure 23. Harmonic Distortion vs Frequency vs Vo

      Typical Characteristics: VS = 24 V (continued)

      at VS+ = 12 V, VS– = –12 V, RL = 1 kΩ, input and output are biased to midsupply, and TA ≈ 25°C. For AC specifications, VO = 2 VPP, G = 2 V/V, RF = 1 kΩ, and CL = 4.7 pF (unless otherwise noted)






























      0.15 6


      4

      0.1


      Output Voltage (V)

      Output Voltage (V)

      2

      0.05

      0

      0

      -2


      -0.05 -4


      -0.1


      Time (100 ns/div)

      -6


      D078


      Time (100 ns/div)


      D079

      See Figure 62, gain = 1 V/V, RF = 0 Ω, CL = 10 pF

      Figure 24. Small-Signal Transient Response





      VO = 2 VPP VO = 10 VPP

      VO = 20 VPP






















































      12


      8


      Output Voltage (V)

      4


      0


      -4


      -8

      See Figure 62, gain = 1 V/V, RF = 0 Ω

      Figure 25. Large-Signal Transient Response








      VO = 4 VPP VO = 10 VPP
















































































































      6


      4


      Output Voltage (V)

      2


      0


      -2


      -4


      -12

























      Overshoot, VO = 2 VPP Undershoot, VO = 2 VPP Overshoot, VO = 200 mVPP Undershoot, VO = 200 mVPP





























      25


      Overshoot/Undershoot (%)

      20


      15


      10


      5


      0


      Time (100 ns/div)


      See Figure 62, gain = 2 V/V


      Figure 26. Large-Signal Transient Response


      D080


      -6


      15

      12

      Input and Output Voltage (V)

      9

      6

      3

      0

      -3

      -6

      -9

      -12

      -15


      Time (50 ns/div)


      See Figure 63, gain = –1 V/V


      Figure 27. Large-Signal Transient Response


      D081

      VIN VOUT

      5 10 15 20 25 30 35 40 45 50 55 60 0 200 400 600 800

      Load Capacitance (pF)

      See Figure 62, gain = 1 V/V, RF = 0 Ω

      Figure 28. Overshoot and Undershoot vs CL


      D082

      Time (nsec)

      See Figure 62, gain = 1 V/V, RF = 0 Ω

      Figure 29. Input Overdrive Recovery


      D083

      Typical Characteristics: VS = 24 V (continued)

      Figure 33. Input Offset Voltage vs Input Common-Mode Voltage

      1500


      1000


      500


      0


      -500


      -1000


      -1500

      -12.5 -10 -7.5 -5 -2.5 0 2.5 5

      Output saturated and then short-circuited


      Figure 32. Output Short-Circuit Current vs Ambient Temperature

      150

      120

      90

      60

      30

      0

      -30

      -60

      -90

      -120

      -150

      -180

      -40 -20 0 20 40 60 80 100 120 140

      0 10 20 30 40 50 60 70 80 90

      Output Current (mA) D085


      Figure 31. Output Voltage Range vs Load Current

      14


      10


      6


      2


      -2


      -6


      -10


      -14

      0 200 400 600 800 1000 1200 1400

      Time (nsec) D084

      See Figure 63, gain = –1 V/V


      Figure 30. Output Overdrive Recovery

      15

      12

      9

      6

      3

      0

      -3

      -6

      -9

      -12

      -15

      VIN x -1 Gain VO

      Output Short-Circuit Current (mA)

      Input and Output Voltage (V)

      Input Offset Voltage (V)

      Output Voltage (V)

      at VS+ = 12 V, VS– = –12 V, RL = 1 kΩ, input and output are biased to midsupply, and TA ≈ 25°C. For AC specifications, VO = 2 VPP, G = 2 V/V, RF = 1 kΩ, and CL = 4.7 pF (unless otherwise noted)














































































































      Sourcing

      Sinking












































































































































































      Sourcing

      Sinking





































































































      Ambient Temperature (C)

      D086

      Input Common-Mode Voltage (V)

      Measured for 12 units

      7.5 10 12.5

      D087

    10. Typical Characteristics: VS = 5 V

      at VS+ = 5 V, VS– = 0 V, VCM= 1.25 V, RL = 1 kΩ, output is biased to midsupply, and TA ≈ 25°C. For AC specifications, VS+ =

      3.5 V, VS– = –1.5 V, VCM= 0 V, VO = 2 VPP, G = 2 V/V, RF = 1 kΩ, and CL = 4.7 pF (unless otherwise noted)


      3


      0


      Normalized Gain (dB)

      -3


      -6


      -9


      -12


      -15


      -18

      0.15


      Output Voltage (V)





















      0.1


      0.05


      0


      -0.05


      Gain = 1 V/V Gain = 1 V/V

      Gain = 2 V/V Gain = 5 V/V

      -21

      100k 1M 10M 100M

      Frequency (Hz)

      See Figure 62 and Figure 63, VO = 20 mVPP

      Figure 34. Small-Signal Response vs Gain

      Overshoot, VO = 2 VPP Undershoot, VO = 2 VPP

      Overshoot, VO = 200 mVPP Undershoot, VO = 200 mVPP































































































      60

      55

      Overshoot/Undershoot (%)

      50

      45

      40

      35

      30

      25

      20

      15

      10

      5

      0


      D010

      -0.1


      3


      Input and Output Voltage (V)

      2


      1


      0


      -1


      -2


      -3


      Time (100 ns/div)


      See Figure 62, gain = 1 V/V, RF = 0 Ω, CL = 10 pF

      Figure 35. Small-Signal Transient Response


      D01

      VIN

      VOUT

      5 10 15 20 25 30 35 40 45 50 0 200 400 600 800 1000 1200 1400

      Load Capacitance (pF)

      See Figure 62, gain = 1 V/V, RF = 0 Ω

      Figure 36. Overshoot and Undershoot vs CL

      3


      D012

      Time (nsec)

      See Figure 62, gain = 1 V/V, RF = 0 Ω

      Figure 37. Input Overdrive Recovery



























































































      Sourcing

      Sinking





















































































































      3


      D014


      Input and Output Voltage (V)

      2 2


      Output Voltage (V)

      1 1


      0 0


      -1 -1


      VIN x -1 Gain VO

      -2 -2


      -3

      0 200 400 600 800 1000 1200 1400

      -3

      0 10 20 30 40 50 60 70 80 90

      Time (nsec)

      See Figure 63, gain = –1 V/V

      D013

      Output Current (mA)


      D015

      Figure 38. Output Overdrive Recovery Figure 39. Output Voltage Range vs Output Current

      Typical Characteristics: VS = 5 V (continued)

      at VS+ = 5 V, VS– = 0 V, VCM= 1.25 V, RL = 1 kΩ, output is biased to midsupply, and TA ≈ 25°C. For AC specifications, VS+ =

      Figure 41. Input Offset Voltage vs Input Common-Mode Voltage

      3

      D017

      Input Common-Mode Voltage (V)

      Measured for 12 units

      2

      1

      0

      -1

      -2

      -3

      -1000

      -500

      0

      500

      1000

      Output saturated and then short-circuited


      Figure 40. Output Short-Circuit Current vs Ambient Temperature

      D016

      Ambient Temperature (C)

      125

      100

      75

      50

      25

      0

      -25

      -50

      -75

      -100

      -125

      -40 -20 0 20 40 60 80 100 120 140

      Output Short-Circuit Current (mA)

      Input Offset Voltage (V)

      3.5 V, VS– = –1.5 V, VCM= 0 V, VO = 2 VPP, G = 2 V/V, RF = 1 kΩ, and CL = 4.7 pF (unless otherwise noted)

      7.11 Typical Characteristics: ±2.375-V to ±12-V Split Supply

      at VO = 2 VPP, RF = 1 kΩ, RL = 1 kΩ and TA ≈ 25°C (unless otherwise noted)


      Magnitude Phase

      130 180


      Open-Loop Gain Magnitude (dB)

      110 160


      Open-Loop Phase (o)

      90 140


      70 120


      50 100


      30 80


      10 60


      -10 40

      10 100 1k 10k 100k 1M 10M 100M

      3


      Normalized Gain (dB)
































































































      VS = 5 V

      VS = 10 V VS = 24 V














      0


      -3


      -6


      -9


      -12


      -15

      100k 1M 10M 100M

      Frequency (Hz)

      Simulated with no output load


      D109

      Frequency (Hz)

      See Figure 62, gain = 1 V/V, RF = 0 Ω


      D101


      3


      Normalized Gain (dB)

      0


      -3


      -6


      -9


      -12


      -15


      Figure 42. Open-Loop Gain and Phase vs Frequency

































































































      VS= 5 V

      VS= 10 V

      VS= 24 V















      -60

      -70

      Harmonic Distortion (dBc)

      -80

      -90

      -100

      -110

      -120

      -130

      -140

      -150

      -160


      HD2, VS = 5 V

      Figure 43. Large-Signal Response vs Supply Voltage



      HD3, VS = 5 V HD2, VS = 10 V HD3, VS = 10 V HD2, VS = 24 V HD3, VS = 24 V

      100k 1M 10M 100M

      Frequency (Hz)

      See Figure 62, gain = 2 V/V


      D102

      1k 10k 100k 1M

      Frequency (Hz)

      See Figure 62, gain = 2 V/V


      D103


      Figure 44. Large-Signal Response vs Supply Voltage

      Figure 45. Harmonic Distortion vs Frequency vs Supply Voltage

      HD2, VS = 5 V

      -60

      HD3, VS = 5 V HD2, VS = 10 V HD3, VS = 10 V HD2, VS = 24 V HD3, VS = 24 V

      -70

      Harmonic Distortion (dBc)

      -80

      -90

      -100

      -110

      -120

      -130

      -140

      -150

      -160

      1k 10k 100k 1M

      100


      Input Voltage Noise (nV/Hz)

      10


      1

      10 100 1k 10k 100k 1M 10M

      Frequency (Hz)

      See Figure 63, gain = –1 V/V

      D104

      Frequency (Hz)

      Measured then fit to ideal 1/f model


      D103

      Figure 46. Harmonic Distortion vs Frequency vs Supply Voltage


      Figure 47. Input Voltage Noise Density vs Frequency

      Typical Characteristics: ±2.375-V to ±12-V Split Supply (continued)

      at VO = 2 VPP, RF = 1 kΩ, RL = 1 kΩ and TA ≈ 25°C (unless otherwise noted)

      Aux Input Voltage Noise (nV/Hz)

      10000


      1000


      100


      10

      10 100 1k 10k 100k 1M 10M

      100

      90

      Output Impedance ()

      80

      70

      60

      50

      40

      30

      20

      10

      0

      10 100 1k 10k 100k 1M 10M 100M

      Frequency (Hz)

      Measured then fit to ideal 1/f model

      Frequency (Hz)

      D106

      D108


      Figure 48. Auxiliary Input Stage Voltage Noise Density vs Frequency

      120

      Figure 49. Open-Loop Output Impedance vs Frequency


      Power Supply Rejection Ratio (dB)

      120



      Common-Mode Rejection Ratio (dB)

      100

      100


      80

      80

      60

      60

      40


      40 20


      20

      10 100 1k 10k 100k 1M 10M

      0

      10 100 1k 10k 100k 1M 10M 100M

      Frequency (Hz)

      VS = 10 V and 24 V

      D110 Frequency (Hz)

      VS = 5 V and 10 V


      D11


      Figure 50. Common-Mode Rejection Ratio vs Frequency

      PSRR VS+ PSRR VS-

      120


      Power Supply Rejection Ratio (dB)

      100


      80


      60


      40


      20


      0

      100 1k 10k 100k 1M 10M 100M


      Figure 51. Power Supply Rejection Ratio vs Frequency





































































































      20

      16

      Input Bias Current (pA)

      12

      8

      4

      0

      -4

      -8

      -12

      -16

      -20

      -12.5 -10 -7.5 -5 -2.5 0 2.5 5 7.5 10 12.5

      Frequency (Hz)

      Simulated curves, VS = 24 V

      D112

      Input Common-Mode Voltage (V)

      VS = ±12 V


      D118

      Figure 52. Power Supply Rejection Ratio vs Frequency


      Figure 53. Input Bias Current vs Input Common-Mode Voltage

      Typical Characteristics: ±2.375-V to ±12-V Split Supply (continued)

      at VO = 2 VPP, RF = 1 kΩ, RL = 1 kΩ and TA ≈ 25°C (unless otherwise noted)

      Non-Inverting Input Bias Current (A)













































































































      TA = 25C TA = 125C









      300


      200


      100


      0


      -100


      -200


      -300

      -7.5 -6 -4.5 -3 -1.5 0 1.5 3 4.5 6 7.5

      4.2


      Quiescent Current (mA)

      4


      3.8


      3.6


      3.4

      -50 -25 0 25 50 75 100 125 150

      Differential Input Voltage (V)

      Abs (VIN,Diff (max)) = VS when VS < 7 V


      D115

      Ambient Temperature (C)

      32 units, SOIC package, VS = ±5 V


      D117


      Figure 54. Input Bias Current vs Differential Input Voltage

      600


      Input Offset Voltage (V)

      400


      200


      0


      -200


      -400


      -600


      -800

      -50 -25 0 25 50 75 100 125 150

      Ambient Temperature (C)

      D116

      32 units, SOIC package


      Figure 56. Input Offset Voltage vs Ambient Temperature







































































      14000


      12000


      No. of Units in Each Bin

      10000


      8000


      6000


      4000


      2000


      -500

      -400

      -300

      -200

      -100

      0

      100

      200

      300

      400

      500

      0

      Figure 55. Quiescent Current vs Ambient Temperature


























































































































      24000

      22000

      20000

      No. of Units in Each Bin

      18000

      16000

      14000

      12000

      10000

      8000

      6000

      4000

      2000

      3.6

      3.65

      3.7

      3.75

      3.8

      3.85

      3.9

      3.95

      4

      4.05

      4.1

      0


      D120

      Quiescent Current (mA)

      27000 units, µ = 3.82 mA, σ = 17 µA, VS = 24 V

      Figure 57. Quiescent Current Distribution












































































      14


      12


      No. of Units in Each Bin

      10


      8


      6


      4


      2


      -10

      -8

      -6

      -4

      -2

      0

      2

      4

      6

      8

      10

      0


      Input Offset Voltage (V)


      D113 Input Offset Voltage Drift (V/C)


      D114

      27000 units, µ = 16 µV, σ = 63 µV, VS = 24 V

      Figure 58. Input Offset Voltage Distribution

      –40°C to +125°C fit, 32 units, µ = –0.15 µV/ºC, σ = 2.5 µV/ºC


      Figure 59. Input Offset Voltage Drift Distribution

  1. Detailed Description


    1. Overview

      The OPA810 is a single-channel, field-effect transistor (FET)-input, unity-gain stable, voltage-feedback operational amplifier with extremely low input bias current across its common-mode input voltage range. The OPA810, characterized to operate over a wide supply range of 4.75 V to 27 V, has a small-signal, unity-gain bandwidth of 140 MHz and offers both excellent DC precision and dynamic AC performance at low quiescent power. The OPA810 is fabricated on Texas Instrument's proprietary, high-speed SiGe BiCMOS process and achieves significant performance improvements over comparable FET-input amplifiers at similar levels of quiescent power. With a gain-bandwidth product (GBWP) of 70 MHz, extremely high slew rate (200 V/µs), and low noise (6.3 nV/√Hz), the OPA810 is ideal in a wide range of data acquisition and signal processing applications. The OPA810 includes input clamps to allow maximum input differential voltage of up to 7 V, making the device suitable for use with multiplexers and for processing signals with fast transients. The device achieves these benchmark levels of performance while consuming a typical quiescent current (IQ) of 3.7 mA per channel.

      The OPA810 can source and sink large amounts of current without degradation in its linearity performance. The wide bandwidth of the OPA810 implies that the device has low output impedance across a wide frequency range, thereby allowing the amplifier to drive capacitive loads up to 10 pF without requiring output isolation. This device is suitable for a wide range of data acquisition, test and measurement front-end buffer, impedance measurement, power analyzer, wideband photodiode transimpedance, and signal processing applications.


    2. Functional Block Diagram



      VS+


      OPA810


      VIN+


      + Aux-Stage


      C

      EN

      C


      + JFET-Stage VO


      EN



      VIN

      +


      VS+ 2.5 V


      VS

    3. Feature Description

      1. OPA810 Architecture

        The OPA810 features a true high-impedance input stage including a JFET differential-input pair main stage and a CMOS differential-input auxiliary (aux) stage operational within 2.5 V of the positive supply voltage. The bias current is limited to a maximum of 20 pA throughout the common-mode input range of the amplifier. The Functional Block Diagram section provides a block diagram representation for the input stage of the OPA810. The amplifier exhibits superior performance for high-speed signals (distortion, noise, and input offset voltage) while the aux stage enables rail-to-rail inputs and prevents phase reversal. The device exhibits a CMRR and PSRR of 75 dB (typical) when the input common-mode is in aux stage.

        The OPA810 also includes input clamps that enable the maximum input differential voltage of up to 7 V (lower of 7 V and total supply voltage). This architecture offers significantly greater differential input voltage capability as compared to one to two times the diode forward voltage drop maximum rating in standard amplifiers, and makes this device suitable for use with multiplexers and processing of signals with fast transients. The input bias currents are also clamped to maximum 300 µA, as Figure 54 shows, which does not load the previous driver stage or require current-limiting resistors (except limiting current through the input ESD diodes when input common-mode voltages are greater than the supply voltages). This feature also enables this amplifier to be used as a comparator in systems that require an amplifier and a comparator for signal gain and fault detection, respectively. For the lowest offset, distortion, and noise performance, limit the common-mode input voltage to the main JFET-input stage (greater than 2.5 V away from the positive supply).

        The OPA810 is a rail-to-rail output amplifier and swings to either of the rails at the output, as shown in Figure 15 for 10-V supply operation. This is particularly useful for inputs biased near the rails or when the amplifier is configured in a closed-loop gain such that the output approaches the supply voltage. When the output saturates, it recovers with 55 ns when inputs exceed the supply voltages by 0.5 V in an G = –1 V/V inverting gain with a 10–V supply. The outputs are short-circuit protected with the limits of Figure 16.

        As Figure 60 shows, an amplifier phase margin reduces and becomes unstable when driving a capacitive load (CL) at its output. Using a series resistor (RS) between the amplifier output and load capacitance introduces a zero that cancels the pole formed by the amplifier output impedance and CL in the open-loop transfer function. The OPA810 drives capacitive loads of up to 10 pF without causing instability. It is recommended to use a series resistor for larger load capacitance values, as Figure 3 shows for OPA810 configured as a unity-gain buffer. As Figure 4 shows, when used in a gain larger than 1 V/V, the OPA810 is able to drive a load capacitance larger than 10 pF without the need for a series resistor at its output.



        VIN +

        RS

        VO

        CL RL



        Figure 60. OPA810 Driving Capacitive Load

        Feature Description (continued)

      2. ESD Protection

As Figure 61 shows, all device pins are protected with internal ESD protection diodes to the power supplies. These diodes provide moderate protection to input overdrive voltages above the supplies. The protection diodes can typically support 10-mA continuous input and output currents. The differential input clamps only limit the bias current when the input common-mode voltages are within the supply voltage range, whereas current-limiting series resistors must be added at the inputs if common-mode voltages higher than the supply voltages are possible. Keep these resistor values as low as possible because using high values degrades noise performance and frequency response.


VS+



Power Sup ply ESD Cell

VIN+


+

300 µA

ICLAMP - VO


VIN-



VS-


Figure 61. Internal ESD Protection


    1. Device Functional Modes

      1. Split-Supply Operation (±2.375 V to ±13.5 V)

        To facilitate testing with common lab equipment, the OPA810 can be configured to allow for split-supply operation (see the OPA2810DGK Evaluation Module user guide). This configuration eases lab testing because the mid-point between the power rails is ground, and most signal generators, network analyzers, oscilloscopes, spectrum analyzers, and other lab equipment reference the inputs and outputs to ground. Figure 62 depicts the OPA810 configured as a noninverting amplifier and Figure 63 illustrates the OPA810 configured as an inverting amplifier. For split-supply operation referenced to ground, the power supplies VS+ and VS- are symmetrical around ground and VREF is at GND. Split-supply operation is preferred in systems where the signals swing around ground because of the ease-of-use; however, the system requires two supply rails.


      2. Single-Supply Operation (4.75 V to 27 V)

        Many newer systems use a single power supply to improve efficiency and reduce the cost of the extra power supply. The OPA810 can be used with a single supply (with the negative supply set to ground) with no change in performance if the input and output are biased within the linear operation of the device. To change the circuit from split supply to a balanced, single-supply configuration, level shift all voltages by half the difference between the power-supply rails. An additional advantage of configuring an amplifier for single-supply operation is that the effects of PSRR are minimized because the low-supply rail is grounded. See the Single-Supply Op Amp Design Techniques application report for examples of single-supply designs.

  1. Application and Implementation


NOTE

Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.


9.1 Application Information

9.1.1 Amplifier Gain Configurations

The OPA810 is a classic voltage-feedback amplifier with each channel having two high-impedance inputs and a low-impedance output. Standard application circuits (as shown in Figure 62 and Figure 63) include the noninverting and inverting gain configurations. The DC operating point for each configuration is level-shifted by the reference voltage VREF that is typically set to midsupply in single-supply operation. VREF is often connected to ground in split-supply applications.



VSIG


VREF


VIN


VREF


RG

VS+


+


-


VS-


(1+RF/RG)VSIG


VO VREF


RF

Figure 62. Noninverting Amplifier



VSIG


VREF


VIN


VREF


RG


VS+


+


-


VS-


-(RF/RG)VSIG


VO VREF


RF

Figure 63. Inverting Amplifier


Equation 1 shows the closed-loop gain of an amplifier in a noninverting configuration.

V V 1 RF V

O IN

RG

REF


(1)

Equation 2 shows the closed-loop gain of an amplifier in an inverting configuration.

V V RF V

O IN

RG

REF


(2)

Application Information (continued)

      1. Selection of Feedback Resistors

        The OPA810 is a classic voltage feedback amplifier with each channel having two high-impedance inputs and a low-impedance output. Standard application circuits (as shown in Figure 64 and Figure 65) include the noninverting and inverting gain configurations. The DC operating point for each configuration is level-shifted by the reference voltage VREF which is typically set to midsupply in single-supply operation. VREF is often connected to ground in split-supply applications.


        VSIG VREF


        VIN


        RG

        VREF


        VS+

        +


        VS-


        RF


        (1+RF/RG)VSIG

        VO VREF

        Figure 64. Noninverting Amplifier



        VREF


        VSIG


        VIN


        VREF


        RG

        VS+

        +


        VS-


        -(RF/RG)VSIG

        VO VREF


        RF


        Figure 65. Inverting Amplifier


        The closed-loop gain of an amplifier in noninverting configuration is shown in Equation 1.

        V V 1 RF V

        O IN

        RG

        REF


        (3)

        The closed-loop gain of an amplifier in an inverting configuration is shown in Equation 2.

        V V RF V

        O IN

        RG

        REF


        (4)


        The magnitude of the low-frequency gain is determined by the ratio of the magnitudes of the feedback resistor (RF) and the gain setting resistor RG. The order of magnitudes of the individual values of RF and RG offer a trade- off between amplifier stability, power dissipated in the feedback resistor network, and total output noise. The feedback network increases the loading on the amplifier output. Using large values of the feedback resistors reduces the power dissipated at the amplifier output. On the other hand, this increases the inherent voltage and amplifier current noise contribution seen at the output while lowering the frequency at which a pole occurs in the feedback factor (β). This pole causes a decrease in the phase margin at zero-gain crossover frequency and potential instability. Using small feedback resistors increases power dissipation and also degrades amplifier linearity due to a heavier amplifier output load. Figure 66 illustrates a representative schematic of the OPA810 in an inverting configuration with the input capacitors shown.



        VREF


        VSIG


        VIN


        RG CPCB


        CDIFF

        CCM


        +



        CCM

        VS+


        VS-


        -(RF/RG)VSIG VO VREF


        RF


        Figure 66. Inverting Amplifier with Input Capacitors


        The effective capacitance at the amplifier inverting input pin is shown in Equation 5, which forms a pole in β at a cut-off frequency of Equation 6.

        CIN CCM CDIFF CPCB

        where

          • CCM is the amplifier common-mode input capacitance

          • CDIFF is the amplifier differential input capacitance

          • CPCB is the PCB parasitic capacitance (5)

            FC

            1

            2RFCIN



        1. 10k 100k 1M 10M 100M

          Frequency (Hz) D802

          1k

          100

          90

          80

          70

          60

          50

          40

          30

          20

          10

          0

          100

          10k 100k 1M 10M 100M

          Frequency (Hz) D801

          1k

          120

          110

          100

          90

          80

          70

          60

          50

          40

          30

          20

          10

          0

          -10

          -20

          100

          G

          RF = 10 k, RG = 2.5 k RF = 1 M, RG = 250 k

          F

          R = 200 , R = 50

          RF = 1 M, RG = 250 k

          RF = 10 k, RG = 2.5 k

          RF = 200 , RG = 50

          Gain (dB)

          Phase (Degrees)

          For low-power systems, greater the values of the feedback resistors, the earlier in frequency does the phase margin begin to reduce and cause instability. Figure 67 and Figure 68 illustrate the loop gain magnitude and phase plots, respectively, for the OPA810 simulation in TINA-TI configured as an inverting amplifier with values of feedback resistors varying by orders of magnitudes.


          Figure 67. Loop-Gain vs Frequency for Circuit of Figure 66

          Figure 68. Loop-Gain Phase vs Frequency for Circuit of Figure 66

          Application Information (continued)

          10

          100

          10

          20

          Gain (dB)

          Voltage Noise Density (nV/Hz)

          A lower phase margin results in peaking in the frequency response and lower bandwidth as Figure 69 shows, which is synonymous with overshoot and ringing in the pulse response results. The OPA810 offers a flat-band voltage noise density of 6.3 nV/√Hz. TI recommends selecting an RF so the voltage noise contribution does not exceed that of the amplifier. Figure 70 shows the voltage noise density variation with value of resistance at 25°C. A 2-kΩ resistor exhibits a thermal noise density of 5.75 nV/√Hz which is comparable to the flatband noise of the OPA810. Hence, TI recommends using an RF lower than 2 kΩ while being large enough to not dissipate excessive power for the output voltage swing and supply current requirements of the application. The Noise Analysis and the Effect of Resistor Elements on Total Noise section shows a detailed analysis of the various contributors to noise.


          30

          RF = 200 , RG = 50 RF = 10 k, RG = 2.5 k RF = 1 M, RG = 250 k

          1000


          -10

          10k

          100k

          1M

          Frequency (Hz)

          10M

          100M

          D806

          0.1

          10

          100

          1k 10k 100k 1M 10M

          Resistance ()

          D803


          Figure 69. Closed-Loop Gain vs. Frequency for Circuit of Figure 66

          Figure 70. Thermal Noise Density vs Resistance


          1

          0

      2. Noise Analysis and the Effect of Resistor Elements on Total Noise

The OPA810 provides a low input-referred broadband noise voltage density of 6.3 nV/√Hz while requiring a low 3.7-mA quiescent supply current. To take full advantage of this low input noise, careful attention to the other possible noise contributors is required. Figure 71 shows the operational amplifier noise analysis model with all the noise terms included. In this model, all the noise terms are taken to be noise voltage or current density terms in nV/√Hz or pA/√Hz.


RS ERS


ENI

+

EO

IBN


4kTR S

RF


4kT R G

RG IBI

4kTR F


4kT 1.6E 20 J

at 290 K

Figure 71. Operational Amplifier Noise Analysis Model


The total output spot noise voltage is computed as the square root of the squared contributing terms to the output noise voltage. This computation adds all the contributing noise powers at the output by superposition, then calculates the square root to get back to a spot noise voltage. Figure 71 shows the general form for this output noise voltage using the terms shown in Equation 7.

E E 2 I R 4kTR

2

NG2 I R 4kTR NG

2

O NI BN S S

BI F F




  1. Dividing this expression by the noise gain (NG = 1 + RF / RG) shows the equivalent input referred spot noise voltage at the noninverting input; see Equation 8.

    2

    2 I R  4kTR

    EN

    E 2 IBNRS 4kTRS BI F F

    NI NG NG


  2. Substituting large resistor values into Equation 8 can quickly dominate the total equivalent input referred noise. A source impedance on the noninverting input of 2-kΩ adds a Johnson voltage noise term similar to that of the amplifier (6.3 nV/√Hz).

    Table 1 compares the noise contributions from the various terms when the OPA810 is configured in a noninverting gain of 5 V/V as Figure 72 shows. Two cases are considered where the resistor values in case 2 are 10x the resistor values in case 1. The total output noise in case 1 is 34 nV/√Hz while the noise in case 2 is

    51.5 nV/√Hz. The large value resistors in case 2 dilute the benefits of selecting a low noise amplifier like the OPA810. To minimize total system noise, reduce the size of the resistor values. This increases the amplifiers output load and results in a degradation of distortion performance. The increased loading increases the dynamic power consumption of the amplifier. The circuit designer must make the appropriate tradeoffs to maximize the overall performance of the amplifier to match the system requirements.

    VS+ = 5V

    +


    Case1: 200 O RS

    Case2: 2 kO

    EO


    VS- = -5V


    RG RF


    Case1: 250 O

    Case2: 2.5 kO

    Case1: 1 kO

    Case2: 10 kO

    Figure 72. Comparing Noise Contributors for Two Cases With the Amplifier in a Noninverting Gain of 5 V/V


    Table 1. Comparing Noise Contributions for the Circuit in Figure 72



    NOISE SOURCE


    OUTPUT NOISE EQUATION

    CASE 1

    CASE 2

    NOISE SOURCE VALUE

    VOLTAGE NOISE CONTRIBUTI

    ON (nV/√Hz)

    NOISE POWER CONTRIBUTI ON (nV2/Hz)


    CONTRIBUTI ON (%)

    NOISE SOURCE VALUE

    VOLTAGE NOISE CONTRIBUTI

    ON (nV/√Hz)

    NOISE POWER CONTRIBUTI ON (nV2/Hz)


    CONTRIBUTI ON (%)

    Source resistor, RS

    ERS (1 + RF

    /RG)

    1.82

    nV/√Hz

    9.1

    82.81

    7.15

    5.76

    nV/√Hz

    28.8

    829.44

    31.29

    Gain resistor, RG

    ERG (RF / RG)

    2.04

    nV/√Hz

    8.16

    66.59

    5.75

    6.44

    nV/√Hz

    25.76

    663.58

    25.03

    Feedback resistor, RF

    ERF

    4.07

    nV/√Hz

    4.07

    16.57

    1.43

    12.87

    nV/√Hz

    12.87

    165.64

    6.25

    Amplifier voltage noise,

    ENI

    ENI (1 + RF / RG)

    6.3

    nV/√Hz


    31.5


    992.25


    85.67

    6.3

    nV/√Hz


    31.5


    992.25


    37.43

    Inverting current noise,

    IBI


    IBI (RF || RG)


    5 fA/√Hz


    5.0E-3




    5 fA/√Hz


    50E-3



    Noninverting current noise,

    IBN

    IBNRS (1 + RF/ RG)


    5 fA/√Hz


    1.0E-3




    5 fA/√Hz


    10E-3



      1. Typical Applications

        1. Transimpedance Amplifier

          The high GBWP and low input voltage and current noise for the OPA810 make the device an ideal wideband transimpedance amplifier for moderate to high transimpedance gains.



          VBIAS



          Oscillosco pe with 50-0 Inputs

          +5 V

          Sup ply Decouplin g n ot shown



          CD 20 pF


          CPCB

          0.3 pF


          +


          -


          -5 V

          RF

          OPA810

          100 k0


          CF + CPCB

          1.03 pF


          Figure 73. Wideband, High-Sensitivity, Transimpedance Amplifier


          1. Design Requirements

            Table 2 lists the design requirements for a high-bandwidth, high-gain transimpedance amplifier circuit.


            Table 2. Design Requirements


            PARAMETER

            DESIGN REQUIREMENT

            Target bandwidth

            > 2 MHz

            Transimpedance gain

            100 kΩ

            Photodiode capacitance

            20 pF


          2. Detailed Design Procedure

            Designs that require high bandwidth from a large area detector with relatively high transimpedance gain benefit from the low input voltage noise of the OPA810. This input voltage noise is peaked up over frequency by the diode source capacitance, and can (in many cases) become the limiting factor to input sensitivity. The key elements to the design are the expected diode capacitance (CD) with the reverse bias voltage (VBIAS) applied, the desired transimpedance gain, RF, and the GBWP for the OPA810 (70 MHz). Figure 73 shows a transimpedance circuit with the parameters as described in Table 2. With these three variables set (and including the parasitic input capacitance for the OPA810 and the printed circuit board (PCB) added to CD), the feedback capacitor value (CF) can be set to control the frequency response. The Transimpedance Considerations for High-Speed Amplifiers application report discusses using high-speed amplifiers for transimpedance applications. Set the feedback pole according to Equation 9 in order to achieve a maximally-flat second-order Butterworth frequency response:

            1

            2 R C

            GBWP

            4 R C

            F F F D


  3. The input capacitance of the amplifier is the sum of the common-mode and differential capacitance (2.0 + 0.5) pF. The parasitic capacitance from the photodiode package and the PCB is approximately 0.3 pF. Using Equation 5 gives a total input capacitance of CD = 22.8 pF. From Equation 9, set the feedback pole at 1.55 MHz. Setting the pole at 1.55 MHz requires a total feedback capacitance of 1.03 pF.

    F D

    Equation 10 shows the approximate –3-dB bandwidth of the transimpedance amplifier circuit:

    f3dB

    GBWP / (2 R C )Hz




Equation 10 estimates a closed-loop bandwidth of 2.19 MHz. Figure 74 and Figure 75 show the loop-gain magnitude and phase plots from the TINA-TI simulations of the transimpedance amplifier circuit of Figure 73. The 1/β gain curve has a zero from RF and CIN at 70 kHz and a pole from RF and CF cancelling the 1/β zero at 1.5 MHz, resulting in a 20-dB per decade rate-of-closure at the loop-gain crossover frequency (the frequency where AOL equals 1/β), ensuring a stable circuit. A phase margin of 62° is obtained with a closed-loop bandwidth of 3 MHz and a 100-kΩ transimpedance gain.


10k 100k 1M 10M 100M

Frequency (Hz) D805

1k

100

90

80

70

60

50

40

30

20

10

0

100

10k 100k 1M 10M 100M

Frequency (Hz) D804

1k

120

110

100

90

80

70

60

50

40

30

20

10

0

-10

100

AOL

1/

AOL

1/

AOL

AOL

Gain (dB)

Phase (Degrees)

        1. Application Curves


          Figure 74. Loop-Gain Magnitude vs Frequency for the Transimpedance Amplifier Circuit of Figure 73

          Figure 75. Loop-Gain Phase vs Frequency for the Transimpedance Amplifier Circuit of Figure 73

              1. High-Z Input Data Acquisition Front-End

                An ideal data acquisition system must measure a parameter without altering the measurand. When measuring a voltage or current from sensors with a large output impedance, an extremely high input impedance front-end with a pA range bias current is needed. Figure 76 shows an example circuit with the OPA810 used at the front-end. For systems with large input voltage attenuated with the MΩ range resistor divider, the OPA810 with its pA range bias currents adds negligible offset voltage and distortion because of the bias current induced resistor voltage drops. This circuit shows a funneling architecture with the OPA810 FET-input amplifier used as a unity-gain buffer, followed by attenuation to the ADS9110 5-V, full-scale input range and the ADC input drive using the THS4561 fully-differential amplifier (FDA). The THS4561 helps achieve better SNR and ENOB than a similar 5-V FDA, with a higher 12.6-V supply voltage and signal swings up to the ADC full-scale input range.

                As a result of the capacitive switching and current inrush on the ADC VREF input pin, a wide bandwidth amplifier such as the OPA837 is used with the OPA378 in a composite loop as a reference buffer. The OPA378, driven from the REF5050 5-V voltage reference, offers high precision and the OPA837 gives fast-settling performance for the ADC reference input drive. See the Reference Design Maximizing Signal Dynamic Range for True 10 Vpp Differential Input to 20 bit ADC design guide for more a detailed analysis of this high-Z front-end.


                CF

                12V

                RF


                VIN+

                R C


                OPA810

                +


                -12V


                12V


                RG

                12V


                VOCM

                THS456 1

                +

                RG

                -0.2V


                RS


                CCB CCB

                1.8V 1.8V


                AVDD DVDD


                ADS911 0

                18-bit 2 MSPS

                VREF


                VIN-

                R C

                OPA810

                +


                -12V


                12V


                RF R'

                R'

                5V

                CF

                5V


                REF505 0

                5.0 V

                Reference

                RFILT


                CFILT

                OPA378

                +

                OPA837

                +


                Figure 76. High-Z Input Data Acquisition Front-End

              2. Multichannel Sensor Interface

          High-Z input amplifiers are particularly useful when interfaced with sensors that have relatively high output impedance. Such multichannel systems usually interface these sensors with the signal chain through a multiplexer. Figure 77 shows one such implementation using an amplifier for the interface with each sensor, and driving into an ADC through a multiplexer. An alternate circuit, shown in Figure 78, can use a single higher GBWP and fast-settling amplifier at the output of the multiplexer. This architecture gives rise to large signal transients when switching between channels, where the settling performance of the amplifier and maximum allowed differential input voltage limits signal chain performance and amplifier reliability, respectively.


          +


          +

          MUX


          ADC


          +


          Figure 77. Multichannel Sensor Interface Using Multiple Amplifiers



          -

          MUX +


          OPA810


          ADC


          Figure 78. Multichannel Sensor Interface Using a Single Higher GBWP Amplifier


          Figure 79 shows the output voltage and input differential voltage when a 8-V step is applied at the noninverting terminal of the OPA810 configured as a unity-gain buffer of Figure 78.


          7.5


          Input and Output Voltage (V)

          5


          2.5


          0


          -2.5


          -5


          Time (10 ns/div)


          VIN VO

          VIN,Diff


          BD_M

          Figure 79. Large-Signal Transient Response Using the OPA810


          Because of the fast input transient, the amplifier is slew-limited and the inputs cease to track each other (a maximum VIN,Diff of 7 V is shown in Figure 79) until the output reaches its final value and the negative feedback loop is closed. For standard amplifiers with a 0.7-V to 1.5-V maximum VIN,Diff rating, current-limiting resistors must be used in series with the input pins to protect the device from irreversible damage, which also limits the device frequency response. The OPA810 has built-in input clamps that allow the application of as much as 7 V of VIN,Diff, with no external resistors required and no damage to the device or a shift in performance specifications. Such an input-stage architecture, coupled with its fast settling performance, makes the OPA810 a good fit for multichannel sensor multiplexed systems.

  1. Power Supply Recommendations

    The OPA810 is intended for operation on supplies ranging from 4.75 V to 27 V. The OPA810 can be operated on single-sided supplies, split and balanced bipolar supplies, or unbalanced bipolar supplies. Operating from a single supply can have numerous advantages. With the negative supply at ground, the DC errors resulting from the –PSRR term can be minimized. Typically, AC performance improves slightly at 10-V operation with minimal increase in supply current. Minimize the distance (< 0.1") from the power-supply pins to high-frequency, 0.01-µF decoupling capacitors. A larger capacitor (2.2 µF typical) is used along with a high-frequency, 0.01-µF, supply- decoupling capacitor at the device supply pins. For single-supply operation, only the positive supply has these capacitors. When a split supply is used, use these capacitors from each supply to ground. If necessary, place the larger capacitors further from the device and share these capacitors among several devices in the same area of the printed circuit board (PCB). An optional supply decoupling capacitor across the two power supplies (for split- supply operation) reduces second harmonic distortion.


  2. Layout


    1. Layout Guidelines

      Achieving optimum performance with a high-frequency amplifier such as the OPA810 requires careful attention to board layout parasitics and external component types. The OPA2810EVM can be used as a reference when designing the circuit board. Recommendations that optimize performance include:

      1. Minimize parasitic capacitance to any AC ground for all signal I/O pins. Parasitic capacitance on the output and inverting input pins can cause instability—on the noninverting input, this capacitance can react with the source impedance to cause unintentional band-limiting. To reduce unwanted capacitance, open a window around the signal I/O pins in all ground and power planes around those pins. Otherwise, ground and power planes must be unbroken elsewhere on the board.

      2. Minimize the distance (< 0.1") from the power-supply pins to high-frequency, 0.01-µF decoupling capacitors. At the device pins, do not allow the ground and power plane layout to be in close proximity to the signal I/O pins. Avoid narrow power and ground traces to minimize inductance between the pins and the decoupling capacitors. The power-supply connections must always be decoupled with these capacitors. Larger (2.2-µF to 6.8-µF) decoupling capacitors, effective at lower frequency, must also be used on the supply pins. These capacitors can be placed somewhat farther from the device and shared among several devices in the same area of the PC board.

      3. Careful selection and placement of external components preserve the high-frequency performance of the OPA810. Resistors must be a low reactance type. Surface-mount resistors work best and allow a tighter overall layout. Metal film and carbon composition axially leaded resistors can also provide good high- frequency performance. Again, keep their leads and PCB trace length as short as possible. Never use wirewound type resistors in a high-frequency application. Because the output pin and inverting input pin are the most sensitive to parasitic capacitance, always position the feedback and series output resistor, if any, as close as possible to the output pin. Other network components, such as noninverting input termination resistors, must also be placed close to the package. Even with a low parasitic capacitance shunting the external resistors, excessively high resistor values can create significant time constants that can degrade performance. Good axial metal film or surface-mount resistors have approximately 0.2 pF in shunt with the resistor. For resistor values greater than 10 kΩ, this parasitic capacitance can add a pole or zero close to the GBWP of 70 MHz and subsequently affects circuit operation. Keep resistor values as low as possible and consistent with load driving considerations. Lowering the resistor values keeps the resistor noise terms low, and minimizes the effect of parasitic capacitance, however lower resistor values increase the dynamic power consumption because RF and RG become part of the amplifiers output load network. Transimpedance applications (see the Transimpedance Amplifier section) can use whatever feedback resistor is required by the application as long as the feedback compensation capacitor is set considering all parasitic capacitance terms on the inverting node.

      4. Connections to other wideband devices on the board can be made with short direct traces or through onboard transmission lines. For short connections, consider the trace and the input to the next device as a lumped capacitive load. Relatively wide traces (50 mils to 100 mils) must be used, preferably with ground and power planes opened up around them. Estimate the total capacitive load and set RS for sufficient phase margin and stability. Low parasitic capacitive loads (< 10 pF) may not need an RS because the OPA810 is nominally compensated to operate with a 10-pF parasitic load. Higher parasitic capacitive loads without an RS are allowed with increase in signal gain (increasing the unloaded phase margin). If a long trace is

        Layout Guidelines (continued)

        required, and the 6-dB signal loss intrinsic to a doubly-terminated transmission line is acceptable, implement a matched impedance transmission line using microstrip or stripline techniques (consult an ECL design handbook for microstrip and stripline layout techniques). A 50-Ω environment is normally not necessary onboard, and a higher impedance environment improves distortion. With a characteristic board trace impedance defined based on board material and trace dimensions, a matching series resistor into the trace from the output of the OPA810 is used as well as a terminating shunt resistor at the input of the destination device. Remember also that the terminating impedance is the parallel combination of the shunt resistor and the input impedance of the destination device—this total effective impedance must be set to match the trace impedance. If the 6-dB attenuation of a doubly-terminated transmission line is unacceptable, a long trace can be series-terminated at the source end only. Treat the trace as a capacitive load in this case and set the series resistor value to obtain sufficient phase margin and stability. This does not preserve signal integrity as well as a doubly-terminated line. If the input impedance of the destination device is low, the signal attenuates because of the voltage divider formed by the series output into the terminating impedance.

      5. Take care to design the PCB layout for optimal thermal dissipation. For the extreme case of 125°C operating ambient, using the approximate 134.8°C/W for the SOIC package, and an internal power of 24-V supply × 4.7-mA 125°C supply current gives a maximum internal power dissipation of 113 mW. This power gives a 15°C increase from ambient to junction temperature. Load power adds to this value and this dissipation must also be calculated to determine the worst-case safe operating point.

      6. Socketing a high-speed device such as the OPA810 is not recommended. The additional lead length and pin-to-pin capacitance introduced by the socket can create an extremely troublesome parasitic network that can almost make achieving a smooth, stable frequency response impossible. Best results are obtained by soldering the OPA810 onto the board.


        11.1.1 Thermal Considerations

        The OPA810 does not require heat sinking or airflow in most applications. Maximum allowed junction temperature sets the maximum allowed internal power dissipation. Do not allow the maximum junction temperature to exceed 150°C.

        Operating junction temperature (TJ) is given by TA + PD × θJA. The total internal power dissipation (PD) is the sum of quiescent power (PDQ) and additional power dissipated in the output stage (PDL) to deliver load power. Quiescent power is the specified no-load supply current times the total supply voltage across the part. PDL depends on the required output signal and load but would, for a grounded resistive load, be at a maximum when the output is fixed at a voltage equal to half of either supply voltage (for equal split-supplies). Under this condition PDL = VS 2 / (4 × RL) where RL includes feedback network loading.

        The power in the output stage and not into the load that determines internal power dissipation.

        As a worst-case example, compute the maximum TJ using a DCK (SC70 package) configured as a unity gain buffer, operating on ±12-V supplies at an ambient temperature of 25°C and driving a grounded 500-Ω load.

        PD = 24 V × 4.7 mA + 122 /(4 × 500 Ω) = 184.8 mW

        Maximum TJ = 25°C + (0.185 W × 190.8°C/W) = 60°C, which is well below the maximum allowed junction temperature of 150oC.

        11.2 Layout Example




        Representative schematic of a single channe l

        VS+



        CBYP


        + RS



        CBYP

        VS-


        RG RF



        Gro und and power plan e e xist on inne r la yer s.


        Remove G ND and Power plan e und er o utp ut and inverting pins to minimize stray PCB capacitance


        1 8


        RG CBYP


        Gro und and power plan e re mo ved from in ner layers. Gro und fill on outer layers a lso removed


        Place bypass capacitors

        Place inpu t resistor close to pin 2 to 2 7

        minimize p arasitic ca pacita nce


        Place feedback r esistor on the

        bottom of PCB be tween pin s 2 and 6

        RS

        3 6


        Place bypass capacitors

        close to power pins 4 5

        CBYP

        close to power pins


        Place output r esi stors close to output pin to minimize para sitic capa citance


        Remove G ND and Power plan e und er o utp ut and inverting pins to minimize stray PCB capacitance


        Figure 80. Layout Recommendation

  1. Device and Documentation Support


    1. Documentation Support

12.1.1 Related Documentation

For related documentation see the following:


    1. Receiving Notification of Documentation Updates

      To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper right corner, click on Alert me to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document.


    2. Community Resources

      TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight from the experts. Search existing answers or ask your own question to get the quick design help you need.

      Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use.

    3. Trademarks

      E2E is a trademark of Texas Instruments.

      All other trademarks are the property of their respective owners.

    4. Electrostatic Discharge Caution

      This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

      ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.


    5. Glossary

      SLYZ022 TI Glossary.

      This glossary lists and explains terms, acronyms, and definitions.

  1. Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

PACKAGE OPTION ADDENDUM


www.ti.com 6-Feb-2020


PACKAGING INFORMATION


Orderable Device

Status

(1)

Package Type

Package Drawing

Pins

Package Qty

Eco Plan

(2)

Lead/Ball Finish

(6)

MSL Peak Temp

(3)

Op Temp (°C)

Device Marking

(4/5)

Samples

OPA810IDBVT

PREVIEW

SOT-23

DBV

5

250

TBD

Call TI

Call TI

-40 to 125



OPA810IDCKT

PREVIEW

SC70

DCK

5

250

TBD

Call TI

Call TI

-40 to 125



OPA810IDR

ACTIVE

SOIC

D

8

2500

Green (RoHS & no Sb/Br)

NIPDAU

Level-2-260C-1 YEAR

-40 to 125

810


OPA810IDT

ACTIVE

SOIC

D

8

250

Green (RoHS & no Sb/Br)

NIPDAU

Level-2-260C-1 YEAR

-40 to 125

810


XOPA810IDBVT

ACTIVE

SOT-23

DBV

5

250

TBD

Call TI

Call TI

-40 to 125



XOPA810IDCKT

ACTIVE

SC70

DCK

5

250

TBD

Call TI

Call TI

-40 to 125



XOPA810IDT

ACTIVE

SOIC

D

8

250

TBD

Call TI

Call TI

-40 to 125



(1) The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.


(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free".

RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.

Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement.


(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.


(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.


(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device.


(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width.


Addendum-Page 1

PACKAGE OPTION ADDENDUM


www.ti.com 6-Feb-2020



Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.


In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.



Addendum-Page 2

PACKAGE MATERIALS INFORMATION


www.ti.com 24-Nov-2019


TAPE AND REEL INFORMATION


*All dimensions are nominal

Device

Package Type

Package Drawing

Pins

SPQ

Reel Diameter (mm)

Reel Width W1 (mm)

A0

(mm)

B0

(mm)

K0

(mm)

P1

(mm)

W

(mm)

Pin1 Quadrant

OPA810IDT

SOIC

D

8

250

180.0

12.4

6.4

5.2

2.1

8.0

12.0

Q1


Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION


www.ti.com 24-Nov-2019



*All dimensions are nominal

Device

Package Type

Package Drawing

Pins

SPQ

Length (mm)

Width (mm)

Height (mm)

OPA810IDT

SOIC

D

8

250

210.0

185.0

35.0


Pack Materials-Page 2


DBV0005A

PACKAGE OUTLINE

SOT-23 - 1.45 mm max height


SCALE 4.000

SMALL OUTLINE TRANSISTOR



PIN 1 INDEX AREA


3.0

2.6

B

1.75

1.45 A

C


0.1

C

1.45

0.90


1 5


0.95

2X

3.05

1.9

1.9

2.75

2


4

5X

0.5 3

0.3


0.2

C

A

B


(1.1)


0.15

TYP

0.00


0.25

GAGE PLANE

0.22

TYP

TYP

0.08



0

8 TYP


0.6

0.3


SEATING PLANE


4214839/E 09/2019

NOTES:


  1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M.

  2. This drawing is subject to change without notice.

  3. Refernce JEDEC MO-178.

  4. Body dimensions do not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side.


    DBV0005A

    EXAMPLE BOARD LAYOUT

    SOT-23 - 1.45 mm max height

    SMALL OUTLINE TRANSISTOR



    1


    5X (0.6)


    5X (1.1)


    PKG


    5



    2

    2X (0.95)


    SYMM


    (1.9)


    3 4


    (R0.05) TYP

    (2.6)


    LAND PATTERN EXAMPLE

    EXPOSED METAL SHOWN SCALE:15X



    SOLDER MASK OPENING


    METAL


    METAL UNDER SOLDER MASK


    SOLDER MASK OPENING


    EXPOSED METAL


    0.07 MAX ARROUND

    EXPOSED METAL


    0.07 MIN ARROUND


    NON SOLDER MASK DEFINED (PREFERRED)


    SOLDER MASK DEFINED


    SOLDER MASK DETAILS


    4214839/E 09/2019

    NOTES: (continued)


  5. Publication IPC-7351 may have alternate designs.

  6. Solder mask tolerances between and around signal pads can vary based on board fabrication site.


    DBV0005A

    EXAMPLE STENCIL DESIGN

    SOT-23 - 1.45 mm max height

    SMALL OUTLINE TRANSISTOR



    1


    5X (0.6)


    5X (1.1)

    PKG


    5



    2

    2X(0.95)


    SYMM


    (1.9)



    (R0.05) TYP

    3 4


    (2.6)


    SOLDER PASTE EXAMPLE

    BASED ON 0.125 mm THICK STENCIL SCALE:15X



    4214839/E 09/2019

    NOTES: (continued)


  7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations.

  8. Board assembly site may have different recommendations for stencil design.


    D0008A

    PACKAGE OUTLINE

    SOIC - 1.75 mm max height


    SCALE 2.800


    SMALL OUTLINE INTEGRATED CIRCUIT



    C



    A


    .189-.197

    [4.81-5.00]

    NOTE 3


    .228-.244 TYP

    [5.80-6.19]

    .050

    [1.27]

    PIN 1 ID AREA

    6X


    1 8


    2X

    .150

    [3.81]

    C

    SEATING PLANE


    .004 [0.1]



    4


    B .150-.157

    [3.81-3.98]

    NOTE 4


    5

    8X .012-.020


    .010 [0.25]

    C

    A

    B

    [0.31-0.51]

    4X (0 -15 )


    .069 MAX

    [1.75]


    .005-.010 TYP

    [0.13-0.25]


    4X (0 -15 )


    SEE DETAIL A

    .010

    [0.25]


    0 - 8

    .004-.010

    [0.11-0.25]

    .016-.050

    [0.41-1.27]


    (.041)

    [1.04]


    DETAIL A

    TYPICAL


    4214825/C 02/2019

    NOTES:


    1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches. Dimensioning and tolerancing per ASME Y14.5M.

    2. This drawing is subject to change without notice.

    3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed .006 [0.15] per side.

    4. This dimension does not include interlead flash.

    5. Reference JEDEC registration MS-012, variation AA.


      D0008A

      EXAMPLE BOARD LAYOUT

      SOIC - 1.75 mm max height

      SMALL OUTLINE INTEGRATED CIRCUIT


      8X (.061 )

      [1.55]


      1


      8X (.024)

      [0.6]


      4

      6X (.050 )

      [1.27]


      SYMM


      (.213)

      [5.4]


      LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:8X


      SEE DETAILS


      8


      SYMM


      (R.002 ) TYP

      5 [0.05]


      METAL SOLDER MASK

      SOLDER MASK METAL UNDER

      OPENING

      OPENING

      SOLDER MASK



      EXPOSED METAL

      .0028 MAX

      [0.07]

      ALL AROUND


      EXPOSED

      METAL


      .0028 MIN

      [0.07]

      ALL AROUND


      NON SOLDER MASK DEFINED

      SOLDER MASK DEFINED


      SOLDER MASK DETAILS


      4214825/C 02/2019


      NOTES: (continued)


    6. Publication IPC-7351 may have alternate designs.

    7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.


      D0008A

      EXAMPLE STENCIL DESIGN

      SOIC - 1.75 mm max height

      SMALL OUTLINE INTEGRATED CIRCUIT


      8X (.061 )

      [1.55]


      1


      SYMM


      8


      8X (.024)

      [0.6]


      SYMM



      4

      6X (.050 )

      [1.27]


      (.213)

      [5.4]

      (R.002 ) TYP

      5 [0.05]


      SOLDER PASTE EXAMPLE

      BASED ON .005 INCH [0.125 MM] THICK STENCIL SCALE:8X


      4214825/C 02/2019


      NOTES: (continued)


    8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations.

    9. Board assembly site may have different recommendations for stencil design.

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