Nanopower, rail-to-rail input and output, 5 V CMOS operational
amplifiers
Datasheet - production data
Features
Submicro ampere current consumption: 580 nA typ per channel at 25 °C at
VCC = 1.8 V
Low supply voltage: 1.5 V - 5.5 V
Unity gain stable
Rail-to-rail input and output
Gain bandwidth product: 8 kHz typ
Low input bias current: 5 pA max at 25 °C
High tolerance to ESD: 2 kV HBM
Industrial temperature range:
-40 °C to 85 °C
Benefits
42 years of typical equivalent lifetime
(for TSU101) if supplied by a 220 mAh coin type Lithium battery
Tolerance to power supply transient drops
Accurate signal conditioning of high impedance sensors
Application performances guaranteed over industrial temperature range
Fast desaturation
Applications
Ultra long life battery-powered applications
Power metering
UV and photo sensors
Electrochemical and gas sensors
Pyroelectric passive infrared (PIR) detection
Battery current sensing
Medical instrumentation
RFID readers
Description
The TSU101, TSU102, and TSU104 operational amplifiers offer an ultra low-power consumption of 580 nA typical and 750 nA maximum per channel when supplied by 1.8 V. Combined with a supply voltage range of 1.5 V to 5.5 V, these features allow the TSU10x series to be efficiently supplied by a coin type Lithium battery or a regulated voltage in low-power applications.
The 8 kHz gain bandwidth of these devices make them ideal for sensor signal conditioning, battery supplied, and portable applications.
September 2015 DocID024317 Rev 3 1/33 This is information on a product in full production. www.st.com
Contents
ln2+
VCC-
VCC-
ln2-
ln1+
ln1+[Ij
•
+ -
IN+ 0--1
0vcc+
0vcc+
Figure 1: Pin connections for each package (top view)
=
OUT [2J
vcc-0
=
OUT
IN-
SC70-5/SOT23-5 (TSU101)
SC70-5/SOT23-5 (TSU101R)
Out1 QJ
ln1-0
[I]vcc+
0 Out2
@] ln2- [}] ln2+
Out1 •
ln1-0
[I]vcc+
Out2
DFN8 2x2 (TSU102)
MiniS08 (TSU102)
-
'
C
:5 :J
'<I"
Out4
QFN16 3x3 (TSU104)
TSSOP14 (TSU104)
Out3
Out2(I]
E
:J 5
0 0
E
(')
N
ln3-
ln2+[}]
VCC-
ln4+
t!lo3•
ln2-@J
(I ln3+
(s') (6') A (s')
C0
ln 2+ ])
ln1+ 0 +
VCC+
<II ln4+
(IT VCC-
NC
VCC+ J)
NC })
ln4-
ln1-0 -
ln1+ J)
E
0
0
:=!:
DocID024317 Rev 3 3/33
conditions
Absolute maximum ratings and operating conditions
Table 1: Absolute maximum ratings (AMR)
Symbol | Parameter | Value | Unit | |
VCC | 6 | V | ||
Vid | ±VCC | |||
Vin | (VCC-) - 0.2 to (VCC+) + 0.2 | |||
Iin | 10 | mA | ||
Tstg | Storage temperature | -65 to 150 | °C | |
Tj | Maximum junction temperature | 150 | ||
Rthja | SC70-5 | 205 | °C/W | |
SOT23-5 | 250 | |||
DFN8 2x2 | 117 | |||
MiniSO8 | 190 | |||
QFN16 3x3 | 45 | |||
TSSOP14 | 100 | |||
ESD | 2000 | V | ||
200 | ||||
All other packages except SC70-5 | 1000 | |||
SC70-5 | 900 | |||
200 | mA |
Notes:
(1)All voltage values, except the differential voltage are with respect to the network ground terminal. (2)The differential voltage is the non-inverting input terminal with respect to the inverting input terminal. (3)((VCC+) - Vin) must not exceed 6 V, (Vin - VCC-) must not exceed 6 V.
(4)The input current must be limited by a resistor in series with the inputs.
(5)Rth are typical values.
(6)Short-circuits can cause excessive heating and destructive dissipation.
(7)Related to ESDA/JEDEC JS-001 Apr. 2010 (8)Related to JEDEC JESD22-A115C Nov.2010 (9)Related to JEDEC JESD22-C101-E Dec. 2009
(10)Related to JEDEC JESD78C Sept. 2010
Table 2: Operating conditions
Symbol | Parameter | Value | Unit |
VCC | Supply voltage | 1.5 to 5.5 | V |
Vicm | Common mode input voltage range | (VCC-) - 0.1 to (VCC+) + 0.1 | |
Toper | Operating free air temperature range | -40 to 85 | °C |
4/33 DocID024317 Rev 3
Table 3: Electrical characteristics at VCC+ = 1.8 V with VCC- = 0 V, Vicm = VCC/2, Tamb = 25 ° C, and RL = 1 MΩ connected to VCC/2 (unless otherwise specified)
Symbol | Parameter | Conditions | Min. | Typ. | Max. | Unit |
DC performance | ||||||
Vio | Input offset voltage | -3 | 0.1 | 3 | mV | |
-40 °C < T< 85 °C | -3.4 | 3.4 | ||||
ΔVio/ΔT | Input offset voltage drift | -40 °C < T< 85 °C | 5 | μV/°C | ||
ΔVio | Long-term input offset voltage drift | 0.18 | µV/ √month | |||
Iio | 1 | 5 | pA | |||
-40 °C < T< 85 °C | 30 | |||||
Iib | 1 | 5 | ||||
-40 °C < T< 85 °C | 30 | |||||
CMR | Common mode rejection ratio 20 log (ΔVicm/ΔVio) | Vicm = 0 to 0.6 V, Vout = VCC/2 | 65 | 85 | dB | |
-40 °C < T< 85 °C | 65 | |||||
Vicm = 0 to 1.8 V, Vout = VCC/2 | 55 | 74 | ||||
-40 °C < T< 85 °C | 55 | |||||
Avd | Large signal voltage gain | Vout = 0.3 V to ((VCC+) - 0.3 V), RL = 100 kΩ | 95 | 115 | ||
-40 °C < T< 85 °C | 95 | |||||
VOH | High level output voltage, (drop from VCC+) | RL = 100 kΩ | 40 | mV | ||
-40 °C < T< 85 °C | 40 | |||||
VOL | Low level output voltage | RL = 100 kΩ | 40 | |||
-40 °C < T< 85 °C | 40 | |||||
Iout | Output sink current | Vout = VCC , VID = -200 mV | 4 | 5 | mA | |
-40 °C < T< 85 °C | 4 | |||||
Output source current | Vout = 0 V, VID = 200 mV | 4 | 5 | |||
-40 °C < T< 85 °C | 4 | |||||
ICC | Supply current, (per channel) | No load, Vout = VCC/2 | 580 | 750 | nA | |
-40 °C < T< 85 °C | 800 | |||||
AC performance | ||||||
GBP | Gain bandwidth product | RL = 1 MΩ, CL = 60 pF | 8 | kHz | ||
Fu | Unity gain frequency | 8 | ||||
ϕm | Phase margin | 60 | Degrees | |||
Gm | Gain margin | 10 | dB | |||
SR | Slew rate (10 % to 90 %) | RL = 1 MΩ, CL = 60 pF Vout = 0.3 V to ((VCC+) - 0.3 V) | 3 | V/ms | ||
en | Equivalent input noise voltage | f = 100 Hz | 265 | nV/√Hz | ||
f = 1 kHz | 265 |
DocID024317 Rev 3 5/33
Symbol | Parameter | Conditions | Min. | Typ. | Max. | Unit |
∫en | Low-frequency peak-to- peak input noise | Bandwidth: f = 0.1 to 10 Hz | 9 | µVpp | ||
in | Equivalent input noise current | f = 100 Hz | 0.64 | fA/√Hz | ||
f = 1 kHz | 4.4 | |||||
trec | Overload recovery time | 100 mV from rail in comparator, RL = 100 kΩ, VID = ±VCC, -40 °C < T< 85 °C | 30 | µs |
Notes:
(1)Typical value is based on the Vio drift observed after 1000h at 125 °C extrapolated to 25 °C using the Arrhenius law and assuming an activation energy of 0.7 eV. The operational amplifier is aged in follower mode configuration.
(2)Guaranteed by design.
6/33 DocID024317 Rev 3
Table 4: Electrical characteristics at VCC+ = 3.3 V with VCC- = 0 V, Vicm = VCC/2, Tamb = 25 ° C, and RL = 1 MΩ connected to VCC/2 (unless otherwise specified)
Symbol | Parameter | Conditions | Min. | Typ. | Max. | Unit |
DC performance | ||||||
Vio | Input offset voltage | -3 | 0.1 | 3 | mV | |
-40 °C < T< 85 °C | -3.4 | 3.4 | ||||
ΔVio/ΔT | Input offset voltage drift | -40 °C < T< 85 °C | 5 | μV/°C | ||
ΔVio | Long-term input offset voltage drift | 0.36 | µV/ √month | |||
Iio | 1 | 5 | pA | |||
-40 °C < T< 85 °C | 30 | |||||
Iib | 1 | 5 | ||||
-40 °C < T< 85 °C | 30 | |||||
CMR | Common mode rejection ratio 20 log (ΔVicm/ΔVio) | Vicm = 0 to 2.1 V, Vout = VCC/2 | 70 | 92 | dB | |
-40 °C < T< 85 °C | 70 | |||||
Vicm = 0 to 3.3 V, Vout = VCC/2 | 60 | 77 | ||||
-40 °C < T< 85 °C | 60 | |||||
Avd | Large signal voltage gain | Vout = 0.3 V to ((VCC+) - 0.3 V), RL= 100 kΩ | 105 | 120 | ||
-40 °C < T< 85 °C | 105 | |||||
VOH | High level output voltage (drop from VCC+) | RL = 100 kΩ | 40 | mV | ||
-40 °C < T< 85 °C | 40 | |||||
VOL | Low level output voltage | RL = 100 kΩ | 40 | |||
-40 °C < T< 85 °C | 40 | |||||
Iout | Output sink current | Vout = VCC , VID = -200 mV | 6 | 9 | mA | |
-40 °C < T< 85 °C | 6 | |||||
Output source current | Vout = 0 V, VID = 200 mV | 8 | 11 | |||
-40 °C < T< 85 °C | 8 | |||||
ICC | Supply current, (per channel) | No load, Vout = VCC/2 | 600 | 800 | nA | |
-40 °C < T< 85 °C | 850 | |||||
AC performance | ||||||
GBP | Gain bandwidth product | RL = 1 MΩ, CL = 60 pF | 8 | kHz | ||
Fu | Unity gain frequency | 8 | ||||
ϕm | Phase margin | 60 | Degrees | |||
Gm | Gain margin | 11 | dB | |||
SR | Slew rate (10 % to 90 %) | RL = 1 MΩ, CL = 60 pF, Vout = 0.3 V to ((VCC+) - 0.3 V) | 3 | V/ms | ||
en | Equivalent input noise voltage | f = 100 Hz | 260 | nV/√Hz | ||
f = 1 kHz | 255 | |||||
∫en | Low-frequency peak-to- peak input noise | Bandwidth: f = 0.1 to 10 Hz | 8.6 | µVpp |
DocID024317 Rev 3 7/33
Symbol | Parameter | Conditions | Min. | Typ. | Max. | Unit |
in | Equivalent input noise current | f = 100 Hz | 0.55 | fA/√Hz | ||
f = 1 kHz | 3.8 | |||||
trec | Overload recovery time | 100 mV from rail in comparator, RL = 100 kΩ, VID = ±VCC, -40 °C < T< 85 °C | 30 | µs |
Notes:
(1)Typical value is based on the Vio drift observed after 1000h at 125 °C extrapolated to 25 °C using the Arrhenius law and assuming an activation energy of 0.7 eV. The operational amplifier is aged in follower mode configuration.
(2)Guaranteed by design.
8/33 DocID024317 Rev 3
Table 5: Electrical characteristics at VCC+ = 5 V with VCC- = 0 V, Vicm = VCC/2, Tamb = 25 ° C, and RL = 1 MΩ connected to VCC/2 (unless otherwise specified)
Symbol | Parameter | Conditions | Min. | Typ. | Max. | Unit |
DC performance | ||||||
Vio | Input offset voltage | -3 | 0.1 | 3 | mV | |
-40 °C < T< 85 °C | -3.4 | 3.4 | ||||
ΔVio/ΔT | Input offset voltage drift | -40 °C < T< 85 °C | 5 | μV/°C | ||
ΔVio | Long-term input offset voltage drift | 1.1 | µV/ √month | |||
Iio | 1 | 5 | pA | |||
-40 °C < T< 85 °C | 30 | |||||
Iib | 1 | 5 | ||||
-40 °C < T< 85 °C | 30 | |||||
CMR | Common mode rejection ratio 20 log (ΔVicm/ΔVio) | Vicm = 0 to 3.8 V, Vout = VCC/2 | 70 | 90 | dB | |
-40 °C < T< 85 °C | 70 | |||||
Vicm = 0 to 5 V, Vout = VCC/2 | 65 | 82 | ||||
-40 °C < T< 85 °C | 65 | |||||
SVR | Supply voltage rejection ratio | VCC = 1.5 to 5.5 V, Vicm = 0 V | 70 | 90 | ||
-40 °C < T< 85 °C | 70 | |||||
Avd | Large signal voltage gain | Vout = 0.3 V to ((Vcc+) - 0.3 V), RL= 100 kΩ | 110 | 130 | ||
-40 °C < T< 85 °C | 110 | |||||
VOH | High level output voltage, (drop from VCC+) | RL = 100 kΩ | 40 | mV | ||
-40 °C < T< 85 °C | 40 | |||||
VOL | Low level output voltage | RL = 100 kΩ | 40 | |||
-40 °C < T< 85 °C | 40 | |||||
Iout | Output sink current | Vout = VCC , VID = -200 mV | 6 | 9 | mA | |
-40 °C < T< 85 °C | 6 | |||||
Output source current | Vout = 0 V, VID = 200 mV | 8 | 11 | |||
-40 °C < T< 85 °C | 8 | |||||
ICC | Supply current, (per channel) | No load, Vout = VCC/2 | 650 | 850 | nA | |
-40 °C < T< 85 °C | 950 | |||||
AC performance | ||||||
GBP | Gain bandwidth product | RL = 1 MΩ, CL = 60 pF | 9 | kHz | ||
Fu | Unity gain frequency | 8.6 | ||||
ϕm | Phase margin | 60 | Degrees | |||
Gm | Gain margin | 12 | dB | |||
SR | Slew rate (10 % to 90 %) | RL = 1 MΩ, CL = 60 pF, Vout = 0.3 V to ((VCC+) - 0.3 V) | 3 | V/ms | ||
en | Equivalent input noise voltage | f = 100 Hz | 240 | nV√Hz | ||
f = 1 kHz | 225 |
DocID024317 Rev 3 9/33
Symbol | Parameter | Conditions | Min. | Typ. | Max. | Unit |
∫en | Low-frequency peak-to-peak input noise | Bandwidth: f = 0.1 to 10 Hz | 8.1 | µVpp | ||
in | Equivalent input noise current | f = 100 Hz | 0.18 | fA√Hz | ||
f = 1 kHz | 3.5 | |||||
trec | Overload recovery time | 100 mV from rail in comparator, RL = 100 kΩ, VID = ±VCC, -40 °C < T< 85 °C | 30 | µs | ||
EMIRR | Vin = -10 dBm, f = 400 MHz | 73 | dB | |||
Vin = -10 dBm, f = 900 MHz | 88 | |||||
Vin = -10 dBm, f = 1.8 GHz | 80 | |||||
Vin = -10 dBm, f = 2.4 GHz | 80 |
Notes:
(1)Typical value is based on the Vio drift observed after 1000h at 125 °C extrapolated to 25 °C using the Arrhenius law and assuming an activation energy of 0.7 eV. The operational amplifier is aged in follower mode configuration.
(2)Guaranteed by design.
(3)Based on evaluations performed only in conductive mode.
10/33 DocID024317 Rev 3
Figure 2: Supply current vs. supply voltage
Figure 3: Supply current vs. input common mode voltage
Figure 5: Input offset voltage distribution
Temperature 85°C/65°C/45°C/25°C/-5°C/-40°C | |||||||||||||||
Vcc=3.3V Follower configuration | |||||||||||||||
Input voltage (mV)
Figure 6: Input offset voltage vs common mode voltage
Figure 7: Input offset voltage vs temperature at 3.3 V supply voltage
Figure 4: Supply current in saturation mode
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0.0
Icc (µA)
0
25
50
75
100
125
150
175
3100
3125
3150
3175
3200
3225
3250
3275
3300
DocID024317 Rev 3 11/33
Vee=1.8 | V | |||||
Viem=Vee/2 | ||||||
- | ||||||
I |
Viol T (µV/'C)
Temperature ('C)
Figure 10: Input bias current vs. temperature at low VICM
2
Figure 11: Input bias current vs. temperature at high VICM
20 -
Figure 12: Output characteristics at 1.8 V supply voltage
1.8-
1.6
1.4
1.2
Figure 13: Output characteristics at 3.3 V supply voltage
3.3 - 3.0
2.7
> 2.4
-; 2.1
2 3 4 5 6 7 8 9 10
Output Current (mA)
O 0 . 9
0 . 6
0 . 3
0.0
0
1 . 2
-::S:,
::'. 1.5
1.8
:gC)
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
Output Current (mA}
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0
0.4
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-15
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-40 -20 0 20 40 60 80
Temperature ('C)
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Temperature ('C)
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Viem=Ve
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ee=5VI
Vee=3.3V
ee 5V
V
0-
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0-
20 40 60 80
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-15
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-40 -20 0
:i
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0-
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15
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c
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0
Figure 9: Input bias current vs. temperature at mid VICM
20-
1 2
0
,■
-3 -2 -1
5
07
-5 -4
10
0
ll.
C.
:i
15
C:
0
20
t:,.Vio/t:,T. distribution between T=-40' C and 85' C for Vee=3.3V, Viem=1.65V
25
Figure 8: Input offset voltage temperature coefficient distribution
30
12/33 DocID024317 Rev 3
Figure 14: Output characteristics at 5 V supply voltage
Vcc=3.3V Follower configuration | |||||||||||||||
Figure 16: Output saturation with a sine wave on input
Figure 18: Phase reversal free
Figure 19: Slew rate vs. supply voltage
Figure 15: Output voltage vs. input voltage close to the rails
3300
3275
3250
3225
3200
3175
3150
3125
3100
175
150
125
100
75
50
25
0
Input voltage (mV)
Output voltage (mV)
0
25
50
75
100
125
150
175
3100
3125
3150
3175
3200
3225
3250
3275
3300
DocID024317 Rev 3 13/33
Figure 20: Output swing vs. input signal frequency
4.0-
3.5-
Figure 21: Triangulation of a sine wave
3-
Follower configuration, Vin=3Vpp, F=1kHz
2-
Figure 22: Large signal response at 3.3 V supply voltage
Figure 23: Small signal response at 3.3 V supply voltage
Figure 25: Phase margin vs. capacitive load at 3.3 V supply voltage
Vcc=3.3V, Vicm=Vrl=1 65V Follower configuration 50mVpp step Rl=10MO, T=25°C | ||||
0- | ||||
5- | ||||
0- | ||||
0- | |||||
0- | |||||
- | |||||
- | Vcc=3.3V, Vicm=Vrl=1.65V Gain 101 : Rg=10k0 , Rf=1MQ Rl=10MQ T=25°C | ||||
- | |||||
- | |||||
I I
50 100 150 200 250
Capacitive load (pF)
5: 25
f"' 2 0
15
10
5
0 L
0
45
7
65
6
55
°gi 50-
a, 4 0
:. 35
E 30
Figure 24: Overshoot vs. capacitive load at 3.3 V supply voltage
30-
28
25-
23
l 2
0 18
0
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I!? 13
0 1
8
5-
3
0L I
0 50 100 150 200
Capacitive load (pF)
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_§_ 15
10
5
Q. 0
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§, -15
iii -20
-25
-30 -
_3 5 ,
0.0 0.1 0 . 2 0.3 0.4 0.5 0 . 6 0 . 7 0 . 8 0 . 9 1 . 0
Time(ms)
Follower configuration, T=25°C
35
30-
25
2 3 4 5 6 7 8 9 10
Time (ms)
0
Q. 0
E
<(
iii
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iii
-2- Rl=10MO, Cl=16pF
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Follower configuration, T=25
2-
°C
4
3
2
Time (ms)
-3L 0
Vcc=3.3V , Vicm=Vrl=1 .65V Rl=10MO , Cl=16pF , T=25 ° C
E
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-1 -
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-2-
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Frequency (Hz)
10000
1000
100
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5"5 1.
0 1.
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10
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>
I
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0-
p
Follower configuration Vcc=3 .3V, Vin=3.3Vp
Vicm=Vrl=1 65V Rl=10MQ, Cl=16pF T=25°C
14/33 DocID024317 Rev 3
100
1000
Frequency (Hz)
10000
100
1000
Frequency (Hz)
Figure 28: Bode diagram at 3.3 V supply voltage
45
30
15
Figure 29: Bode diagram at 5 V supply voltage
45
30
15
CJ
C
"cij
C)
0
CJ
C
' cij
C)
0
-15
-30
-457
10
-120
-150
-180
Figure 31: In-series resistor (Riso) vs. capacitive load
::c:
Vcc=3.3V, Vicm=Vrl Gain 101: Rg=10kO, Rf=1MO Rl=10MO, Cl=60pF T=25°C Measured at 20dB | ||||||
L |
100 -
Capacitive load (nF)
,I
1o'
,I
1(f
" 1
10
,I
1d'
,I
1IT'
Recommended resistor to place between the output of the op amp and the capacitive load Vcc=3.3V, Vicm=1 65V
Follower configuration
0
1/)
ii:
a
=-
O
0 .0 0 .5 1.0 1.5 2.0 2.5 3.0
Vicm (V)
5
4-
3
2-
0..
Cll
(.')
N 6-
Figure 30: Gain bandwidth product vs. input common mode voltage
10-
9
8 -
7
10000
1000
Frequency (Hz)
100
-120
-150
-180
-15
-30
-457
10
Q)
-30
0..
-60
-90
en
180
150
120
90
60
30 0
0
10000
1000
Frequency (Hz)
100
Q)
-30
0..
-60
-90
en
180
150
120
90
60
30 0
0
180
150
120
90
60
30
0 eQn)
-30
0..
-60
-90
-120
-150
-180
10000
Figure 27: Bode diagram at 1.8 V supply voltage
45
3 0
15
-15-
-30
C 0
'cij
C) -5
-10
-15
\
15
10 Vcc=3.3V, Vicm=l.65V, T=25°C
Gain=l
CJ 5 Rl=lOMQ, Cl=16pF, Vrl=Vcc/2
Figure 26: Bode diagram for different feedback values
20
Feedback : lO0kQ
/
Feedback: 1MQ/ /47pF
Feedback: lMQ
DocID024317 Rev 3 15/33
Figure 32: Noise at 1.8 V supply voltage in follower configuration
Figure 33: Noise at 3.3 V supply voltage in follower configuration
., 10000 ., 10000
J: J:
Vcc=1.8V Vcc=3.3V
.>s
Follower configuration
.s Follower configuration
z, T=25°C z, T=25°C
Vicm=1 65V
C: C:
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0
0
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2 3 4 5 6 7 8 9 10
Time (s)
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0
z
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0
5
Q.
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Figure 35: Noise amplitude on 0.1 to 10 Hz frequency range
20-
15
I
10000 100000
1000
Frequency (Hz)
100
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10
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0
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z,
.s
Figure 34: Noise at 5 V supply voltage in follower configuration
.,10000
J:
Vcc=5V Fol ower configuration T=25°C | ||||||||||||||||||||
0- | ||||||||||||||||||||
Vicm=2.5V | ||||||||||||||||||||
0- | I | |||||||||||||||||||
Vicm=4 7V | ||||||||||||||||||||
I | I |
Vcc=3V, Vicm=1.65V Bandpass filter : 0.1Hz to 1OHz T=25°C | |||||||||
0L | |||||||||
10 | 100 | 1000 | 10000 | 100000 | 10 | 100 | 1000 | 10000 | 100000 |
Frequency (Hz) | Frequency (Hz) |
0 10L 0 10
Figure 36: Channel separation on TSU102
140-
Figure 37: Channel separation on TSU104
140-
iii"
120-
iii"
120-
Ch1 -Ch2
Ch1 Ch3
Ch1 -Ch4
0
100-
C:
100-
E 80-
C.
E
80-
."t::':
60-
V =5V
v:m=2.5V V,,=2Vpp T=25°C
Cl)
a"i'
60-
Frequency (Hz)
Frequency (Hz)
10k
1k
100
20-
0L
10
."t::':
(J
40-
C:
C:
"C.'
0
:;::;
I
10k
1k
100
20-
OL 10
(J
40-
C
C:
Cl)
a"i'
"'
:;::;
C
I
I
V =5V V""'=2.5V V,,=2Vpp T=25°C
16/33 DocID024317 Rev 3
The TSU101, TSU102, and TSU104 series of amplifiers can operate from 1.5 V to 5.5 V. Their parameters are fully specified at 1.8 V, 3.3 V, and 5 V supply voltages and are very stable in the full VCC range. Additionally, main specifications are guaranteed on the industrial temperature range from -40 to 85 ° C.
The TSU101, TSU102, and TSU104 series is built with two complementary PMOS and NMOS input differential pairs. Thus, these devices have a rail-to-rail input, and the input common mode range is extended from (VCC-) - 0.1 V to (VCC+) + 0.1 V.
The devices have been designed to prevent phase reversal behavior.
Input offset voltage drift over temperature
The maximum input voltage drift over the temperature variation is defined as the offset variation related to the offset value measured at 25 °C. The operational amplifier is one of the main circuits of the signal conditioning chain, and the amplifier input offset is a major contributor to the chain accuracy. The signal chain accuracy at 25 °C can be compensated during production at application level. The maximum input voltage drift over temperature enables the system designer to anticipate the effects of temperature variations.
The maximum input voltage drift over temperature is computed using Equation 1.
Equation 1
∆Vio = ma x VioT – Vio25 °C
∆T T – 25 °C
with T = -40 °C and 85 °C.
The datasheet maximum value is guaranteed by measurements on a representative sample size ensuring a Cpk (process capability index) greater than 2.
DocID024317 Rev 3 17/33
Long term input offset voltage drift
To evaluate product reliability, two types of stress acceleration are used:
Voltage acceleration, by changing the applied voltage
Temperature acceleration, by changing the die temperature (below the maximum junction temperature allowed by the technology) with the ambient temperature.
The voltage acceleration has been defined based on JEDEC results, and is defined using
Equation 2
FV
A = eβ . VS – VU
Where:
AFV is the voltage acceleration factor
b is the voltage acceleration constant in 1/V, constant technology parameter (β = 1) VS is the stress voltage used for the accelerated test
VU is the voltage used for the application
The temperature acceleration is driven by the Arrhenius model, and is defined in
Equation 3
AFT
E
a .
-----
k
= e
1 – 1
TU TS
Where:
AFT is the temperature acceleration factor
Ea is the activation energy of the technology based on the failure rate k is the Boltzmann constant (8.6173 x 10-5 eVk-1)
TU is the temperature of the die when VU is used (°K)
TS is the temperature of the die under temperature stress (°K)
Equation 4
AF = AFT × AFV
AF is calculated using the temperature and voltage defined in the mission profile of the product. The AF value can then be used in Equation 5 to calculate the number of months of use equivalent to 1000 hours of reliable stress duration.
Equation 5
Months = AF × 1000 h × 12 months / 24 h × 365.25 days
18/33 DocID024317 Rev 3
To evaluate the op-amp reliability, a follower stress condition is used where VCC is defined as a function of the maximum operating voltage and the absolute maximum rating (as recommended by JEDEC rules).
Equation 6
VCC = maxVop with Vicm = VCC / 2
Equation 7
∆Vio =
Viodrift
month s
where Vio drift is the measured drift value in the specified test conditions after 1000 h stress duration.
Schematic optimization aiming for nanopower
To benefit from the full performance of the TSU10 series, the impedances must be maximized so that current consumption is not lost where it is not required.
For example, an aluminum electrolytic capacitance can have significantly high leakage. This leakage may be greater than the current consumption of the op-amp. For this reason, ceramic type capacitors are preferred.
For the same reason, big resistor values should be used in the feedback loop. However, there are three main limitations to be considered when choosing a resistor.
When the TSU10x series is used with a sensor: the resistance connected between the sensor and the input must remain much higher than the impedance of the sensor itself.
Noise generated: a 100 kΩ resistor generates 40 nV/√Hz, a bigger resistor value generates even more noise.
Leakage on the PCB: leakage can be generated by moisture. This can be improved by using a specific coating process on the PCB.
DocID024317 Rev 3 19/33
For correct operation, it is advised to add 10 nF decoupling capacitors as close as possible to the power supply pins.
Minimizing the leakage from sensitive high impedance nodes on the inputs of the TSU10x series can be performed with a guarding technique. The technique consists of surrounding high impedance tracks by a low impedance track (the ring). The ring is at the same electrical potential as the high impedance node.
Therefore, even if some parasitic impedance exists between the tracks, no leakage current can flow through them as they are at the same potential (see Figure 38: "Guarding on the PCB").
Figure 38: Guarding on the PCB
Using the TSU10x series with sensors
The TSU10x series has MOS inputs, thus input bias currents can be guaranteed down to
pA maximum at ambient temperature. This is an important parameter when the operational amplifier is used in combination with high impedance sensors.
The TSU101, TSU102, and TSU104 series is perfectly suited for trans-impedance configuration as shown in Figure 39: "Trans-impedance amplifier schematic". This configuration allows a current to be converted into a voltage value with a gain set by the user. It is an ideal choice for portable electrochemical gas sensing or photo/UV sensing applications. The TSU10x series, using trans-impedance configuration, is able to provide a voltage value based on the physical parameter sensed by the sensor.
20/33 DocID024317 Rev 3
Electrochemical gas sensors
The output current of electrochemical gas sensors is generally in the range of tens of nA to hundreds of µA. As the input bias current of the TSU101, TSU102, and TSU104 is very low (see Figure 9, Figure 10, and Figure 11) compared to these current values, the TSU10x series is well adapted for use with the electrochemical sensors of two or three electrodes. Figure 40: "Potentiostat schematic using the TSU101 (or TSU102)" shows a potentiostat (electronic hardware required to control a three-electrode cell) schematic using the TSU101, TSU102, and TSU104. In such a configuration, the devices minimize leakage in the reference electrode compared to the current being measured on the working electrode.
Figure 39: Trans-impedance amplifier schematic
Figure 40: Potentiostat schematic using the TSU101 (or TSU102)
DocID024317 Rev 3 21/33
When the TSU101, TSU102, and TSU104 operational amplifiers go into saturation mode, they take a short period of time to recover, typically thirty microseconds. When recovering after saturation, the TSU10x series does not exhibit any voltage peaks that could generate issues (such as false alarms) in the application (see Figure 17). This is because the internal gain of the amplifier decreases smoothly when the output signal gets close to the VCC+ or VCC- supply rails (see Figure 15 and Figure 16).
Thus, to maintain signal integrity, the user should take care that the output signal stays at 100 mV from the supply rails.
With a trans-impedance schematic, a voltage reference can be used to keep the signal away from the supply rails.
Using the TSU10x series in comparator mode
The TSU10x series can be used as a comparator. In this case, the output stage of the device always operates in saturation mode. In addition, Figure 4 shows the current consumption is not bigger and even decreases smoothly close to the rails. The TSU101, TSU102, and TSU104 are obviously operational amplifiers and are therefore optimized to be used in linear mode. We recommend to use the TS88 series of nanopower comparators if the primary function is to perform a signal comparison only.
ESD structure of TSU10x series
The TSU101, TSU102, and TSU104 are protected against electrostatic discharge (ESD) with dedicated diodes (see Figure 41: "ESD structure"). These diodes must be considered at application level especially when signals applied on the input pins go beyond the power supply rails (VCC+ or VCC-).
Current through the diodes must be limited to a maximum of 10 mA as stated in Table 1: "Absolute maximum ratings (AMR)". A serial resistor or a Schottky diode can be used on the inputs to improve protection but the 10 mA limit of input current must be strictly observed.
22/33 DocID024317 Rev 3
In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark.
DocID024317 Rev 3 23/33
SC70-5 (or SOT323-5) package information
Figure 42: SC70-5 (or SOT323-5) package outline
SIDE VIEW
DIMENSIONS IN MM
GAUGE PLANE
COPLANAR LEADS
SEATING PLANE
TOP VIEW
Table 6: SC70-5 (or SOT323-5) mechanical data
Ref. | Dimensions | |||||
Millimeters | Inches | |||||
Min. | Typ. | Max. | Min. | Typ. | Max. | |
A | 0.80 | 1.10 | 0.315 | 0.043 | ||
A1 | 0.10 | 0.004 | ||||
A2 | 0.80 | 0.90 | 1.00 | 0.315 | 0.035 | 0.039 |
b | 0.15 | 0.30 | 0.006 | 0.012 | ||
c | 0.10 | 0.22 | 0.004 | 0.009 | ||
D | 1.80 | 2.00 | 2.20 | 0.071 | 0.079 | 0.087 |
E | 1.80 | 2.10 | 2.40 | 0.071 | 0.083 | 0.094 |
E1 | 1.15 | 1.25 | 1.35 | 0.045 | 0.049 | 0.053 |
e | 0.65 | 0.025 | ||||
e1 | 1.30 | 0.051 | ||||
L | 0.26 | 0.36 | 0.46 | 0.010 | 0.014 | 0.018 |
< | 0° | 8° | 0° | 8° |
24/33 DocID024317 Rev 3
Figure 43: SOT23-5 package outline
Table 7: SOT23-5 mechanical data
Ref. | Dimensions | |||||
Millimeters | Inches | |||||
Min. | Typ. | Max. | Min. | Typ. | Max. | |
A | 0.90 | 1.20 | 1.45 | 0.035 | 0.047 | 0.057 |
A1 | 0.15 | 0.006 | ||||
A2 | 0.90 | 1.05 | 1.30 | 0.035 | 0.041 | 0.051 |
B | 0.35 | 0.40 | 0.50 | 0.014 | 0.016 | 0.020 |
C | 0.09 | 0.15 | 0.20 | 0.004 | 0.006 | 0.008 |
D | 2.80 | 2.90 | 3.00 | 0.110 | 0.114 | 0.118 |
D1 | 1.90 | 0.075 | ||||
e | 0.95 | 0.037 | ||||
E | 2.60 | 2.80 | 3.00 | 0.102 | 0.110 | 0.118 |
F | 1.50 | 1.60 | 1.75 | 0.059 | 0.063 | 0.069 |
L | 0.10 | 0.35 | 0.60 | 0.004 | 0.014 | 0.024 |
K | 0 degrees | 10 degrees | 0 degrees | 10 degrees |
DocID024317 Rev 3 25/33
Figure 44: DFN8 2x2 package outline
Table 8: DFN8 2x2 mechanical data
Ref. | Dimensions | |||||
Millimeters | Inches | |||||
Min. | Typ. | Max. | Min. | Typ. | Max. | |
A | 0.70 | 0.75 | 0.80 | 0.028 | 0.030 | 0.031 |
A1 | 0.00 | 0.02 | 0.05 | 0.000 | 0.001 | 0.002 |
b | 0.15 | 0.20 | 0.25 | 0.006 | 0.008 | 0.010 |
D | 2.00 | 0.079 | ||||
E | 2.00 | 0.079 | ||||
e | 0.50 | 0.020 | ||||
L | 0.045 | 0.55 | 0.65 | 0.018 | 0.022 | 0.026 |
N | 8 |
26/33 DocID024317 Rev 3
Figure 45: MiniSO8 package outline
Table 9: MiniSO8 mechanical data
Ref. | Dimensions | |||||
Millimeters | Inches | |||||
Min. | Typ. | Max. | Min. | Typ. | Max. | |
A | 1.1 | 0.043 | ||||
A1 | 0 | 0.15 | 0 | 0.006 | ||
A2 | 0.75 | 0.85 | 0.95 | 0.030 | 0.033 | 0.037 |
b | 0.22 | 0.40 | 0.009 | 0.016 | ||
c | 0.08 | 0.23 | 0.003 | 0.009 | ||
D | 2.80 | 3.00 | 3.20 | 0.11 | 0.118 | 0.126 |
E | 4.65 | 4.90 | 5.15 | 0.183 | 0.193 | 0.203 |
E1 | 2.80 | 3.00 | 3.10 | 0.11 | 0.118 | 0.122 |
e | 0.65 | 0.026 | ||||
L | 0.40 | 0.60 | 0.80 | 0.016 | 0.024 | 0.031 |
L1 | 0.95 | 0.037 | ||||
L2 | 0.25 | 0.010 | ||||
k | 0° | 8° | 0° | 8° | ||
ccc | 0.10 | 0.004 |
DocID024317 Rev 3 27/33
QFN16 3x3 package information
Figure 46: QFN16 3x3 mm package outline
The exposed pad is not internally connected and can be set to ground.
28/33 DocID024317 Rev 3
Table 10: QFN16 3x3 mm mechanical data
Ref. | Dimensions | |||||
Millimeters | Inches | |||||
Min. | Typ. | Max. | Min. | Typ. | Max. | |
A | 0.80 | 0.90 | 1.00 | 0.031 | 0.035 | 0.039 |
A1 | 0 | 0.05 | 0 | 0.002 | ||
A3 | 0.20 | 0.008 | ||||
b | 0.18 | 0.30 | 0.007 | 0.012 | ||
D | 2.90 | 3.00 | 3.10 | 0.114 | 0.118 | 0.122 |
D2 | 1.50 | 1.80 | 0.059 | 0.071 | ||
E | 2.90 | 3.00 | 3.10 | 0.114 | 0.118 | 0.122 |
E2 | 1.50 | 1.80 | 0.059 | 0.071 | ||
e | 0.50 | 0.020 | ||||
L | 0.30 | 0.50 | 0.012 | 0.020 |
Figure 47: QFN16 3x3 mm recommended footprint
DocID024317 Rev 3 29/33
Figure 48: TSSOP14 package outline
Table 11: TSSOP14 mechanical data
Ref. | Dimensions | |||||
Millimeters | Inches | |||||
Min. | Typ. | Max. | Min. | Typ. | Max. | |
A | 1.20 | 0.047 | ||||
A1 | 0.05 | 0.15 | 0.002 | 0.004 | 0.006 | |
A2 | 0.80 | 1.00 | 1.05 | 0.031 | 0.039 | 0.041 |
b | 0.19 | 0.30 | 0.007 | 0.012 | ||
c | 0.09 | 0.20 | 0.004 | 0.0089 | ||
D | 4.90 | 5.00 | 5.10 | 0.193 | 0.197 | 0.201 |
E | 6.20 | 6.40 | 6.60 | 0.244 | 0.252 | 0.260 |
E1 | 4.30 | 4.40 | 4.50 | 0.169 | 0.173 | 0.176 |
e | 0.65 | 0.0256 | ||||
L | 0.45 | 0.60 | 0.75 | 0.018 | 0.024 | 0.030 |
L1 | 1.00 | 0.039 | ||||
k | 0° | 8° | 0° | 8° | ||
aaa | 0.10 | 0.004 |
30/33 DocID024317 Rev 3
Table 12: Order codes
Order code | Temperature range | Package | Packing | Marking |
TSU101ICT | -40 °C to 85 °C | SC70-5 | Tape and reel | K22 |
TSU101ILT | SΟΤ23-5 | K160 | ||
TSU101RICT | SC70-5 | K24 | ||
TSU101RILT | SΟΤ23-5 | K169 | ||
TSU102IQ2T | DFN8 2x2 | K24 | ||
TSU102IST | MiniSO8 | K160 | ||
TSU104IQ4T | QFN16 3x3 | K160 | ||
TSU104IPT | TSSOP14 | TSU104I |
DocID024317 Rev 3 31/33
Table 13: Document revision history
Date | Revision | Changes |
16-Apr-2013 | 1 | Initial release |
02-Jul-2013 | 2 | Added the TSU102 and TSU104 devices and updated the datasheet accordingly. Added the silhouettes, pin connections, and package information for DFN8 2x2, MiniSO8, QFN16 3x3, and TSSOP14. |
04-Sep-2015 | 3 | Replaced QFN16 3x3 package information (outline, mechanical data, and footprint). |
32/33 DocID024317 Rev 3
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DocID024317 Rev 3 33/33
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