NCS21911, NCV21911, NCS21912, NCV21912, NCS21914, NCV21914


Precision Operational Amplifier, 25 µV Offset, Zero-Drift, 36 V Supply, 2 MHz

The NCS2191x family of high precision op amps feature low input offset voltage and near−zero drift over time and temperature. These op amps operate over a wide supply range from 4 V to 36 V with low quiescent current. The rail−to−rail output swings within 10 mV of the rails. The family includes the single channel NCS(V)21911, the dual channel NCS(V)21912, and the quad channel NCS(V)21914 in a variety of packages. All versions are specified for operation from

−40C to +125C. Automotive qualified options are available under

the NCV prefix.


www.onsemi.com


MARKING DIAGRAMS




AEZAYW■






5 5

1

TSOP5

CASE 483 1

8

XXXX

8

AYW■

1

Micro8

Features

XXXXX = Specific Device Code A = Assembly Location

L or WL = Wafer Lot Y = Year

W = Work Week

■ = PbFree Package

(Note: Microdot may be in either location)


ORDERING INFORMATION

See detailed ordering and shipping information on page 2 of this data sheet.


Semiconductor Components Industries, LLC, 2013

July, 2019 Rev. 1

1 Publication Order Number:

NCS21911/D


PIN CONNECTIONS

Single Channel Configuration

NCS21911


4

3

2

5

1

OUT VSS

VDD

IN+ IN


Dual Channel Configuration

NCS21912

Quad Channel Configuration

NCS21914


OUT 1 1


IN1 2

IN+ 1 3


VSS 4


8


7

+ 6

+ 5


VDD OUT 2

IN2


IN+ 2


OUT 1 1


IN1 2

IN+ 1 3 +

VDD 4


14


13

+ 12


11


OUT 4


IN4


IN+ 4 VSS

IN+ 2 5

+ + 10

IN+ 3

IN2 6

OUT 2 7

9 IN3

8 OUT 3


ORDERING INFORMATION

Channels

Device

Package

Shipping †

Single

NCS21911SN2T1G

SOT235 / TSOP5

3000 / Tape & Reel

Dual

NCS21912DR2G

(In Development*)

SOIC8

2500 / Tape & Reel

NCS21912DMR2G

(In Development*)

MICRO8

4000 / Tape & Reel

Quad

NCS21914DR2G

(In Development*)

SOIC14

2500 / Tape & Reel

NCS21914DBR2G

(In Development*)

TSSOP14

2500 / Tape & Reel

Automotive Qualified

Channels

Device

Package

Shipping

Single

NCV21911SN2T1G

SOT235 / TSOP5

3000 / Tape & Reel

Dual

NCV21912DR2G

(In Development*)

SOIC8

2500 / Tape & Reel

NCV21912DMR2G

(In Development*)

MICRO8

4000 / Tape & Reel

Quad

NCV21914DR2G

(In Development*)

SOIC14

2500 / Tape & Reel

NCV21914DBR2G

(In Development*)

TSSOP14

2500 / Tape & Reel

†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD8011/D.

*Contact local sales office for more information.


ABSOLUTE MAXIMUM RATINGS

Parameter

Rating

Unit

Supply Voltage (VDDVSS)

40

V

INPUT AND OUTPUT PINS


Input Voltage (Note 1)

VSS – 0.3 to VDD + 0.3

V

Differential Input Voltage (Note 2)

17

V

Input Current (Notes 1 and 2)

10

mA

Output Short Circuit Current (Note 3)

Continuous

mA

TEMPERATURE


Operating Temperature

–40 to +125

C

Storage Temperature

–65 to +150

C

Junction Temperature

+150

C

ESD RATINGS (Note 4)


Human Body Model (HBM)

3000

V

Charged Device Model (CDM)

2000

V

OTHER RATINGS


Latchup Current (Note 5)

100

mA

MSL

Level 1


Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected.

  1. Input terminals are diodeclamped to the powersupply rails. Input signals that can swing more than 0.3 V beyond the supply rails should be current limited to 10 mA or less.

  2. The inputs are diode connected with a total input protection of 1.65 kQ, increasing the absolute maximum differential voltage to 17 VDC. If the applied differential voltage is expected to exceed this rating, external resistors should be added in series with the inputs to limit the input current to 10 mA.

  3. Shortcircuit to VDD or VSS. Short circuits to either rail can cause an increase in the junction temperature. The total power dissipation must be limited to prevent the junction temperature from exceeding the 150°C limit.

  4. This device series incorporates ESD protection and is tested by the following methods: ESD Human Body Model tested per JEDEC standard JS0012017 (AECQ100002) ESD Charged Device Model tested per JEDEC standard JS0022014 (AECQ100011)

  5. Latchup Current tested per JEDEC standard JESD78E (AECQ100004).


    THERMAL INFORMATION (Note 6)

    Rating

    Symbol

    Package

    Value

    Unit

    Thermal Resistance, Junction to Ambient

    8JA

    TSOP5 / SOT235

    170

    Micro8/MSOP8

    TBD

    SOIC8

    TBD

    SOIC14

    TBD

    TSSOP14

    TBD

  6. As mounted on an 80x80x1.5 mm FR4 PCB with 2S2P, 2 oz copper, and a 200 mm2 heat spreader area. Following JEDEC JESD517 guidelines.


    OPERATING CONDITIONS

    Parameter

    Symbol

    Range

    Unit

    Supply Voltage (VDD VSS)

    VS

    4 to 36

    V

    Specified Operating Temperature Range

    TA

    40 to 125

    C

    Input Common Mode Voltage Range

    VCM

    VSS to VDD1.5

    V

    Differential Voltage (Note 7)

    VDIFF

    17

    V

  7. The inputs are diode connected with a total input protection of 1.65 kQ, increasing the absolute maximum differential voltage to 17 VDC. If the applied differential voltage is expected to exceed this rating, external resistors should be added in series with the inputs to limit the input current to 10 mA.


    Parameter

    Symbol

    Conditions

    Min

    Typ

    Max

    Unit

    INPUT CHARACTERISTICS


    Offset Voltage

    VOS



    1

    25

    µV

    Offset Voltage Drift vs Temp

    !). VOS/!). T



    0.02

    0.085

    µV/C

    Input Bias Current

    IIB



    100

    500

    pA




    3500

    pA

    Input Offset Current

    IOS



    200

    500

    pA




    3500

    pA

    Common Mode Rejection Ratio

    CMRR

    VSS VCM

    VDD1.5 V

    VS = 36 V

    140

    150


    dB

    130



    VS = 12 V

    (Note 8)

    130

    150


    120



    VS = 8 V

    (Note 8)

    130

    140


    120



    VS = 4 V

    120

    130


    110



    Input Capacitance

    CIN

    Common Mode


    3


    pF

    EMI Rejection Ratio

    EMIRR

    f = 5 GHz


    100


    dB

    f = 400 MHz


    80


    OUTPUT CHARACTERISTICS


    Open Loop Voltage Gain

    AVOL

    VSS + 0.5 V VO VDD – 0.5 V

    130

    150


    dB

    125

    135


    Open Loop Output Impedance

    ZOUT_OL

    No Load


    See Figure 23


    Q

    Output Voltage High, Referenced to Rail

    VOH

    No Load


    5

    10

    mV

    RL = 10 kQ


    100

    210


    140

    250

    Output Voltage Low, Referenced to Rail

    VOL

    No Load


    5

    10

    mV

    RL = 10 kQ


    100

    210


    140

    250

    Short Circuit Current

    ISC

    Sinking Current


    18


    mA

    Sourcing Current


    16


    Capacitive Load Drive

    CL



    1


    nF

    DYNAMIC PERFORMANCE


    Gain Bandwidth Product

    GBW

    CL = 100 pF


    2


    MHz

    Gain Margin

    AM

    CL = 100 pF


    13


    dB

    Phase Margin

    M

    CL = 100 pF


    55


    Slew Rate

    SR

    G = +1


    1.6


    V/µs

    Settling Time

    tS

    VS = 36 V

    0.1%


    20


    µs

    0.01%


    45


    µs

    Overload Recovery Time

    tOR

    VS = 18 V, AV = 10, VIN = 2.5 V


    1


    µs

  8. Guaranteed by characterization and/or design.


Parameter

Symbol

Conditions

Min

Typ

Max

Unit

NOISE PERFORMANCE


Total Harmonic Distortion + Noise

THD+N

fIN = 1 kHz, AV = 1, VOUT = 1

Vrms


0.0003


%

Voltage Noise Density

eN

f = 1 kHz


22


nV/Hz

Current Noise Density

iN

f = 1 kHz


100


fA/Hz

Voltage Noise, PeaktoPeak

ePP

f = 0.1 Hz to 10 Hz


400


nVPP

Voltage Noise, RMS

erms

f = 0.1 Hz to 10 Hz


70


nVrms

POWER SUPPLY


Power Supply Rejection Ratio

PSRR

VS = 4 V to 36 V


0.02

0.3

µV/V

130

154


dB

Quiescent Current

IQ

Per channel


475

570

µA



570


GRAPHS

Typical performance at TA = 25C, unless otherwise noted.


35

VS = 36 V

NUMBER OF AMPLIFIERS

30 VCM = midsupply 105 units

25


20


15


10


5


0

16

VS = 36 V

NUMBER OF AMPLIFIERS

14 VCM = midsupply

12 105 units 10

8

6


4


2


0

20 16 12 8 4 0 4 8 12 16 20

OFFSET VOLTAGE (µV)

0.10 0.06 0.02 0.02 0.06 0.10

OFFSET VOLTAGE DRIFT (µV/C)

Figure 1. Offset Voltage Distribution Figure 2. Offset Voltage Drift Distribution



15


OFFSET VOLTAGE (V)

10


5


0


5


10


VS = 36 V

VCM = midsupply 5 typical units


15


OFFSET VOLTAGE (V)






VS = 4 V

5 typical units
















































10


5


0


5


10


15

50 25 0 25 50 75 100 125

TEMPERATURE (C)

15


0 0.5 1 1.5 2 2.5 3

COMMON MODE VOLTAGE (V)

Figure 3. Offset Voltage vs. Temperature Figure 4. Offset Voltage vs. Common Mode

Voltage








VCM = midsupply 5 typical units









































15 15

VS = 36 V

OFFSET VOLTAGE (V)

OFFSET VOLTAGE (V)

10 5 typical units 10


5 5


0 0


5 5


10


15

0 5 10 15 20 25 30 35

10


15

4 8 12 16 20 24 28 32 36

COMMON MODE VOLTAGE (V) SUPPLY VOLTAGE (V)

Figure 5. Offset Voltage vs. Common Mode Voltage

Figure 6. Offset Voltage vs. Power Supply


GAIN (dB) AND PHASE MARGIN ()

120


100


80


60


40


20


0

25






























































PHASE MARGIN
























































































GAIN





















































































































VS = 4 V, 36 V RL = 10 kQ




















































20

15

GAIN (dB)

10

5

0

5

10

15


AV = 1

AV = 1

AV = 10


VS = 36 V RL = 10 kQ CL = 25 pF

20

20

10 1k 100k 10M 10k 100k 1M 10M FREQUENCY (Hz) FREQUENCY (Hz)

Figure 7. Open Loop Gain and Phase vs.

Frequency

Figure 8. Closed Loop Gain vs. Frequency



300


INPUT CURRENT (pA)

200


100


0


100


200


300


IIB+

IIBIOS


VS = 36 V


1600


INPUT CURRENT (pA)

1200


800


400


0


400


IIB+

VS = 36 V

VCM = midsupply

IIBIOS

0 5 10 15 20 25 30 35 40 20 0 20 40 60 80 100 120 140

COMMON MODE VOLTAGE (V) TEMPERATURE (C)

Figure 9. Input Current vs. Common Mode Voltage

Figure 10. Input Current vs. Temperature



POWER SUPPLY REJECTION (dB)

140


120


100


80


60


40


20


0


PSRR


VS = 2, PSRR+

VS = 18, PSRR+ VS = 2, PSRRVS = 18, PSRR


RL = 10 kQ


PSRR+


120


COMMON MODE REJECTION (dB)

100


80


60


40


20


0


VS = 4 V, 36 V RL = 10 kQ

10 100

1k 10k

100k 1M

10 100

1k 10k

100k 1M

FREQUENCY (Hz) FREQUENCY (Hz)

Figure 11. PSRR vs. Frequency Figure 12. CMRR vs. Frequency



0.5

0.4


VS = 4 V, 36 V

5

4.5 VCM = VSS+0.5 to VDD1.5 V


0.3

PSRR (µV/V)

0.2

0.1

0

0.1

0.2

0.3

0.4

0.5

5 typical units

4

3.5

CMRR (µV/V)

3

2.5

2

1.5

1

0.5

0

0.5

VCM = VSS to VDD1.5 V

50

25 0

25 50

75 100

125 150

50

25 0

25 50

75 100

125 150

TEMPERATURE (C) TEMPERATURE (C)

Figure 13. PSRR vs. Temperature Figure 14. CMRR vs. Temperature at VS = 4 V



2

1.8

1.6

1.4

CMRR (µV/V)

1.2

1

0.8

0.6

0.4

0.2

0

0.2

0.4


VCM = VSS+0.5 to VDD1.5 V VCM = VSS to VDD1.5 V


400



VS = 36 V




















































































































































300


VOLTAGE (nV)

200


100


0


100

200

300

400

50

25 0 25 50 75 100

125 150

0 1 2 3 4

5 6 7

8 9 10

TEMPERATURE (C) TIME (s)

Figure 15. CMRR vs. Temperature at VS = 36 V Figure 16. 0.1 Hz to 10 Hz Noise


VOLTAGE NOISE (nV/Hz)


















VS

=

6










































































































































































































































































































































1k 3 V


100


10


0.01


THD + N (%)

0.001


VS = 36 V RL = 10 kQ BW = 80 kHz

VIN = 1 Vrms


AV = 1

AV = 1



1

1 10


100


1k 10k 100k


0.0001

10


100 1k


10k

FREQUENCY (Hz) FREQUENCY (Hz)

Figure 17. Voltage Noise Density vs.

Frequency

Figure 18. THD+N vs. Frequency



10


1


THD + N (%)

0.1


0.01


0.001


0.0001


VS = 36 V RL = 10 kQ BW = 80 kHz

f = 1 kHz


AV = 1

AV = 1

0.50

QUIESCENT CURRENT (mA)



























































































0.48

0.46

0.44

0.42

0.40

0.38

0.36

0.34

0.32

0.30

0.01 0.1 1 10

0 4 8

12 16

20 24 28

32 36

OUTPUT AMPLITUDE (Vrms) SUPPLY VOLTAGE (V)

Figure 19. THD+N vs. Output Amplitude Figure 20. Quiescent Current vs. Supply

Voltage



0.50

QUIESCENT CURRENT (mA)

0.48

0.46

0.44

0.42

0.40

0.38

0.36

0.34 VS = 4 V


3.0


OPEN LOOP GAIN (µV/V)

2.5


2.0


1.5


1.0


0.5


AV = 1

AV = 1

0.32

0.30

VS = 36 V


0.0

50 25

0 25 50

75 100 125

150

50

25 0

25 50

75 100

125 150

TEMPERATURE (C) TEMPERATURE (C)

Figure 21. Quiescent Current vs. Temperature Figure 22. Open Loop Gain vs. Temperature



OUTPUT IMPEDANCE (Q)

10k 1k

100


10


1


50

45

40

OVERSHOOT (%)

35

30

25

20

15

10

5


Riso = 0 Q Riso = 25 Q Riso = 50 Q


RL = 10 kQ AV = 1

0.1

1


10 100 1k


10k


100k 1M

0

10M 0


200


400


600


800 1000

FREQUENCY (Hz) CAPACITIVE LOAD (pF)

Figure 23. Open Loop Output Impedance vs.

Frequency

Figure 24. Small Signal Overshoot vs. Capacitive Load (100 mV Output Step)



70


60


OVERSHOOT (%)

50


40


30


20


Riso = 0 Q Riso = 25 Q Riso = 50 Q


RL = 10 kQ AV = 1

100 mV Step

5

4 Input

3 Output

VOLTAGE (V)

2

1

0

1

2


10


0

0 200


400


600 800


1000

3 VS = 8 V RL = 10 kQ

4 CL = 15 pF

5

CAPACITIVE LOAD (pF) TIME (100 µs/div)

Figure 25. Small Signal Overshoot vs. Capacitive Load (100 mV Output Step)

Figure 26. No Phase Reversal



4


3


INPUT VOLTAGE (V)

2


1


0


1

2 VS = 18 V

RL = 10 kQ

3 CL = 15 pF

4 AV = 10

TIME (1 µs/div)


Input Output


20


15


OUTPUT VOLTAGE (V)

10


5


0


5

10

15

20

Figure 27. Positive Overload Recovery



4

Input

3 Output

INPUT VOLTAGE (V)

2


1


0


1

2

3

4


VS = 18 V RL = 10 kQ CL = 15 pF AV = 10


20


15


OUTPUT VOLTAGE (V)

10


5


0


5

10

15

20

TIME (1 µs/div)

Figure 28. Negative Overload Recovery


0.1

0.08

0.06

VOLTAGE (V)

0.04

0.02

0

0.02

0.04

0.06

0.08

0.1


Input Output


VS = 36 V RL = 10 kQ CL = 15 pF AV = 1

0.1

















































VS = 36 V

RL = 10 kQ CL = 15 pF AV = 1














































Input Output
















0.08

0.06

VOLTAGE (V)

0.04

0.02

0

0.02

0.04

0.06

0.08

0.1

TIME (10 µs/div) TIME (10 µs/div)

Figure 29. NonInverting Small Signal Step Response

Figure 30. Inverting Small Signal Step Response



10

8

6

VOLTAGE (V)

4

2

0

2

4

6

8

10


Input Output


VS = 36 V RL = 10 kQ CL = 15 pF AV = 1


10














































VS = 36 V

RL = 10 kQ CL = 15 pF AV = 1

























































Input

Output















8

6

VOLTAGE (V)

4

2

0

2

4

6

8

10

TIME (10 µs/div) TIME (10 µs/div)

Figure 31. NonInverting Large Signal Step Response

Figure 32. Inverting Large Signal Step Response



0.01

0.008

0.006

VOLTAGE (V)

0.004

0.002

0

0.002

0.004

0.006


VS = 36 V RL = 10 kQ CL = 15 pF

VIN = 10 V Step


Output


0.01

0.008

0.006

VOLTAGE (V)

0.004

0.002

0

0.002

0.004

0.006


VS = 36 V RL = 10 kQ CL = 15 pF

VIN = 10 V Step


Output

0.008

0.01

Input

0.008

0.01

Input

TIME (5 µs/div) TIME (5 µs/div)

Figure 33. Large Signal Settling Time, LowtoHigh

Figure 34. Large Signal Settling Time, HightoLow


25

SHORT CIRCUIT CURRENT (mA)

20 VS = 36 V ISC, Source

35

VS = 18 V


15

10

5

0

5

10

15

20

25

ISC, Sink 30


OUTPUT VOLTAGE (Vpp)

25


20


15


10


5


0


VS = 9 V

VS = 5 V VS = 2.5 V

50 0

50 100

150 1k

10k

100k

1M 10M

TEMPERATURE (C) FREQUENCY (Hz)

Figure 35. Short Circuit Current vs.

Temperature

Figure 36. Maximum Output Voltage vs.

Frequency (AV = 1 for VS = ±2.5 V, ±5 V, ±9 V; AV = 2 for VS = ±18 V)



3


OUTPUT VOLTAGE LOW (V)

2.5


2


1.5


1


0.5


TA = 40C TA = 0C TA = 25C TA = 85C

TA = 125C


36


OUTPUT VOLTAGE HIGH (V)

35.5


35


34.5


34


33.5


TA = 40C TA = 0C TA = 25C TA = 85C


VS = 36 V

VS = 36 V

0

0 2 4 6 8 10 12 14 16 18 20 22 24

TA = 125C

33

0 2 4 6 8 10


12 14 16


18 20

OUTPUT CURRENT (mA) OUTPUT CURRENT (mA)

Figure 37. Output Voltage Low vs. Output Current

Figure 38. Output Voltage High vs. Output Current



160

140

EMI REJECTION (dB)

120

100

80

60

40

20

0


VS = 36 V VIN = 100 mVp

AV = 1

10M 100M 1G 10G

FREQUENCY (Hz)

Figure 39. EMIRR IN+ vs. Frequency



Overview

APPLICATION INFORMATION

The NCS21911 series of amplifiers uses a

The NCS21911, NCS21912, and NCS21914 precision op amps provide low offset voltage and zero drift over temperature. With a maximum offset voltage of 25 µV and input common mode voltage range that includes ground, the NCS21911 series is well−suited for applications where precision is required, such as low side current sensing and interfacing with sensors.

chopper−stabilized architecture, which provides the advantage of minimizing offset voltage drift over temperature and time. The simplified block diagram is shown in Figure 40. Unlike the classical chopper architecture, the chopper stabilized architecture has two signal paths.

Main amp


IN+ IN

+

+


OUT


+

+

Chopper


Chopper


RC notch filter


RC notch filter


Figure 40. Simplified NCS21911 Block Diagram


In Figure 40, the lower signal path is where the chopper samples the input offset voltage, which is then used to correct the offset at the output. The offset correction occurs at a frequency of 250 kHz. The chopper−stabilized architecture is optimized for best performance at frequencies up to the related Nyquist frequency (1/2 of the offset correction frequency). As the signal frequency exceeds the Nyquist frequency, 125 kHz, aliasing may occur at the output. This is an inherent limitation of all chopper and chopper−stabilized architectures. Nevertheless, the NCS21911 series op amps have minimal aliasing up to 200 kHz and are less susceptible to aliasing effects when compared to competitor parts from other manufacturers. ON Semiconductor’s patented approach utilizes two cascaded, symmetrical, RC notch filters tuned to the chopper frequency and its fifth harmonic to reduce aliasing effects.

The chopper−stabilized architecture also benefits from the feed−forward path, which is shown as the upper signal path of the block diagram in Figure 40. This is the high speed signal path that extends the gain bandwidth up to 2 MHz. Not

only does this help retain high frequency components of the input signal, but it also improves the loop gain at low frequencies. This is especially useful for low−side current sensing and sensor interface applications where the signal is low frequency and the differential voltage is relatively small.

Application Circuits

Low−Side Current Sensing

Low−side current sensing is used to monitor the current through a load. This method can be used to detect over−current conditions and is often used in feedback control, as shown in Figure 41. A sense resistor is placed in series with the load to ground. Typically, the value of the sense resistor is less than 100 mQ to reduce power loss across the resistor. The op amp amplifies the voltage drop across the sense resistor with a gain set by external resistors R1, R2, R3, and R4 (where R1 = R2, R3 = R4). Precision resistors are required for high accuracy, and the gain is set to utilize the full scale of the ADC for the highest resolution.


VLOAD


Load

R1


RSENSE


R2

R3


VDD


+



VDD


ADC


VDD


Microcontroller


control


R4


Figure 41. LowSide Current Sensing


Differential Amplifier for Bridged Circuits

Sensors to measure strain, pressure, and temperature are often configured in a Wheatstone bridge circuit as shown in Figure 42. In the measurement, the voltage change that is

produced is relatively small and needs to be amplified before going into an ADC. Precision amplifiers are recommended in these types of applications due to their high gain, low noise, and low offset voltage.


RF

VDD


R1 R3


R3 Rx

VDD



+



Figure 42. Wheatstone Bridge Circuit Amplification


EMI Susceptibility and Input Filtering

Op amps have varying amounts of EMI susceptibility. Semiconductor junctions can pick up and rectify EMI signals, creating an EMI−induced voltage offset at the output, adding another component to the total error. Input pins are the most sensitive to EMI. The NCS2191x integrates low−pass filters to decrease its sensitivity to EMI. Figure 39 shows the EMIRR performance.

General Layout Guidelines

To ensure optimum device performance, it is important to follow good PCB design practices. Place 0.1 µF decoupling

capacitors as close as possible to the supply pins. Keep traces short, utilize a ground plane, choose surface−mount components, and place components as close as possible to the device pins. These techniques will reduce susceptibility to electromagnetic interference (EMI). Thermoelectric effects can create an additional temperature dependent offset voltage at the input pins. To reduce these effects, use metals with low thermoelectric coefficients and prevent temperature gradients from heat sources or cooling fans.


TSOP5 CASE 483 ISSUE M



NOTE 5


T

0.10

2X



0.20

C

A

B

D 5X


NOTES:

  1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994.

  2. CONTROLLING DIMENSION: MILLIMETERS.

  3. MAXIMUM LEAD THICKNESS INCLUDES LEAD FINISH THICKNESS. MINIMUM LEAD THICKNESS IS THE MINIMUM THICKNESS OF BASE MATERIAL.

M 4. DIMENSIONS A AND B DO NOT INCLUDE MOLD

5 4

1 2 3

B

T

0.20

2X S K

B G DETAIL Z

A A

FLASH, PROTRUSIONS, OR GATE BURRS. MOLD FLASH, PROTRUSIONS, OR GATE BURRS SHALL NOT EXCEED 0.15 PER SIDE. DIMENSION A.

  1. OPTIONAL CONSTRUCTION: AN ADDITIONAL TRIMMED LEAD IS ALLOWED IN THIS LOCATION. TRIMMED LEAD NOT TO EXTEND MORE THAN 0.2 FROM BODY.


    DIM

    MILLIMETERS

    MIN

    MAX

    A

    2.85

    3.15

    B

    1.35

    1.65

    C

    0.90

    1.10

    D

    0.25

    0.50

    G

    0.95 BSC

    H

    0.01

    0.10

    J

    0.10

    0.26

    K

    0.20

    0.60

    M

    0 °

    10 °

    S

    2.50

    3.00

    TOP VIEW



    C

    0.05 H

    DETAIL Z

    C

    J


    SIDE VIEW

    SEATING PLANE

    END VIEW


    SOLDERING FOOTPRINT*

    1.9

    0.95 0.037

    0.074



    1.0

    0.039

    2.4

    0.094






    0.7 0.028


    SCALE 10:1


    mm inches

    ( )

    *For additional information on our PbFree strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.


    Micro8

    CASE 846A02 ISSUE J



    HE


    PIN 1 ID e


    SEATING PLANE

    D


    E


    b 8 PL


    0.08 (0.003)

    M

    T

    B

    S

    A

    S


    T



    0.038 (0.0015)


    A


    A1 c L


    NOTES:

    1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982.

    2. CONTROLLING DIMENSION: MILLIMETER.

    3. DIMENSION A DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED

      0.15 (0.006) PER SIDE.

    4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE.

    5. 846A-01 OBSOLETE, NEW STANDARD 846A-02.



      DIM

      MILLIMETERS

      INCHES

      MIN

      NOM

      MAX

      MIN

      NOM

      MAX

      A

      −−

      −−

      1.10

      −−

      −−

      0.043

      A1

      0.05

      0.08

      0.15

      0.002

      0.003

      0.006

      b

      0.25

      0.33

      0.40

      0.010

      0.013

      0.016

      c

      0.13

      0.18

      0.23

      0.005

      0.007

      0.009

      D

      2.90

      3.00

      3.10

      0.114

      0.118

      0.122

      E

      2.90

      3.00

      3.10

      0.114

      0.118

      0.122

      e

      0.65 BSC

      0.026 BSC

      L

      0.40

      0.55

      0.70

      0.016

      0.021

      0.028

      HE

      4.75

      4.90

      5.05

      0.187

      0.193

      0.199


      RECOMMENDED SOLDERING FOOTPRINT*

      8X

      8X 0.48 0.80

      5.25


      0.65

      PITCH

      DIMENSION: MILLIMETERS

      *For additional information on our PbFree strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.


      SOIC8 NB CASE 75107 ISSUE AK



      X

      A



      5


      8


      0.25 (0.010) M

      Y M

      B S

      1


      4

      Y


      G


      C


      DIM

      MILLIMETERS

      INCHES

      MIN

      MAX

      MIN

      MAX

      A

      4.80

      5.00

      0.189

      0.197

      B

      3.80

      4.00

      0.150

      0.157

      C

      1.35

      1.75

      0.053

      0.069

      D

      0.33

      0.51

      0.013

      0.020

      G

      1.27 BSC

      0.050 BSC

      H

      0.10

      0.25

      0.004

      0.010

      J

      0.19

      0.25

      0.007

      0.010

      K

      0.40°

      1.27°

      0.016°

      0.050°

      M

      0

      8

      0

      8

      N

      0.25

      0.50

      0.010

      0.020

      S

      5.80

      6.20

      0.228

      0.244

      SEATING




      K


      N X 45°

      NOTES:

      1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982.

      2. CONTROLLING DIMENSION: MILLIMETER.

      3. DIMENSION A AND B DO NOT INCLUDE MOLD PROTRUSION.

      4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE.

      5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION.

      6. 75101 THRU 75106 ARE OBSOLETE. NEW STANDARD IS 75107.

Z

PLANE


0.10 (0.004)

H D M J



0.25 (0.010)

M

Z

Y

S

X

S



SOLDERING FOOTPRINT*



1.52 0.060


7.0

0.275

4.0

0.155


0.6 0.024

1.270

( )

0.050


SCALE 6:1


mm inches

*For additional information on our PbFree strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.


SOIC14 NB CASE 751A03 ISSUE L


A

D

B


14 8

A3

H E

L


NOTES:

  1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994.

  2. CONTROLLING DIMENSION: MILLIMETERS.

  3. DIMENSION b DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE PROTRUSION SHALL BE 0.13 TOTAL IN EXCESS OF AT MAXIMUM MATERIAL CONDITION.

  4. DIMENSIONS D AND E DO NOT INCLUDE MOLD PROTRUSIONS.


    DIM

    MILLIMETERS

    INCHES

    MIN

    MAX

    MIN

    MAX

    A

    1.35

    1.75

    0.054

    0.068

    A1

    0.10

    0.25

    0.004

    0.010

    A3

    0.19

    0.25

    0.008

    0.010

    b

    0.35

    0.49

    0.014

    0.019

    D

    8.55

    8.75

    0.337

    0.344

    E

    3.80

    4.00

    0.150

    0.157

    e

    1.27 BSC

    0.050 BSC

    H

    5.80

    6.20

    0.228

    0.244

    h

    0.25

    0.50

    0.010

    0.019

    L

    0.40

    1.25

    0.016

    0.049

    M

    0 °

    7 °

    0 °

    7 °

  5. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE.

1

7


0.25 M

B M

13X b

DETAIL A


0.25 M

C

A S

B S


h

A X 45 °

DETAIL A



0.10

e A1

M

C

SEATING PLANE


SOLDERING FOOTPRINT*

6.50


1


14X

1.18


1.27

PITCH


14X

0.58


DIMENSIONS: MILLIMETERS

*For additional information on our PbFree strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.



0.15 (0.006)

U S


T

L

PIN 1 IDENT.


0.15 (0.006)

U S


14X K REF


14



1


V

2X L/2

A

TSSOP14 WB CASE 948G ISSUE C


U S


0.25 (0.010)

V S

T

0.10 (0.004) M

N

8

M

B

U

N

7

F DETAIL E

K K1


NOTES:

  1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982.

  2. CONTROLLING DIMENSION: MILLIMETER.

  3. DIMENSION A DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE.

  4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE.

  5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION.

  6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY.


    DIM

    MILLIMETERS

    INCHES

    MIN

    MAX

    MIN

    MAX

    A

    4.90

    5.10

    0.193

    0.200

    B

    4.30

    4.50

    0.169

    0.177

    C

    −−−

    1.20

    −−−

    0.047

    D

    0.05

    0.15

    0.002

    0.006

    F

    0.50

    0.75

    0.020

    0.030

    G

    0.65 BSC

    0.026 BSC

    H

    0.50

    0.60

    0.020

    0.024

    J

    0.09

    0.20

    0.004

    0.008

    J1

    0.09

    0.16

    0.004

    0.006

    K

    0.19

    0.30

    0.007

    0.012

    K1

    0.19

    0.25

    0.007

    0.010

    L

    6.40 BSC

    0.252 BSC

    M

    0 °

    8 °

    0 °

    8 °

  7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE W.


T

J J1


C


SECTION NN


W


0.10 (0.004)

T

D

G

SEATING PLANE

H DETAIL E



SOLDERING FOOTPRINT

7.06


1


0.65

PITCH


14X

0.36


14X

1.26


DIMENSIONS: MILLIMETERS


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