Low input bias current: 50 pA maximum Offset voltage
1.5 mV maximum for B grade (ADA4062-2 SOIC package)
2.5 mV maximum for A grade
OUT A 1
–IN A 2
+IN A 3
1 OUT A
10 NC
V– 4
ADA4062-2
TOP VIEW
(Not to Scale)
8 V+
7 OUT B
07670-001
6 –IN B
5
+IN B
Offset voltage drift: 5 μV/°C typical Slew rate: 3.3 V/μs typical
CMRR: 90 dB typical
Low supply current: 165 μA typical High input impedance
Unity-gain stable
Figure 1. 8-Lead Narrow-Body SOIC and 8-Lead MSOP
±5 V to ±15 V dual-supply operation Packaging
8-lead SOIC, 8-lead MSOP, 10-lead LFCSP, 14-lead TSSOP, and 16-lead LFCSP packages
–IN A 2
ADA4062-2
TOP VIEW
(Not to Scale)
+IN A 3
V– 4
NC = NO CONNECT
8 OUT B
9 V+
7 –IN B
NC 5
+IN B 6
07670-065
Power controls and monitoring
Figure 2. 10-Lead LFCSP
Active filters Industrial/process controls Body probe electronics Data acquisition Integrators
OUT A 1
–IN A 2
+IN A 3
V+ 4
+IN B 5
ADA4062-4
TOP VIEW
(Not to Scale)
14 OUT D
13 –IN D
12 +IN D
11 V–
10 +IN C
Input buffering
–IN B 6
OUT B 7
9 –IN C
07670-064
8 OUT C
The ADA4062-2 and ADA4062-4 are dual and quad JFET-input amplifiers with industry-leading performance. They offer lower power, offset voltage, drift, and ultralow bias current. The ADA4062-2 B grade (SOIC package) features a typical low offset
voltage of 0.5 mV, an offset drift of 5 μV/°C, and a bias current
Figure 3. 14-Lead TSSOP
of 2 pA.
The ADA4062 family is ideal for various applications, including
–IN A 1
ADA4062-4
TOP VIEW
(Not to Scale)
16 NC
+IN A 2
V+ 3
12 –IN D
15 OUT A
14 OUT D
13 NC
11 +IN D
10 V–
–IN B 5
OUT B 6
OUT C 7
–IN C 8
process controls, industrial and instrumentation equipment, active filtering, data conversion, buffering, and power control and monitoring. With a low supply current of 165 μA per amplifier, they are well suited for lower power applications.
NOTES
+IN B 4 9
+IN C
The ADA4062 family is also specified for the extended industrial temperature range of −40°C to +125°C. The ADA4062-2 is available in lead-free, 8-lead SOIC, 8-lead MSOP, and 10-lead LFCSP (1.6 mm × 1.3 mm × 0.55 mm) packages, while the ADA4062-4 is available in lead-free, 14-lead TSSOP and
lead LFCSP packages.
Rev. B
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibilityis assumedby Analog Devicesforitsuse, norforanyinfringements ofpatents orother rightsofthirdpartiesthatmayresultfromitsuse.Specificationssubjecttochangewithoutnotice.No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
NC = NO CONNECT.
07670-068
IT IS RECOMMENDED TO CONNECT THE EXPOSED PAD TO V–.
Figure 4. 16-Lead LFCSP
Table 1. Low Power Op Amps
Precision CMOS | Precision High Bandwidth | High Bandwidth | |
Single Dual Quad |
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com
Fax: 781.461.3113 ©2008–2010 Analog Devices, Inc. All rights reserved.
Typical Performance Characteristics 6
High-Side Signal Conditioning 15
Micropower Instrumentation Amplifier 15
2/10—Rev. A to Rev. B
Added 16-Lead LFCSP Package........................................Universal
Changes to Features Section, General Description Section, and Table 1 1
Changes to Offset Voltage Drift Parameter, Table 2 3
Changes to Table 4 5
Changes to Typical Performance Characteristics Layout 6
Added Figure 6 and Figure 9; Renumbered Sequentially 6
Changes to Figure 7, Figure 8, and Figure 10 6
Changes to Figure 25 and Figure 28 9
Changes to Figure 37 and Figure 40 11
Changes to Figure 41 to Figure 46 12
Changes to Figure 47 and Figure 50 13
Changes to Figure 53 to Figure 58 14
Changes to Notch Filter Section and Micropower Instrumentation Amplifier Section 15
Updated Outline Dimensions 18
Changes to Ordering Guide 20
7/09—Rev. 0 to Rev. A
Added ADA4062-4............................................................. Universal Added 14-Lead TSSOP Package....................................... Universal
Added 10-Lead LFCSP Package ....................................... Universal
Changes to Features Section and Table 1 1
Changes to Table 2 3
Changes to Thermal Resistance Section 5
Changes to Figure 5, Figure 6, Figure 8, and Figure 9 6
Changes to Figure 37 and Figure 40. 11
Changes to Figure 41 and Figure 44. 12
Changes to Figure 47, Figure 48, Figure 50, and Figure 51 13
Added Figure 49 and Figure 52; Renumbered Sequentially 13
Changes to Figure 57 and Figure 59. 15
Changes to Phase Reversal Section and Figure 61 16
Changes to Figure 63 17
Updated Outline Dimensions 18
Changes to Ordering Guide 19
10/08—Revision 0: Initial Version
VSY = ±15 V, VCM = 0 V, TA = 25°C, unless otherwise noted.
Table 2.
Parameter | Symbol | Conditions | Min | Typ | Max | Unit |
INPUT CHARACTERISTICS Offset Voltage B Grade (ADA4062-2, 8-Lead SOIC Only) A Grade Offset Voltage Drift Input Bias Current Input Offset Current Input Voltage Range Common-Mode Rejection Ratio B Grade (ADA4062-2, 8-Lead SOIC Only) A Grade Large-Signal Voltage Gain Input Resistance Input Capacitance, Differential Mode Input Capacitance, Common Mode | VOS | |||||
0.5 | 1.5 | mV | ||||
−40°C ≤ TA ≤ +125°C | 3 | mV | ||||
0.75 | 2.5 | mV | ||||
−40°C ≤ TA ≤ +125°C | 5 | mV | ||||
∆VOS/∆T | −40°C ≤ TA ≤ +125°C | 5 | μV/°C | |||
IB | 2 | 50 | pA | |||
−40°C ≤ TA ≤ +125°C | 5 | nA | ||||
IOS | 0.5 | 25 | pA | |||
−40°C ≤ TA ≤ +125°C | 2.5 | nA | ||||
−40°C ≤ TA ≤ +125°C | −11.5 | +15 | V | |||
CMRR | ||||||
VCM = −11.5 V to +11.5 V | 80 | 90 | dB | |||
−40°C ≤ TA ≤ +125°C | 80 | dB | ||||
VCM = −11.5 V to +11.5 V | 73 | 90 | dB | |||
−40°C ≤ TA ≤ +125°C | 70 | dB | ||||
AVO | RL = 10 kΩ, VO = −10 V to +10 V | 76 | 83 | dB | ||
−40°C ≤ TA ≤ +125°C | 72 | dB | ||||
RIN | 10 | TΩ | ||||
CINDM | 1.5 | pF | ||||
CINCM | 4.8 | pF | ||||
OUTPUT CHARACTERISTICS | ||||||
Output Voltage High | VOH | RL = 10 kΩ to VCM | 13 | 13.5 | V | |
−40°C ≤ TA ≤ +125°C | 12.5 | V | ||||
Output Voltage Low | VOL | RL = 10 kΩ to VCM | −13.8 | −13 | V | |
−40°C ≤ TA ≤ +125°C | −12.5 | V | ||||
Short-Circuit Current | ISC | 20 | mA | |||
Closed-Loop Output Impedance | ZOUT | f = 1 kHz, AV = 1 | 1 | Ω | ||
POWER SUPPLY Power Supply Rejection Ratio B Grade (ADA4062-2, 8-Lead SOIC Only) A Grade Supply Current per Amplifier | PSRR | |||||
VSY = ±4 V to ±18 V | 80 | 90 | dB | |||
−40°C ≤ TA ≤ +125°C | 80 | dB | ||||
VSY = ±4 V to ±18 V | 74 | 90 | dB | |||
−40°C ≤ TA ≤ +125°C | 70 | dB | ||||
ISY | IO = 0 mA | 165 | 220 | μA | ||
−40°C ≤ TA ≤ +125°C | 260 | μA | ||||
DYNAMIC PERFORMANCE | ||||||
Slew Rate | SR | RL = 10 kΩ, CL = 100 pF, AV = 1 | 3.3 | V/μs | ||
Settling Time | tS | To 0.1%, VIN = 10 V step, CL = 100 pF, | 3.5 | μs | ||
RL = 10 kΩ, AV = 1 | ||||||
Gain Bandwidth Product | GBP | RL = 10 kΩ, AV = 1 | 1.4 | MHz | ||
Phase Margin | ΦM | RL = 10 kΩ, AV = 1 | 78 | Degrees | ||
Channel Separation (ADA4062-2 Only) | CS | f = 1 kHz | 135 | dB | ||
Channel Separation (ADA4062-4 Only) | CS | f = 1 kHz | 130 | dB |
Parameter | Symbol | Conditions | Min Typ Max | Unit |
NOISE PERFORMANCE | ||||
Voltage Noise | en p-p | f = 0.1 Hz to 10 Hz | 1.5 | μV p-p |
Voltage Noise Density | en | f = 1 kHz | 36 | nV/√Hz |
Current Noise Density | in | f = 1 kHz | 5 | fA/√Hz |
Table 3.
Parameter | Rating |
Supply Voltage | ±18 V |
Input Voltage | ±VSY |
Differential Input Voltage | ±VSY |
Input Current | ±10 mA |
Output Short-Circuit Duration to GND | Indefinite |
Storage Temperature Range | −65°C to +150°C |
Operating Temperature Range | −40°C to +125°C |
Junction Temperature Range | −65°C to +150°C |
Lead Temperature (Soldering, 60 sec) | 300°C |
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
θJA is specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages. It was measured using a standard 4-layer board.
Table 4. Thermal Resistance
Package Type | θJA | θJC | Unit |
8-Lead SOIC | 120 | 45 | °C/W |
8-Lead MSOP | 142 | 45 | °C/W |
10-Lead LFCSP | 132 | 46 | °C/W |
14-Lead TSSOP | 112 | 35 | °C/W |
16-Lead LFCSP | 75 | 12 | °C/W |
The supply voltages of the op amps must be established simultaneously with, or before, any input signals are applied. If this is not possible, the input current must be limited to 10 mA.
TA = 25°C, unless otherwise noted.
70
VSY = ±5V VCM = 0V
60 BASED ON 600 OP AMPS
280
240
VSY = ±15V VCM = 0V
BASED ON 600 OP AMPS
NUMBER OF AMPLIFERS
NUMBER OF AMPLIFERS
50 200
40 160
30 120
20 80
07670-054
10 40
0
–4 –3 –2 –1 0 1 2 3 4
VOS (mV)
Figure 5. Input Offset Voltage Distribution
0
07670-003
–4 –3 –2 –1 0 1 2 3 4
VOS (mV)
Figure 8. Input Offset Voltage Distribution
40
ADA4062-2 ONLY VSY = ±5V
–40°C ≤ TA ≤ +125°C BASED ON 200 OP AMPS
NUMBER OF AMPLIFERS
30
40
ADA4062-2 ONLY VSY = ±15V
–40°C ≤ TA ≤ +125°C
BASED ON 200 OP AMPS
NUMBER OF AMPLIFERS
30
20 20
10 10
0
–2 0 2 4 6 8 10
TCVOS (µV/°C)
Figure 6. Input Offset Voltage Drift Distribution
0
07670-005
–2 0 2 4 6 8 10
TCVOS (µV/°C)
Figure 9. Input Offset Voltage Drift Distribution
07670-055
25 25
ADA4062-4 ONLY VSY = ±5V
–40°C ≤ T ≤ 125°C
NUMBER OF AMPLIFIERS
20 BASED ON 200 OP AMPS 20
ADA4062-4 ONLY VSY = ±15V
–40°C ≤ T ≤ 125°C
BASED ON 200 OP AMPS
NUMBER OF AMPLIFIERS
15 15
10 10
5 5
0
07670-070
0 2 4 6 8 10 12 14 16 18
TCVOS (µV/°C)
Figure 7. Input Offset Voltage Drift Distribution
0
07670-069
0 2 4 6 8 10 12 14 16 18
TCVOS (µV/°C)
Figure 10. Input Offset Voltage Drift Distribution
VSY = ±5V | |
5
4
3
2
VOS (mV)
1
0
–1
–2
–3
–4
–5
–4 –3 –2 –1 0 1 2 3 4 5
VCM (V)
Figure 11. Input Offset Voltage vs. Common-Mode Voltage
5
VSY = ±15V |
4
3
2
VOS (mV)
1
0
–1
–2
–3
–4
07670-006
–5
–15 –12 –9 –6 –3 0 3 6 9 12 15
VCM (V)
Figure 14. Input Offset Voltage vs. Common-Mode Voltage
07670-056
10000
VSY = ±5V
10000
VSY = ±15V
1000 1000
100 100
IB (pA)
IB (pA)
10 10
07670-012
1 1
0.1
–50 –25 0 25 50 75 100 125
TEMPERATURE (°C)
Figure 12. Input Bias Current vs. Temperature
0.1
07670-009
–50 –25 0 25 50 75 100 125
TEMPERATURE (°C)
Figure 15. Input Bias Current vs. Temperature
VSY = ±5V | |||||||
3
2
IB (pA)
1
0
–1
–2
–3 –2 –1 0 1 2 3 4 5
VCM (V)
Figure 13. Input Bias Current vs. Common-Mode Voltage
5
VSY = ±15V | |||||||||||||
4
IB (pA)
3
2
1
07670-013
07670-010
0
–12 –10 –8 –6 –4 –2 0 2 4 6 8 10 12 14 16
VCM (V)
Figure 16. Input Bias Current vs. Common-Mode Voltage
VSY = ±15V
10 10
VSY = ±5V
OUTPUT VOLTAGE TO SUPPLY RAIL (V)
V+ – VOH
1
VOL – V–
V+ – VOH
OUTPUT VOLTAGE TO SUPPLY RAIL (V)
1
VOL – V–
07670-014
0.1
0.01 0.1 1 10 100
LOAD CURRENT (mA)
Figure 17. Output Voltage to Supply Rail vs. Load Current
0.1
07670-011
0.01 0.1 1 10 100
LOAD CURRENT (mA)
Figure 20. Output Voltage to Supply Rail vs. Load Current
220
200
SUPPLY CURRENT/AMP (µA)
180
160
140
120
100
80
60
40
20
0
+125°C | ||||||||
+85°C | ||||||||
+25°C | ||||||||
–40°C | ||||||||
0 2 4 6 8 10 12 14 16 18
SUPPLY VOLTAGE (±V)
Figure 18. Supply Current/Amp vs. Supply Voltage
200
VSY = ±15V | |||||||
VSY = | ±5V | ||||||
190
SUPPLY CURRENT/AMP (µA)
180
170
160
150
140
130
120
110
07670-149
100
–50 –25 0 25 50 75 100 125 150
TEMPERATURE (°C)
Figure 21. Supply Current/Amp vs. Temperature
OUTPUT VOTLAGE TO SUPPLY RAIL (V)
2.0
1.5
1.0
V+ – VOH VOL – V–
07670-146
VSY = ±5V RL = 10kΩ
2.0
OUTPUT VOTLAGE TO SUPPLY RAIL (V)
1.5
1.0
V+ – VOH
VOL – V–
VSY = ±15V RL = 10kΩ
0.5 0.5
0
–50 –25
0 25 50 75 100
TEMPERATURE (°C)
125
0
–50 –25
0 25 50 75 100
TEMPERATURE (°C)
125
07670-018
07670-015
Figure 19. Output Voltage to Supply Rail vs. Temperature Figure 22. Output Voltage to Supply Rail vs. Temperature
120
100
PHASE
VSY = ±5V
120
100
120
100
PHASE
VSY = ±15V
120
100
80 80 80 80
PHASE (Degrees)
PHASE (Degrees)
60 60 60 60
GAIN (dB)
40
GAIN
20
40 40
GAIN (dB)
20 20
40
GAIN
20
0 0 0 0
–20
–20
–20
–20
–40
–40
07670-019
–40
–40
–60
–60
–60
07670-016
–60
1k 10k 100k 1M 10M 100M FREQUENCY (Hz)
Figure 23. Open-Loop Gain and Phase vs. Frequency
1k 10k 100k 1M 10M 100M FREQUENCY (Hz)
Figure 26. Open-Loop Gain and Phase vs. Frequency
50
40
30
GAIN (dB)
20
10
0
–10
AV = +100
AV = +10
AV = +1
VSY = ±5V
50
40
30
GAIN (dB)
20
10
0
07670-020
–10
AV = +100
AV = +10
AV = +1
VSY = ±15V
–20
10 100 1k 10k 100k 1M 10M 100M FREQUENCY (Hz)
Figure 24. Closed-Loop Gain vs. Frequency
–20
07670-017
10 100 1k 10k 100k 1M 10M 100M FREQUENCY (Hz)
Figure 27. Closed-Loop Gain vs. Frequency
1000
VSY = ±5V
1000
VSY = ±15V
100
ZOUT (Ω)
AV = +100
100
AV = +100
ZOUT (Ω)
10 AV = +10
10 AV = +10
1 AV = +1
1
AV = +1
07670-021
0.1
100 1k 10k 100k 1M 10M
FREQUENCY (Hz)
Figure 25. Output Impedance vs. Frequency
0.1
07670-018
100 1k 10k 100k 1M 10M
FREQUENCY (Hz)
Figure 28. Output Impedance vs. Frequency
VSY = ±5V | ||||||||||||||||||||||||
100
90
80
70
CMRR (dB)
60
50
40
30
20
10
0
100 1k 10k 100k 1M 10M FREQUENCY (Hz)
Figure 29. CMRR vs. Frequency
100
VSY = ±15V | ||||||||||||||||||||||||
90
80
70
CMRR (dB)
60
50
40
30
20
10
07670-022
0
100 1k 10k 100k 1M 10M FREQUENCY (Hz)
Figure 32. CMRR vs. Frequency
07670-025
120
100
140
120
VSY = ±15V
VSY = ±5V | ||||||||||||||||||||||||||||
PSRR+ | ||||||||||||||||||||||||||||
PSRR– | ||||||||||||||||||||||||||||
100
80
PSRR (dB)
PSRR (dB)
80
60
60
40
40
20
20
07670-026
0 0
PSRR–
PSRR+
–20
10 100
1k 10k 100k 1M 10M FREQUENCY (Hz)
Figure 30. PSRR vs. Frequency
–20
10 100
1k 10k 100k 1M 10M FREQUENCY (Hz)
07670-023
Figure 33. PSRR vs. Frequency
VSY = ±15V AV = +1
RL = 10kΩ
VSY = ±5V AV = +1 RL = 10kΩ
60 60
50 50
OVERSHOOT (%)
OVERSHOOT (%)
40 40
30 30
20 20
07670-030
10 10
0
10 100 1000 10000
CL (pF)
Figure 31. Small-Signal Overshoot vs. Load Capacitance
0
07670-027
10 100 1000 10000
CL (pF)
Figure 34. Small-Signal Overshoot vs. Load Capacitance
VOLTAGE (1V/DIV)
VSY = ±5V VIN = 4V p-p AV = +1
RL = 10kΩ
CL = 100pF
VSY = ±15V VIN = 20V p-p AV = +1
VOLTAGE (5V/DIV)
RL = 10kΩ
07670-031
CL = 100pF
TIME (4µs/DIV)
Figure 35. Large-Signal Transient Response
TIME (10µs/DIV)
07670-028
Figure 38. Large-Signal Transient Response
VOLTAGE (20mV/DIV)
VSY = ±5V
VIN = 100mV p-p AV = +1
RL = 10kΩ
CL = 100pF
VSY = ±15V
VOLTAGE (20mV/DIV)
VIN = 100mV p-p AV = +1
RL = 10kΩ
CL = 100pF
07670-032
07670-029
TIME (10µs/DIV) TIME (10µs/DIV)
Figure 36. Small-Signal Transient Response Figure 39. Small-Signal Transient Response
4
2
INPUT
0
VSY = ±5V AV = –10
4
2
INPUT
OUTPUT VOLTAGE (V)
INPUT VOLTAGE (V)
0
VSY = ±15V AV = –10
INPUT VOLTAGE (V)
OUTPUT
0
–2
–4
OUTPUT
OUTPUT VOLTAGE (V)
0
–5
–10
07670-036
07670-033
–15
–6
TIME (2µs/DIV)
TIME (2µs/DIV)
–20
Figure 37. Negative Overload Recovery Figure 40. Negative Overload Recovery
VSY = ±5V AV = –10 | ||||||||
INPUT | ||||||||
OUTPUT | ||||||||
2
0
INPUT VOLTAGE (V)
–2
4
2
07670-037
0
–2
TIME (2µs/DIV)
Figure 41. Positive Overload Recovery
2
VSY = ±15V AV = –10 | ||||||||
INPUT | ||||||||
OUTPUT | ||||||||
0
OUTPUT VOLTAGE (V)
INPUT VOLTAGE (V)
OUTPUT VOLTAGE (V)
–2
15
10
5
07670-034
0
–5
TIME (2µs/DIV)
Figure 44. Positive Overload Recovery
INPUT
VOLTAGE (1V/DIV)
VOLTAGE (5V/DIV)
INPUT
OUTPUT
+20mV 0V
OUTPUT
+100mV 0V
VSY = ±5V CL = 100pF RL = 10kΩ
ERROR BAND
–20mV
VSY = ±15V CL = 100pF RL = 10kΩ
ERROR BAND
–100mV
07670-075
07670-077
TIME (2µs/DIV) TIME (2µs/DIV)
Figure 42. Positive Settling Time to 0.1% Figure 45. Positive Settling Time to 0.1%
VOLTAGE (1V/DIV)
INPUT
OUTPUT
VSY = ±5V CL = 100pF RL = 10kΩ
+20mV 0V
INPUT
VOLTAGE (5V/DIV)
OUTPUT
VSY = ±15V CL = 100pF RL = 10kΩ
+100mV 0V
07670-076
ERROR BAND
–20mV
ERROR BAND
–100mV
TIME (2µs/DIV)
Figure 43. Negative Settling Time to 0.1%
TIME (2µs/DIV)
07670-078
Figure 46. Negative Settling Time to 0.1%
1000
VSY = ±5V
1000
VSY = ±15V
VOLTAGE NOISE DENSITY (nV/√Hz)
VOLTAGE NOISE DENSITY (nV/√Hz)
100 100
10
1 10 100 1k
FREQUENCY (Hz)
Figure 47. Voltage Noise Density
10
07670-040
1 10 100 1k
FREQUENCY (Hz)
Figure 50. Voltage Noise Density
INPUT NOISE VOLTAGE (0.5µV/DIV)
07670-043
INPUT NOISE VOLTAGE (0.5µV/DIV)
VSY = ±5V |
VSY = ±15V
TIME (1s/DIV)
Figure 48. 0.1 Hz to 10 Hz Noise
TIME (1s/DIV)
07670-041
Figure 51. 0.1 Hz to 10 Hz Noise
0
–20
CHANNEL SEPARATION (dB)
–40
–60
VSY = ±5V VIN = 5V p-p RL = 10kΩ
ADA4062-2 ONLY
100kΩ
RL
07670-044
1kΩ
0
–20
CHANNEL SEPARATION (dB)
–40
–60
VSY = ±15V VIN = 10V p-p RL = 10kΩ
ADA4062-2 ONLY
100kΩ
RL
1kΩ
–80 –80
–100 –100
–120 –120
–140 –140
–160
100 1k 10k 100k FREQUENCY (Hz)
–160
07670-046
100 1k 10k 100k
FREQUENCY (Hz)
07670-049
Figure 49. Channel Separation vs. Frequency (ADA4062-2 Only) Figure 52. Channel Separation vs. Frequency (ADA4062-2 Only)
VSY = ±5V VIN = 5V p-p RL = 10kΩ
ADA4062-4 ONLY
0
–20
CHANNEL SEPARATION (dB)
–40
–60
100kΩ
RL
1kΩ
0
–20
CHANNEL SEPARATION (dB)
–40
–60
100kΩ
RL
1kΩ
VSY = ±15V VIN = 10V p-p RL = 10kΩ
ADA4062-4 ONLY
–80 –80
–100 –100
–120 –120
–140 –140
–160
07670-067
100 1k 10k 100k FREQUENCY (Hz)
–160
07670-066
100 1k 10k 100k
FREQUENCY (Hz)
Figure 53. Channel Separation vs. Frequency (ADA4062-4 Only) Figure 56. Channel Separation vs. Frequency (ADA4062-4 Only)
100
10
THD + N (%)
1
10
VS = ±5V
f = 1kHz RL = 10kΩ
1
THD + N (%)
0.1
0.1
0.01
0.001
0.001 0.01 0.1 1 10
AMPLITUDE (V rms)
Figure 54. THD + N vs. Amplitude
0.01
VS = ±15V
f = 1kHz RL = 10kΩ
07670-072
0.001
0.001 0.01 0.1 1 10
AMPLITUDE (V rms)
Figure 57 THD + N vs. Amplitude
07670-071
1
THD + N (%)
0.1
07670-073
0.01
1
THD + N (%)
0.1
0.01
VS = ±15V
VIN = 2V rms RL = 10kΩ
0.001
VSY = ±5V | ||||||||||||||||||||||||||||
VIN = 0.5V rms | ||||||||||||||||||||||||||||
RL = 10kΩ | ||||||||||||||||||||||||||||
10 100 1k 10k 100k FREQUENCY (Hz)
Figure 55. THD + N vs. Frequency
0.001
07670-074
100 1k 10k 100k 1M
FREQUENCY (Hz)
Figure 58. THD + N vs. Frequency
A notch filter rejects a specific interfering frequency and can be implemented using a single op amp. Figure 59 shows a 60 Hz notch filter that uses the twin-T network with the ADA4062-x configured as a voltage follower. The ADA4062-x works as a buffer that provides high input resistance and low output impedance. The low bias current (2 pA typical) and high input resistance (10 TΩ typical) of the ADA4062-x enable large resistors and small capacitors to be used.
Many applications require the sensing of signals near the positive rail. The ADA4062-x can be used in high-side current sensing applications. Figure 61 shows a high-side signal conditioning circuit using the ADA4062-x. The ADA4062-x has an input common-mode range that includes the positive supply (−11.5 V ≤ VCM ≤ +15 V). In the circuit, the voltage drop across a low value resistor, such as the 0.1 Ω shown in Figure 61, is amplified by a factor of 5 using the ADA4062-x.
0.1Ω
Alternatively, different combinations of resistor and capacitor values can be used to achieve the desired notch frequency. However, the major drawback to this circuit topology is the need to ensure that all the resistors and capacitors be closely matched. If they are not closely matched, the notch frequency offset and drift cause the circuit to attenuate at a frequency
+15V
100kΩ
500kΩ
100kΩ
500kΩ
RL
+15V
VO
07670-058
ADA4062-x
–15V
other than the ideal notch frequency.
Therefore, to achieve the desired performance, 1% or better component tolerances are usually required. In addition, a notch filter requires an op amp with a bandwidth of at least 100× to 200× the center frequency. Hence, using the ADA4062-x with
a bandwidth of 1.4 MHz is excellent for a 60 Hz notch filter. Figure 60 shows the frequency response of the notch filter. At 60 Hz, the notch filter has about 50 dB attenuation of signal.
+VSY
Figure 61. High-Side Signal Conditioning
The ADA4062-2 is a dual amplifier and is perfectly suited for applications that require lower supply currents. For supply voltages of ±15 V, the supply current per amplifier is 165 μA typical. The ADA4062-2 also offers a typical low offset voltage drift of 5 μV/°C and a very low bias current of 2 pA, which make it well suited for instrumentation amplifiers.
Figure 62 shows the classic 2-op-amp instrumentation amplifier with four resistors using the ADA4062-2. The key to high CMRR
R1
804kΩ
IN
R2
804kΩ
C3
VO
6.6nF
R3 402kΩ
ADA4062-x
–VSY
for this instrumentation amplifier are resistors that are well matched to both the resistive ratio and relative drift. For true difference amplification, matching of the resistor ratio is very important, where R3/R4 = R1/R2. Assuming perfectly matched
C1 3.3nF
O =
f 1 2π R1 C1
R1 = R2 = 2R3
C1 = C2 = C3
2
C2 3.3nF
resistors, the gain of the circuit is 1 + R2/R1, which is approximately
100. Tighter matching of two op amps in one package, as is the case with the ADA4062-2, offers a significant boost in performance over the classical 3-op-amp configuration. Overall, the circuit only requires about 330 μA of supply current.
07670-060
Figure 59. Notch Filter Circuit
20
10
0
R4 1MΩ
R3 10.1kΩ
+15V
1/2
R1 10.1kΩ
R2 1MΩ
+15V
–10
ADA4062-2
V1 –15V
1/2 VO
ADA4062-2
GAIN (dB)
–20
–30
V2
07670-059
VO = 100(V2 – V1)
–15V
–40
–50
–70
–80
10 100 1k
FREQUENCY (Hz)
Figure 60. Frequency Response of the Notch Filter
TYPICAL: 0.5mV < │V2 – V1│< 135mV TYPICAL: –13.8V < VO < +13.5V
USE MATCHED RESISTORS
07670-057
Figure 62. Micropower Instrumentation Amplifier
Phase reversal occurs in some amplifiers when the input common- mode voltage range is exceeded. When the voltage driving the input to these amplifiers exceeds the maximum input common- mode voltage range, the output of the amplifiers changes polarity. Most JFET input amplifiers have phase reversal if either input exceeds the input common-mode range.
For the ADA4062-x, the output does not phase reverse if one or both of the inputs exceeds the input voltage range but remains within the positive supply rail and 0.5 V above the negative supply rail. In other words, for an application with a supply voltage of ±15 V, the input voltage can be as high as +15 V
VIN
VOLTAGE (5V/DIV)
VOUT
VSY = ±15V
07670-063
TIME (40µs/DIV)
without any output phase reversal. However, when the voltage of the inputs is driven beyond −14.5 V, phase reversal occurs due to saturation of the input stage leading to forward biasing of the gate-drain diode. Phase reversal in ADA4062-x can be prevented by using a Schottky diode to clamp the input terminals to each other. In the simple buffer circuit in Figure 63, D1 protects the op amp against phase reversal, and R limits the input current that flows into the op amp.
+VSY
Figure 64. No Phase Reversal
R 10kΩ
D1 IN5711
VO
07670-053
ADA4062-x
–VSY
Figure 63. Phase Reversal Solution Circuit
V+
OUT
–IN +IN
07670-062
V–
Figure 65. Simplified Schematic of the ADA4062-x
3.20
3.00
2.80
3.20
3.00
2.80
5.15
8 | 5 |
1 | 4 |
4.90
4.65
PIN 1 IDENTIFIER
0.65 BSC
0.95
0.85
0.75
0.15
0.05
COPLANARITY 0.10
0.40
0.25
1.10 MAX
6°
0°
15° MAX
0.23
0.09
0.80
0.55
0.40
100709-B
COMPLIANT TO JEDEC STANDARDS MO-187-AA
Figure 66. 8-Lead Mini Small Outline Package [MSOP] (RM-8)
Dimensions shown in millimeters
5.00 (0.1968)
4.80 (0.1890)
8 5
4.00 (0.1574)
6.20 (0.2441)
3.80 (0.1497) 1 4 5.80 (0.2284)
1.27 (0.0500) 0.50 (0.0196)
45°
0.25 (0.0098)
0.10 (0.0040)
BSC
1.75 (0.0688)
1.35 (0.0532) 8°
0°
0.25 (0.0099)
COPLANARITY
0.51 (0.0201)
1.27 (0.0500)
0.10
SEATING PLANE
0.31 (0.0122)
0.25 (0.0098)
0.17 (0.0067)
0.40 (0.0157)
COMPLIANT TO JEDEC STANDARDS MS-012-AA
012407-A
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
Figure 67. 8-Lead Standard Small Outline Package [SOIC_N] Narrow Body (R-8)
Dimensions shown in millimeters and (inches)
0.20 DIA
TYP
0.55
9
1.30 | |
1.6 |
0.40 PIN 1
0.30
0
0.40
BSC 6
IDENTIFIER
1
0.35
0.30
4 0.25
TOP VIEW BOTTOM VIEW
0.60
0.55
0.50 0.05 MAX
0.02 NOM
SEATING PLANE
0.20 BSC
033007-A
Figure 68. 10-Lead Lead Frame Chip Scale Package [LFCSP_UQ]
1.30 mm × 1.60 mm, Body, Ultra Thin Quad (CP-10-10)
Dimensions shown in millimeters
5.10
5.00
4.90
4.50
4.40
4.30
14 8
6.40
BSC
1 7
PIN 1
1.05
1.00
0.65 BSC
1.20
0.20
0.80
MAX
0.09 0.75
0.15
0.05 0.30
8°
SEATING 0°
PLANE
0.60
0.45
COPLANARITY 0.10
0.19
061908-A
COMPLIANT TO JEDEC STANDARDS MO-153-AB-1
Figure 69. 14-Lead Thin Shrink Small Outline Package [TSSOP] (RU-14)
Dimensions shown in millimeters
PIN 1 INDICATOR
3.10
3.00 SQ 2.90
0.50
BSC
0.50
0.30
0.23
0.18
13
12
9
8
16
1
EXPOSED PAD
4
5
PIN 1 INDICATOR
1.75
1.60 SQ 1.45
0.20 MIN
0.80
0.75
0.70
TOP VIEW
0.40
0.30
0.05 MAX
0.02 NOM
BOTTOM VIEW
FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
SEATING PLANE
COPLANARITY 0.08
0.20 REF
SECTION OF THIS DATA SHEET.
01-13-2010-D
COMPLIANT TO JEDEC STANDARDS MO-220-WEED-6.
Figure 70. 16-Lead Lead Frame Chip Scale Package [LFCSP_WQ] 3 mm × 3 mm Body, Very Very Thin Quad
(CP-16-22)
Dimensions shown in millimeters
Temperature Range | Package Description | Package Option | Branding | |
ADA4062-2ARMZ ADA4062-2ARMZ-RL ADA4062-2ARMZ-RL7 ADA4062-2ARZ ADA4062-2ARZ-R7 ADA4062-2ARZ-RL ADA4062-2BRZ ADA4062-2BRZ-R7 ADA4062-2BRZ-RL ADA4062-2ACPZ-R2 ADA4062-2ACPZ-RL ADA4062-2ACPZ-R7 | −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C | 8-Lead MSOP 8-Lead MSOP 8-Lead MSOP 8-Lead SOIC_N 8-Lead SOIC_N 8-Lead SOIC_N 8-Lead SOIC_N 8-Lead SOIC_N 8-Lead SOIC_N 10-Lead LFCSP_UQ 10-Lead LFCSP_UQ 10-Lead LFCSP_UQ | RM-8 RM-8 RM-8 R-8 R-8 R-8 R-8 R-8 R-8 CP-10-10 CP-10-10 CP-10-10 | A25 A25 A25 J J J |
ADA4062-4ARUZ ADA4062-4ARUZ-RL ADA4062-4ACPZ-R2 ADA4062-4ACPZ-R7 ADA4062-4ACPZ-RL | −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C | 14-Lead TSSOP 14-Lead TSSOP 16-Lead LFCSP_WQ 16-Lead LFCSP_WQ 16-Lead LFCSP_WQ | RU-14 RU-14 CP-16-22 CP-16-22 CP-16-22 | A2K A2K A2K |
1 Z = RoHS Compliant Part.
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ADA4062-4ACPZ-R2 ADA4062-4ACPZ-R7 ADA4062-4ACPZ-RL ADA4062-4ARUZ ADA4062-4ARUZ-RL ADA4062-2ACPZ-R7 ADA4062-2ACPZ-RL ADA4062-2ARMZ ADA4062-2ARMZ-R7 ADA4062-2ARMZ-RL ADA4062-2ARZ ADA4062-2ARZ-R7 ADA4062-2ARZ-RL ADA4062-2BRZ ADA4062-2BRZ-R7 ADA4062-2BRZ-RL