TSX56x, TSX56xA


Micropower, wide bandwidth (900 kHz), 16 V CMOS operational

amplifiers

Datasheet - production data




SOT23- 5 ( single)

DFN8 2x 2 ( dual)



MiniSO8 ( dual)


QFN16 3x 3 ( quad)

TSSOP14 ( quad)


Features

Low power consumption: 235 µA typ. at 5 V Supply voltage: 3 V to 16 V

Gain bandwidth product: 900 kHz typ.

Low offset voltage

“A” version: 600 µV max. Standard version: 1 mV max.

Low input bias current: 1 pA typ. High tolerance to ESD: 4 kV

Wide temperature range: -40 to 125 °C Automotive qualification

Tiny packages available: SOT23-5, DFN8 2 mm x 2 mm, MiniSO8, QFN16 3 mm x 3 mm, and TSSOP14


Benefits

Power savings in power-conscious applications

Easy interfacing with high impedance sensors


Related topics

See TSX63x series for reduced power consumption (45 mA, 200 kHz)

See TSX92x series for higher gain bandwidth products (10 MHz)


Applications

Industrial and automotive signal conditioning Active filtering

Medical instrumentation High impedance sensors


Description

The TSX56x, TSX56xA series of operational amplifiers benefit from STMicroelectronics® 16 V CMOS technology to offer state-of-the-art accuracy and performance in the smallest industrial packages. The TSX56x, TSX56xA have pinouts compatible with industrial standards and offer an outstanding speed/power consumption ratio, 900 kHz gain bandwidth product while consuming only 250 µA at 16 V. Such features make the TSX56x, TSX56xA ideal for sensor interfaces and industrial signal conditioning. The wide temperature range and high ESD tolerance ease use in harsh automotive applications.

Table 1: Device summary

Version

Standard VIO

Enhanced VIO

Single

TSX561

TSX561A

Dual

TSX562

TSX562A

Quad

TSX564

TSX564A



February 2017 DocID023274 Rev 5 1/28 This is information on a product in full production. www.st.com


Contents

  1. Pinout information 3

  2. Absolute maximum ratings and operating conditions 4

  3. Electrical characteristics 6

  4. Electrical characteristic curves 12

  5. Application information 16

    1. Operating voltages 16

    2. Rail-to-rail input 16

    3. Input offset voltage drift over temperature 16

    4. Long term input offset voltage drift 17

    5. PCB layouts 18

    6. Macromodel 18

  6. Package information 19

    1. SOT23-5 package information 20

    2. DFN8 2x2 package information 21

    3. MiniSO8 package information 22

    4. QFN16 3x3 package information 23

    5. TSSOP14 package information 25

  7. Ordering information 26

  8. Revision history 27

  1. Pinout information

    IN2+

    vee -

    IN2+

    IN2-

    IN1+

    IN2-

    OUT2

    IN1-

    Vee+

    OUT1

    Figure 1: Pin connections for each package (top view)


    Single



    Vee+


    OIJT


    SOT23-5 (TSX561)


    Dual


    0

    0


    DFN8 2x2 (TSX564

    MiniS08 (TSX564


    Quad


    j::

    ::J

    0

    ::J

    0

    ..,

    O UT4


    IN4-


    IN4+

    IN4+


    Vee-


    NC

    IN3+


    IN3•


    c-:,

    ::J

    0

    C')

    f-

    ::J

    0

    cl,

    OUT3


    QFN16 3x3 (TSX564) TSSOP14 (TSX56'}


    N

    f-

    DocID023274 Rev 5 3/28

    conditions


  2. Absolute maximum ratings and operating conditions

    Table 2: Absolute maximum ratings (AMR)

    Symbol

    Parameter

    Value

    Unit

    VCC

    Supply voltage (1)

    18


    V

    Vid

    Differential input voltage (2)

    ±VCC

    Vin

    Input voltage (3)

    (VCC-) - 0.2 to (VCC+) + 0.2

    Iin

    Input current (4)

    10

    mA

    Tstg

    Storage temperature

    -65 to 150


    °C

    Tj

    Maximum junction temperature

    150


    Rthja


    Thermal resistance junction-to-ambient (5) (6)

    SOT23-5

    250


    °C/W

    DFN8 2x2

    120

    MiniSO8

    190

    QFN16 3x3

    80

    TSSOP14

    100


    Rthjc

    Thermal resistance junction-to-case

    DFN8 2x2

    33

    QFN16 3x3

    30


    ESD

    HBM: human body model (7)

    4

    kV

    MM: machine model for TSX561 (8)

    200


    V

    MM: machine model for TSX562 and TSX564 (8)

    100

    CDM: charged device model (9)

    1.5

    kV


    Latch-up immunity

    200

    mA


    Notes:

    (1)All voltage values, except the differential voltage are with respect to the network ground terminal. (2)The differential voltage is the non-inverting input terminal with respect to the inverting input terminal. (3)Vcc - Vin must not exceed 18 V, Vin must not exceed 18 V

    (4)Input current must be limited by a resistor in series with the inputs.

    (5)Rth are typical values.

    (6)Short-circuits can cause excessive heating and destructive dissipation.

    (7)Human body model: 100 pF discharged through a 1.5 kΩ resistor between two pins of the device, done for all couples of pin combinations with other pins floating.

    (8)Machine model: a 200 pF cap is charged to the specified voltage, then discharged directly between two pins of the device with no external series resistor (internal resistor < 5 Ω), done for all couples of pin combinations with other pins floating.

    (9)Charged device model: all pins plus package are charged together to the specified voltage and then discharged directly to ground.



    4/28 DocID023274 Rev 5

    conditions


    Table 3: Operating conditions

    Symbol

    Parameter

    Value

    Unit

    VCC

    Supply voltage

    3 to 16


    V

    Vicm

    Common-mode input voltage range

    (VCC-) - 0.1 to (VCC+) + 0.1

    Toper

    Operating free-air temperature range

    -40 to 125

    °C


    DocID023274 Rev 5 5/28


  3. Electrical characteristics

    Table 4: Electrical characteristics at VCC+ = 3.3 V with VCC- = 0 V, Vicm = VCC/2, Tamb = 25 ° C, and RL = 10 kΩ connected to VCC/2 (unless otherwise specified)

    Symbol

    Parameter

    Conditions

    Min.

    Typ.

    Max.

    Unit

    DC performance


    Vio


    Offset voltage

    TSX56xA, T = 25 °C



    600


    μV

    TSX56xA, -40 °C < T < 125 °C



    1800

    TSX56x, T = 25 °C



    1


    mV

    TSX56x, -40 °C < T < 125 °C



    2.2

    ΔVio/ΔT

    Input offset voltage drift

    -40 °C < T < 125 °C (1)


    2

    12

    µV/°C


    Iib

    Input bias current, Vout = VCC/2

    T = 25 °C


    1

    100 (2)


    pA

    -40 °C < T < 125 °C


    1

    200 (2)


    Iio

    Input offset current, Vout = VCC/2

    T = 25 °C


    1

    100 (2)

    -40 °C < T < 125 °C


    1

    200 (2)


    CMR1

    Common mode rejection ratio, CMR = 20 log (ΔVic/ΔVio), Vic = -0.1 V to VCC - 1.5 V, Vout = VCC/2,

    RL > 1 MΩ

    T = 25 °C

    63

    80



    dB


    -40 °C < T < 125 °C


    59




    CMR2

    Common mode rejection ratio, CMR = 20 log (ΔVic/ΔVio), Vic = -0.1 V to VCC + 0.1 V, Vout = VCC/2, RL > 1 MΩ

    T = 25 °C

    47

    66



    -40 °C < T < 125 °C


    45




    Avd

    Large signal voltage gain, Vout = 0.5 V to (VCC - 0.5 V), RL > 1 MΩ

    T = 25 °C

    85



    -40 °C < T < 125 °C

    83




    VOH

    High-level output voltage, VOH = VCC - Vout

    T = 25 °C



    70


    mV

    -40 °C < T < 125 °C



    100


    VOL


    Low-level output voltage

    T = 25 °C



    70

    -40 °C < T < 125 °C



    100


    Iout


    Isink, Vout = VCC

    T = 25 °C

    4.3

    5.3



    mA

    -40 °C < T < 125 °C

    2.5




    Isource, Vout = 0 V

    T = 25 °C

    3.3

    4.3


    -40 °C < T < 125 °C

    2.5




    ICC

    Supply current, per channel, Vout = VCC/2, RL > 1 MΩ

    T = 25 °C


    220

    300


    μA

    -40 °C < T < 125 °C



    350

    AC performance

    GBP

    Gain bandwidth product


    RL = 10 kΩ, CL = 100 pF

    600

    800



    kHz

    Fu

    Unity gain frequency


    690


    ɸm

    Phase margin


    55


    Degrees

    Gm

    Gain margin


    9


    dB


    6/28 DocID023274 Rev 5


    Symbol

    Parameter

    Conditions

    Min.

    Typ.

    Max.

    Unit

    SR

    Slew rate

    RL = 10 kΩ, CL = 100 pF, Vout = 0.5 V to VCC - 0.5 V


    1


    V/μs


    en

    Equivalent input noise voltage density

    f = 1 kHz


    55



    nV/√Hz

    f = 10 kHz


    29


    ∫en

    Low-frequency peak-to- peak input noise

    Bandwidth, f = 0.1 to 10 Hz


    16


    µVpp


    THD+N

    Total harmonic distortion + noise

    Follower configuration, fin = 1 kHz, RL = 100 kΩ, Vicm = (VCC -1.5 V)/2,

    BW = 22 kHz, Vout = 1 Vpp



    0.004



    %


    Notes:

    (1)See Section 5.3: "Input offset voltage drift over temperature"

    (2)Guaranteed by design


    DocID023274 Rev 5 7/28


    Table 5: Electrical characteristics at VCC+ = 5 V with VCC- = 0 V, Vicm = VCC/2, Tamb = 25 ° C, and RL = 10 kΩ connected to VCC/2 (unless otherwise specified)

    Symbol

    Parameter

    Conditions

    Min.

    Typ.

    Max.

    Unit

    DC performance


    Vio


    Offset voltage

    TSX56xA, T = 25 °C



    600


    μV

    TSX56xA, -40 °C < T < 125 °C



    1800

    TSX56x, T = 25 °C



    1


    mV

    TSX56x, -40 °C < T < 125 °C



    2.2

    ΔVio/ΔT

    Input offset voltage drift

    -40 °C < T < 125 °C (1)


    2

    12

    µV/°C

    ΔVio

    Long-term input offset voltage drift

    T = 25 °C (2)


    5


    nV/

    √month


    Iib

    Input bias current, Vout = VCC/2

    T = 25 °C


    1

    100 (3)


    pA

    -40 °C < T < 125 °C


    1

    200 (3)


    Iio

    Input offset current, Vout = VCC/2

    T = 25 °C


    1

    100 (3)

    -40 °C < T < 125 °C


    1

    200 (3)


    CMR1

    Common mode rejection ratio, CMR = 20 log (ΔVic/ΔVio), Vic = -0.1 V to VCC - 1.5 V, Vout = VCC/2, RL > 1 MΩ

    T = 25 °C

    66

    84



    dB


    -40 °C < T < 125 °C


    63




    CMR2

    Common mode rejection ratio, CMR = 20 log (ΔVic/ΔVio), Vic = -0.1 V to VCC + 0.1 V, Vout = VCC/2, RL > 1 MΩ

    T = 25 °C

    50

    69



    -40 °C < T < 125 °C


    47




    Avd

    Large signal voltage gain, Vout = 0.5 V to (VCC - 0.5 V), RL > 1 MΩ

    T = 25 °C

    85



    -40 °C < T < 125 °C

    83




    VOH

    High-level output voltage, VOH = VCC - Vout

    RL = 10 kΩ, T = 25 °C



    70


    mV

    RL = 10 kΩ, -40 °C < T < 125 °C



    100


    VOL


    Low-level output voltage

    RL = 10 kΩ, T = 25 °C



    70

    RL = 10 kΩ, -40 °C < T < 125 °C



    100


    Iout


    Isink

    Vout = VCC, T = 25 °C

    11

    14



    mA

    Vout = VCC, -40 °C < T < 125 °C

    8




    Isource

    Vout = 0 V, T = 25 °C

    9

    12


    Vout = 0 V, -40 °C < T < 125 °C

    7




    ICC

    Supply current, per channel, Vout = VCC/2, RL > 1 MΩ

    T = 25 °C


    235

    350


    μA

    -40 °C < T < 125 °C



    400

    AC performance

    GBP

    Gain bandwidth product


    RL = 10 kΩ, CL = 100 pF

    700

    850



    kHz

    Fu

    Unity gain frequency


    730


    ɸm

    Phase margin


    55


    Degrees

    Gm

    Gain margin


    9


    dB


    8/28 DocID023274 Rev 5


    Symbol

    Parameter

    Conditions

    Min.

    Typ.

    Max.

    Unit

    SR

    Slew rate

    RL = 10 kΩ, CL = 100 pF, Vout = 0.5 V to VCC - 0.5 V


    1.1


    V/μs


    en

    Equivalent input noise voltage density

    f = 1 kHz


    55



    nV/√Hz

    f = 10 kHz


    29


    ∫en

    Low-frequency peak-to- peak input noise

    Bandwidth, f = 0.1 to 10 Hz


    15


    µVpp


    THD+N

    Total harmonic distortion + noise

    Follower configuration, fin = 1 kHz, RL = 100 kΩ, Vicm = (VCC -1.5 V)/2,

    BW = 22 kHz, Vout = 2 Vpp



    0.002



    %


    Notes:

    (1)See Section 5.3: "Input offset voltage drift over temperature"

    (2)Typical value is based on the Vio drift observed after 1000h at 125 °C extrapolated to 25 °C using the Arrhenius law and assuming an activation energy of 0.7 eV. The operational amplifier is aged in follower mode configuration.

    (3)Guaranteed by design


    DocID023274 Rev 5 9/28


    Table 6: Electrical characteristics at VCC+ = 16 V with VCC- = 0 V, Vicm = VCC/2, Tamb = 25 ° C, and RL = 10 kΩ connected to VCC/2 (unless otherwise specified)

    Symbol

    Parameter

    Conditions

    Min.

    Typ.

    Max.

    Unit

    DC performance


    Vio


    Offset voltage

    TSX56xA, T = 25 °C



    600


    μV

    TSX56xA, -40 °C < T < 125 °C



    1800

    TSX56x, T = 25 °C



    1


    mV

    TSX56x, -40 °C < T < 125 °C



    2.2

    ΔVio/ΔT

    Input offset voltage drift

    -40 °C < T < 125 °C (1)


    2

    12

    µV/°C

    ΔVio

    Long-term input offset voltage drift

    T = 25 °C (2)


    1.6


    nV/

    √month


    Iib

    Input bias current, Vout = VCC/2

    T = 25 °C


    1

    100 (3)


    pA

    -40 °C < T < 125 °C


    1

    200 (3)


    Iio

    Input offset current, Vout = VCC/2

    T = 25 °C


    1

    100 (3)

    -40 °C < T < 125 °C


    1

    200 (3)


    CMR1

    Common mode rejection ratio, CMR = 20 log (ΔVic/ΔVio), Vic = -0.1 V to VCC - 1.5 V, Vout = VCC/2, RL > 1 MΩ

    T = 25 °C

    76

    95



    dB


    -40 °C < T < 125 °C


    72




    CMR2

    Common mode rejection ratio, CMR = 20 log (ΔVic/ΔVio), Vic = -0.1 V to VCC + 0.1 V, Vout = VCC/2, RL > 1 MΩ

    T = 25 °C

    60

    78



    -40 °C < T < 125 °C


    56




    SVR

    Common mode rejection ratio, 20 log (ΔVCC/ΔVio), VCC = 3 V to 16 V,

    Vout = Vicm = VCC/2

    T = 25 °C

    76

    90



    -40 °C < T < 125 °C


    72




    Avd

    Large signal voltage gain, Vout = 0.5 V to (VCC - 0.5 V), RL > 1 MΩ

    T = 25 °C

    85



    -40 °C < T < 125 °C

    83




    VOH

    High-level output voltage, VOH = VCC - Vout

    RL = 10 kΩ, T = 25 °C



    70


    mV

    RL = 10 kΩ, -40 °C < T < 125 °C



    100


    VOL


    Low-level output voltage

    RL = 10 kΩ, T = 25 °C



    70

    RL = 10 kΩ, -40 °C < T < 125 °C



    100


    Iout


    Isink

    Vout = VCC, T = 25 °C

    40

    92



    mA

    Vout = VCC, -40 °C < T < 125 °C

    35




    Isource

    Vout = 0 V, T = 25 °C

    30

    90


    Vout = 0 V, -40 °C < T < 125 °C

    25




    ICC

    Supply current, per channel, Vout = VCC/2, RL > 1 MΩ

    T = 25 °C


    250

    360


    μA

    -40 °C < T < 125 °C



    400


    10/28 DocID023274 Rev 5


    Symbol

    Parameter

    Conditions

    Min.

    Typ.

    Max.

    Unit

    AC performance

    GBP

    Gain bandwidth product


    RL = 10 kΩ, CL = 100 pF

    750

    900



    kHz

    Fu

    Unity gain frequency


    750


    ɸm

    Phase margin


    55


    Degrees

    Gm

    Gain margin


    9


    dB

    SR

    Slew rate

    RL = 10 kΩ, CL = 100 pF, Vout = 0.5 V to VCC - 0.5 V


    1.1


    V/μs


    en

    Equivalent input noise voltage density

    f = 1 kHz


    48



    nV/√Hz

    f = 10 kHz


    27


    ∫en

    Low-frequency peak-to- peak input noise

    Bandwidth, f = 0.1 to 10 Hz


    15


    µVpp


    THD+N

    Total harmonic distortion + noise

    Follower configuration, fin = 1 kHz, RL = 100 kΩ, Vicm = (VCC -1.5 V)/2,

    BW = 22 kHz, Vout = 5 Vpp


    0.000

    5



    %


    Notes:

    (1)See Section 5.3: "Input offset voltage drift over temperature"

    (2)Typical value is based on the Vio drift observed after 1000h at 125 °C extrapolated to 25 °C using the Arrhenius law and assuming an activation energy of 0.7 eV. The operational amplifier is aged in follower mode configuration.

    (3)Guaranteed by design



    DocID023274 Rev 5 11/28


    Figure 4: Input offset voltage temperature coefficient distribution at VCC = 16 V, Vicm = 8 V

    Figure 2: Supply current vs. supply voltage at Vicm = VCC/2

  4. Electrical characteristic curves


    Figure 3: Input offset voltage distribution at VCC = 16 V and Vicm = 8 V


    Figure 5: Input offset voltage vs. input common-mode voltage at VCC = 12 V


    Figure 6: Input offset voltage vs. temperature at VCC = 16 V

    2500


    2000

    Limit for TSX56xA


    1500


    1000


    500


    0


    -500


    -1000


    -1500


    -2000

    VCC= 16V, Vicm = 8V


    -40 -20 0 20 40 60 80 100 120


    -2500

    Limit for TSX56x

    12/28 DocID023274 Rev 5


    -5








    0 -10









    -13

    -8








    -15









    -18

    -10

    -20


    Figure 9: Output current vs. output voltage at

    Figure 10: Bode diagram at VCC = 3.3 V


    180

    150

    120

    90

    60

    30

    0

    -30

    -60

    -90

    -120

    -150

    -180

    10 10 0 100 0 10000

    Frequency (kHz)


    Q)

    gi

    .c

    Q.

    VCC = 16 V

    100

    75

    T = 25 °e

    50


    0

    -25

    -50

    -75

    -100

    0.0 2.0 4.0 6.0 8.0 10.0 12.0 14.0 16.0

    Output voltage (V)





    45

    Figure 11: Bode diagram at VCC = 5 V

    180

    150

    120

    90

    60

    30 0

    0 QJ

    Ill

    -30 .acl:

    [J_

    -60

    -90

    -120

    -150

    -180

    10 100 1000 10000

    Frequency (kHz)


    ID

    :3,

    C

    " iii

    CJ


    45

    Figure 12: Bode diagram at VCC = 16 V

    180

    150

    120

    90

    60

    30 0

    0 Q)

    Ill

    -30 .acl:

    [J_

    -60

    -90

    -120

    -150


    10 100 1000 10000

    Frequency (kHz)


    30


    30


    15

    15

    ID




    C:

    0

    0

    "iii



    CJ

    -15

    -15



    -30

    -30



    -45

    -45


    0.0 0 .5 1 .0 1 .5 2 .0 2 .5 3.0 3 .5 4 .0 4.5 5.0

    Output voltage(V)

    ./

    ---j T = -40 "e

    I Source

    I V;d = 1 V

    /

    7

    .,,,.

    -

    -

    T - 25 °e 1

    -

    -8

    -5 I T - 125 °e I'--

    11

    :i

    u

    :i

    Ve e = 5 v

    ::,

    ll

    T - 125 °e r

    /

    -S

    C:

    ,,

    1T - 25 °e t"

    .,,,.

    ,/

    ,..

    IT= -40 °e

    ,/

    ,.

    ,,

    -1v : ..,

    S in k

    V;d

    20

    18 I

    15

    13

    10

    8

    5

    3

    0

    -3

    ,

    Figure 8: Output current vs. output voltage at VCC = 5 V

    0.0 0.5 1.0 1.5 2.0 2.5 3.0

    Output voltage (V)

    -3

    "S

    a.

    "S

    0

    0

    :i

    0

    5


    3

    .<s(

    'E

    Figure 7: Output current vs. output voltage at VCC = 3.3 V

    10


    8

    DocID023274 Rev 5 13/28


    Figure 13: Phase margin vs. capacitive load at VCC = 12 V


    Capacitive load (pF)

    Vicm(V)


    M 1 1 1 1M

    Vcc(V)

    -1.0


    -1.5

    M

    -0.5

    0.0

    i

    Q)

    1ii

    0.5

    I

    Figure 16: Slew rate vs. supply voltage


    1.5


    1.0

    0 2 3 4 5 6 7 B 9 10 11 12

    Vicm(V)

    -

    -

    120

    110

    100

    90

    BO

    70

    60

    50

    40

    30

    20

    10

    0

    "C>J

    <{

    iii'

    :!:!-

    Figure 15: Avd vs. input common-mode voltage at VCC = 12 V

    160

    150

    140

    130

    2 3 4 5 6 7 8 9 10 11 12

    0

    0

    I

    900

    800 ,., ---

    700


    600

    500

    400


    300

    200

    100

    c..

    III

    Cl

    N

    :i:

    Figure 14: GBP vs. input common-mode voltage at VCC = 12 V

    1000

    --

    0 50 100 150 200 250 300 350 400 450 500

    gj

    "

    '

    "'

    70

    65

    60 '

    55

    50

    45

    40

    35

    30

    25

    20

    15

    10

    5

    0

    c..

    .c:

    C:


    ttl

    E

    a,

    -

    :!:!-

    s

    da,i






















































    ....





















    ..........











    .........





    Vee 12 V, V;cm-Vrl-6V RL = 50 kQ, CL = 100 pF

    T = 25 ' C




    ....
































    r





















    \












    \


    -


    -











    Vee= 12 v, V;cm =Vrl





    -

    -

    RL = 10 kQ, CL= 100 pF

    I



    \..



    T = 25' C































































































    \






























    Vc c = 12 V, Vrl = 6 V RL = 10 kQ

    T = 25' C



















































































    I T = 25' C j

    I







    T 125' C

    I T = -40' C j



    I




    V;cm = Vrl = Vcci2

    RL = 10 kQ, CL= 100 pF

    V;n from 0.5 V to Vee - 0.5 V

    SR calculated from 1 V to VCC - 1 V


    -









    I T - 125' C j

    T = -40' C j





    I



    I T= 25' C







    1 Vcc=3.3V

    I T = 25' C











    I-


    f-

















    1 1 11





    ...



    ,


















    V;cm = 2.8 V I


    ....




    I'...






    ......



    I

    II J

    I

















    I V;cm - 1.65 V







    I I 11 1 1 1


    I


    Figure 17: Noise vs. frequency at VCC = 3.3 V Figure 18: Noise vs. frequency at VCC = 5 V


    .;- 10000

    5

    >E-

    .,


    .;- 10000


    1








    vcc = 5V

    I T = 25 'C I























    :-..










    I I





    ...






    "'-.





    V;cm - 4.5 V




    ......





    "'

    11lllJ:





    I V;cm-2.5V












    1 1 1 1 1 1 1 1








    E-

    .,

    iC:

    .a,,

    ·o

    C:

    a,

    1

    1000 -

    iC:

  5. Application information


    1. Operating voltages

      The amplifiers of the TSX56x and TSX56xA series can operate from 3 V to 16 V. Their parameters are fully specified at 3.3 V, 5 V, and 16 V power supplies. However, the parameters are very stable in the full VCC range. Additionally, the main specifications are guaranteed in extended temperature ranges from -40 to 125 ° C.


    2. Rail-to-rail input

      The TSX56x and TSX56xA devices are built with two complementary PMOS and NMOS input differential pairs. The devices have a rail-to-rail input, and the input common mode range is extended from (VCC-) - 0.1 V to (VCC+) + 0.1 V.

      However, the performance of these devices is clearly optimized for the PMOS differential pairs (which means from (VCC-) - 0.1 V to (VCC+) - 1.5 V).

      Beyond (VCC+) - 1.5 V, the operational amplifiers are still functional but with degraded performance, as can be observed in the electrical characteristics section of this datasheet (mainly Vio and GBP). These performances are suitable for a number of applications that need to be rail-to-rail.

      The devices are designed to prevent phase reversal.


    3. Input offset voltage drift over temperature

      The maximum input voltage drift over the temperature variation is defined as the offset variation related to the offset value measured at 25 °C. The operational amplifier is one of the main circuits of the signal conditioning chain, and the amplifier input offset is a major contributor to the chain accuracy. The signal chain accuracy at 25 °C can be compensated during production at application level. The maximum input voltage drift over temperature enables the system designer to anticipate the effects of temperature variations.

      The maximum input voltage drift over temperature is computed using Equation 1.

      Equation 1


      ∆Vio = ma x Vio T

      Vio 25 °C

      ∆T T 25 °C


      Where T = -40 °C and 125 °C.

      The datasheet maximum value is guaranteed by measurements on a representative sample size ensuring a Cpk (process capability index) greater than 2.



      16/28 DocID023274 Rev 5


    4. Long term input offset voltage drift

      To evaluate product reliability, two types of stress acceleration are used: Voltage acceleration, by changing the applied voltage

      Temperature acceleration, by changing the die temperature (below the maximum

      junction temperature allowed by the technology) with the ambient temperature.

      The voltage acceleration has been defined based on JEDEC results, and is defined using

      Equation 2.

      Equation 2


      FV

      A = eβ . VS VU


      Where:

      AFV is the voltage acceleration factor

      β is the voltage acceleration constant in 1/V, constant technology parameter (β = 1) VS is the stress voltage used for the accelerated test

      VU is the voltage used for the application

      The temperature acceleration is driven by the Arrhenius model, and is defined in

      Equation 3.

      Equation 3



      Where:


      AFT

      E

      a .

      ---

      k

      = e

      1 1

      TU TS

      AFT is the temperature acceleration factor

      Ea is the activation energy of the technology based on the failure rate k is the Boltzmann constant (8.6173 x 10-5 eV.K-1)

      TU is the temperature of the die when VU is used (K)

      TS is the temperature of the die under temperature stress (K)

      The final acceleration factor, AF, is the multiplication of the voltage acceleration factor and the temperature acceleration factor (Equation 4).

      Equation 4


      AF = AFT × AFV


      AF is calculated using the temperature and voltage defined in the mission profile of the product. The AF value can then be used in Equation 5 to calculate the number of months of use equivalent to 1000 hours of reliable stress duration.

      Equation 5


      Months = AF × 1000 h × 12 months / 24 h × 365.25 days


      DocID023274 Rev 5 17/28


      To evaluate the op amp reliability, a follower stress condition is used where VCC is defined as a function of the maximum operating voltage and the absolute maximum rating (as recommended by JEDEC rules).

      The Vio drift (in µV) of the product after 1000 h of stress is tracked with parameters at different measurement conditions (see Equation 6).

      Equation 6


      VCC = maxVop with Vicm = VCC 2


      The long term drift parameter (ΔVio), estimating the reliability performance of the product, is obtained using the ratio of the Vio (input offset voltage value) drift over the square root of the calculated number of months (Equation 7).

      Equation 7



      ∆Vio =

      Viodr ift month s


      Where Vio drift is the measured drift value in the specified test conditions after 1000 h stress duration.


    5. PCB layouts

      For correct operation, it is advised to add 10 nF decoupling capacitors as close as possible to the power supply pins.


    6. Macromodel

      Accurate macromodels of the TSX56x, TSX56xA devices are available on the STMicroelectronics’ website at: www.st.com. These models are a trade-off between accuracy and complexity (that is, time simulation) of the TSX56x and TSX56xA operational amplifiers. They emulate the nominal performance of a typical device within the specified operating conditions mentioned in the datasheet. They also help to validate a design approach and to select the right operational amplifier, but they do not replace on-board measurements.


      18/28 DocID023274 Rev 5


  1. Package information

    In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com.

    ECOPACK® is an ST trademark.


    DocID023274 Rev 5 19/28


    1. SOT23-5 package information

      Figure 23: SOT23-5 package outline


      Table 7: SOT23-5 mechanical data


      Ref.

      Dimensions

      Millimeters

      Inches

      Min.

      Typ.

      Max.

      Min.

      Typ.

      Max.

      A

      0.90

      1.20

      1.45

      0.035

      0.047

      0.057

      A1



      0.15



      0.006

      A2

      0.90

      1.05

      1.30

      0.035

      0.041

      0.051

      B

      0.35

      0.40

      0.50

      0.014

      0.016

      0.020

      C

      0.09

      0.15

      0.20

      0.004

      0.006

      0.008

      D

      2.80

      2.90

      3.00

      0.110

      0.114

      0.118

      D1


      1.90



      0.075


      e


      0.95



      0.037


      E

      2.60

      2.80

      3.00

      0.102

      0.110

      0.118

      F

      1.50

      1.60

      1.75

      0.059

      0.063

      0.069

      L

      0.10

      0.35

      0.60

      0.004

      0.014

      0.024

      K

      0 degrees


      10 degrees

      0 degrees


      10 degrees


      20/28 DocID023274 Rev 5


    2. DFN8 2x2 package information

      Figure 24: DFN8 2x2 package outline


      Table 8: DFN8 2x2 mechanical data


      Ref.

      Dimensions

      Millimeters

      Inches

      Min.

      Typ.

      Max.

      Min.

      Typ.

      Max.

      A

      0.70

      0.75

      0.80

      0.028

      0.030

      0.031

      A1

      0.00

      0.02

      0.05

      0.000

      0.001

      0.002

      b

      0.15

      0.20

      0.25

      0.006

      0.008

      0.010

      D


      2.00



      0.079


      E


      2.00



      0.079


      e


      0.50



      0.020


      L

      0.045

      0.55

      0.65

      0.018

      0.022

      0.026


      DocID023274 Rev 5 21/28


    3. MiniSO8 package information

      Figure 25: MiniSO8 package outline


      Table 9: MiniSO8 mechanical data


      Ref.

      Dimensions

      Millimeters

      Inches

      Min.

      Typ.

      Max.

      Min.

      Typ.

      Max.

      A



      1.1



      0.043

      A1

      0


      0.15

      0


      0.006

      A2

      0.75

      0.85

      0.95

      0.030

      0.033

      0.037

      b

      0.22


      0.40

      0.009


      0.016

      c

      0.08


      0.23

      0.003


      0.009

      D

      2.80

      3.00

      3.20

      0.11

      0.118

      0.126

      E

      4.65

      4.90

      5.15

      0.183

      0.193

      0.203

      E1

      2.80

      3.00

      3.10

      0.11

      0.118

      0.122

      e


      0.65



      0.026


      L

      0.40

      0.60

      0.80

      0.016

      0.024

      0.031

      L1


      0.95



      0.037


      L2


      0.25



      0.010


      k



      ccc



      0.10



      0.004


      22/28 DocID023274 Rev 5


    4. QFN16 3x3 package information

      Figure 26: QFN16 3x3 package outline


      A

      D


      B

      INDEX AREA

      E

      ( D/ 2x E/ 2)


      C

      aaa

      aaa

      C 2x

      2x


      TOP VI EW


      C

      ccc

      A

      A1

      C



      eee

      C


      SI DE VIEW


      e

      L b


      SEATING PLANE

      5 8 bbb

      C A B

      bbb C


      4 9


      1 12


      Pin#1 ID

      R0. 11

      16 13


      BOTTOM VIEW



      DocID023274 Rev 5 23/28


      Table 10: QFN16 3x3 mechanical data


      Ref.

      Dimensions

      Millimeters

      Inches

      Min.

      Typ.

      Max.

      Min.

      Typ.

      Max.

      A

      0.50


      0.65

      0.020


      0.026

      A1

      0


      0.05

      0


      0.002

      b

      0.18

      0.25

      0.30

      0.007

      0.010

      0.012

      D


      3.00



      0.118


      E


      3.00



      0.118


      e


      0.50



      0.020


      L

      0.30


      0.50

      0.012


      0.020

      aaa



      0.15



      0.006

      bbb



      0.10



      0.004

      ccc



      0.10



      0.004

      ddd



      0.05



      0.002

      eee



      0.08



      0.003


      24/28 DocID023274 Rev 5


    5. TSSOP14 package information

      Figure 27: TSSOP14 package outline


      aaa


      Table 11: TSSOP14 mechanical data


      Ref.

      Dimensions

      Millimeters

      Inches

      Min.

      Typ.

      Max.

      Min.

      Typ.

      Max.

      A



      1.20



      0.047

      A1

      0.05


      0.15

      0.002

      0.004

      0.006

      A2

      0.80

      1.00

      1.05

      0.031

      0.039

      0.041

      b

      0.19


      0.30

      0.007


      0.012

      c

      0.09


      0.20

      0.004


      0.0089

      D

      4.90

      5.00

      5.10

      0.193

      0.197

      0.201

      E

      6.20

      6.40

      6.60

      0.244

      0.252

      0.260

      E1

      4.30

      4.40

      4.50

      0.169

      0.173

      0.176

      e


      0.65



      0.0256


      L

      0.45

      0.60

      0.75

      0.018

      0.024

      0.030

      L1


      1.00



      0.039


      k



      aaa



      0.10



      0.004


      DocID023274 Rev 5 25/28


  2. Ordering information

    Table 12: Order codes

    Order code

    Temperature range

    Channel number

    Package

    Packaging

    Marking

    TSX561ILT


    -40 to 125 °C

    1

    SΟΤ23-5


    Tape and reel


    K23

    TSX562IQ2T


    2

    DFN8 2x2

    TSX562IST

    MiniSO8

    TSX564IQ4T


    4

    QFN16 3x3

    TSX564IPT

    TSSOP14

    TSX5641

    TSX561IYLT (1)


    -40 to 125 °C

    automotive grade

    1

    SΟΤ23-5


    K116

    TSX562IYST (1)

    2

    MiniSO8

    TSX564IYPT (1)

    4

    TSSOP14

    TSX5641Y

    TSX561AILT


    -40 to 125 °C

    1

    SΟΤ23-5


    K117

    TSX562AIST

    2

    MiniSO8

    TSX564AIPT

    4

    TSSOP14

    TSX564AI

    TSX561AIYLT (1)


    -40 to 125 °C

    automotive grade

    1

    SΟΤ23-5


    K118

    TSX562AIYST (1)

    2

    MiniSO8

    TSX564AIYPT (1)

    4

    TSSOP14

    TSX564AIY


    Notes:

    (1)Qualified and characterized according to AEC Q100 and Q003 or equivalent, advanced screening according to AEC Q001 & Q 002 or equivalent



    26/28 DocID023274 Rev 5


  3. Revision history


Table 13: Document revision history


Date

Revision

Changes

06-Aug-2012

1

Initial release.


18-Sep-2012


2

Added TSX562, TSX564, TSX562A, and TSX564A devices.

Updated Features, Description, Figure 1, Table 1 (added DFN8, MiniSO8, QFN16, and TSSOP14 package).

Updated Table 1 (updated ESD MM values).

Updated Table 4 and Table 5 (added footnotes), Section 5 (added Figure 24 to Figure 28 and Table 8 to Table 12), Table 13 (added dual and quad devices).

Minor corrections throughout document.


23-May-2013


3

Replaced the silhouette, pinout, package diagram, and mechanical data of the DFN8 2x2 and QFN16 3x3 packages.

Added Benefits and Related products.

Table 1: updated Rthja values and added Rthjc values for DFN8 2x2 and QFN16 3x3. Updated Section 4.3, Section 4.4, and Section 4.6

Replaced Figure 23: SOT23-5 package mechanical drawing and Table 7: SOT23-5 package mechanical data.


09-Aug-2013


4

Added SO8 package for dual version TSX562 and TSX562A. Table 2: updated for SO8 package

Table 13: added order codes TSX562IDT, TSX562IYDT, TSX562AIDT, TSX562AIYDT; updated automotive grade status.


07-Feb-2017


5

Removed SO8 package

Table 8: "DFN8 2x2 mechanical data": removed "N"

Table 11: "TSSOP14 mechanical data": added "L" and " L1" in inches; updated "aaa" in inches.

Table 12: "Order codes": removed TSX562IDT, TSX562IYDT, TSX562AIDT, TSX562AIYDT.

Updated terminology


DocID023274 Rev 5 27/28


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ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners.


Information in this document supersedes and replaces information previously supplied in any prior versions of this document.


© 2017 STMicroelectronics – All rights reserved


28/28 DocID023274 Rev 5

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TSX561AILT TSX561ILT TSX564IPT TSX564AIPT TSX562IST TSX562AIST TSX562IQ2T TSX564IQ4T TSX562IYST TSX561AIYLT TSX562AIYST TSX561IYLT TSX564AIYPT TSX564IYPT