DESCRIPTION
This archive contains the benchmark set used in [1] and the detailed
experimental results. All hypergraphs are in the hMetis benchmark format [8].
HYPERGRAPHS
Instances derived from the ISPD98 Circuit Benchmark Suite [2] can be found in
the ISPD98_hypergraphs.tar.gz archive. The instances derived from the
international SAT Competition 2014 [3] are contained in sat14_application_track_hypergraphs.tar.gz.
Archive uf_spm_hypergraphs.tar.gz contains the hypergraphs derived from the
University of Florida Sparse Matrix Collection [4].
Properties of the hypergraphs can be found in the following files:
- properties_ISPD98_hypergraphs.pdf
- properties_sat14_hypergraphs.pdf
- properties_sparse_matrix_hypergraphs.pdf
BENCHMARK RESULTS
We provide detailed per-instance results for all hypergraphs that were used in
[1] to compare our algorithm to the state-of-the-art hypergraph partitioners
hMetis [5,6] and PaToH [7]. The results are provided in human-
and machine-readable form (detailed_per_instance_results_*.csv). Instances that have been
excluded from the final evaluation for e=0.03 are shown in excluded_instances.pdf.
In order to evaluate different imbalance thresholds (1% and 10%),
we selected a subset of 100 hypergaphs (ibm09-ibm18, 30 randomly chosen sat hypergraphs,
60 randomly chosen SPM hypergraphs). The hypergraphs that were used in these experiments
can be found in instances_used_for_imbalance_experiments.csv. Detailed per-instance results
can be found in the detailed_per_instance_results_subset_* files.
REFERENCES
[1] S. Schlag, V. Henne, T. Heuer, H. Meyerhenke, P. Sanders, C. Schulz. k-way Hypergraph Partitioning via n-Level Recursive Bisection
[2] C. J. Alpert. The ISPD98 Circuit Benchmark Suite. In Proc. of the 1998 Int. Symp. on Physical Design, pages 80–85, New York, 1998. ACM.
[3] A. Belov, D. Diepold, M. Heule, and M. Järvisalo. The SAT Competition 2014. http://www.satcompetition.org/2014/, 2014.
[4] T. A. Davis and Y. Hu. The University of Florida Sparse Matrix Collection. ACM Trans. Math. Softw.,38(1):1:1–1:25, 2011.
[5] G. Karypis, R. Aggarwal, V. Kumar, and S. Shekhar. Multilevel Hypergraph Partitioning: Applications in VLSI Domain. IEEE Trans. on Very Large Scale Integration VLSI Systems, 7(1):69–79, 1999.
[6] G. Karypis and V. Kumar. Multilevel K-way Hypergraph Partitioning. In Proc. 36th ACM/IEEE Design Automation Conference, pages 343–348. ACM, 1999.
[7] Ü. V. Catalyürek and C. Aykanat. Hypergraph-partitioning-based decomposition for parallel sparse-matrix vector multiplication. IEEE Transactions on Parallel and Distributed Systems, 10(7):673–693, Jul 1999.
[8] http://glaros.dtc.umn.edu/gkhome/fetch/sw/hmetis/manual.pdf