Published January 7, 2019 | Version v1
Conference paper Open

Time-division Multiplexing Automata Processor

  • 1. Laboratory of Computer Engineering, Delft University of Technology, Delft (NL)

Description

Automata Processor (AP) is a special implementation of non-deterministic finite automata that performs pattern matching by exploring parallel state transitions. The implementation typically contains a hierarchical switching network, causing long latency. This paper proposes a methodology to split such a hierarchical switching network into multiple pipelined stages, making it possible to process several input sequences in parallel by using time-division multiplexing. We use a new resistive RAM based AP (instead of known DRAM or SRAM based) to illustrate the potential of our method. The experimental results show that our approach increases the throughput by almost a factor of 2 at a cost of marginal area overhead.

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Additional details

Funding

MNEMOSENE – Computation-in-memory architecture based on resistive devices 780215
European Commission