Catalina Morales
catalina.morales@email.com | +57 310 456 7823 | Calle 85 No. 12-34, Bogotá, Colombia | https://www.linkedin.com/in/catalinamorales

PROFESSIONAL SUMMARY

Design Engineer with expertise in analog/mixed-signal IC design, layout, and verification. Proven track record in developing complex integrated circuits from concept through tape-out, with strong proficiency in Cadence Virtuoso, physical verification, and characterization methodologies. Experienced in collaborating with cross-functional teams to deliver high-performance semiconductor solutions.

PROFESSIONAL EXPERIENCE

Design Engineer
NeoSilicon Technologies, Medellín, Colombia
June 2022 – Present

• Design and implement analog and mixed-signal circuits for advanced semiconductor products using Cadence Virtuoso, achieving 15% improvement in power efficiency over previous generation designs
• Perform comprehensive physical verification including DRC and LVS checks, reducing tape-out iterations by 30% through meticulous pre-silicon validation
• Conduct electrical characterization and modeling of circuit blocks across process corners and temperature ranges to ensure robust performance
• Collaborate with layout engineers to optimize circuit performance while meeting area and power constraints for high-volume production
• Develop Python and Perl scripts to automate design verification workflows, reducing verification cycle time by 40%

Junior Design Engineer
Circuitos Avanzados S.A., Bogotá, Colombia
August 2019 – May 2022

• Assisted in the design and simulation of analog circuit blocks including amplifiers, voltage references, and bias circuits for mixed-signal ICs
• Executed layout versus schematic verification and design rule checking for multiple tape-outs, ensuring compliance with foundry specifications
• Performed post-layout simulations and parasitic extraction to validate circuit performance and identify potential design issues
• Utilized LabVIEW for automated test equipment development and characterization of silicon prototypes
• Documented design specifications, test procedures, and characterization results using LaTeX for internal and customer-facing deliverables

Design Intern
MicroElectrónica Colombiana, Cali, Colombia
May 2018 – August 2018

• Supported senior engineers in schematic capture and simulation of analog circuit blocks using Cadence Virtuoso
• Conducted literature review and competitive analysis of low-power design techniques for battery-operated applications
• Assisted in laboratory measurements and data analysis for prototype characterization using oscilloscopes and spectrum analyzers
• Created technical presentations and reports summarizing design trade-offs and measurement results

EDUCATION

Master of Science in Electrical Engineering
Universidad Nacional de Colombia, Bogotá, Colombia
Graduated: May 2019
Focus: Analog/Mixed-Signal IC Design

Bachelor of Science in Electrical Engineering
Pontificia Universidad Javeriana, Bogotá, Colombia
Graduated: May 2017
Minor: Electronics

TECHNICAL SKILLS

IC Design Tools: Cadence Virtuoso, Design Rule Checking (DRC), Layout Versus Schematic (LVS), Physical Verification
Circuit Design: Analog Design, Mixed-Signal Design, Characterization, Modeling
Programming Languages: Python, Perl, C, C++, Verilog, MATLAB, PHP
Test & Measurement: LabVIEW
Operating Systems: Linux, Windows
Documentation: LaTeX, Microsoft Office
Other: Communication, Electronics, Electrical Engineering fundamentals

CERTIFICATIONS

Cadence Custom IC Design Certification – 2020

LANGUAGES

English (Fluent)
Spanish (Native)