Delay Reduction in Three operand binary adder

Today's world places a high value on a processor's
ability to operate its arithmetic logic units (ALU). The delay in
processing an output is used to gauge the efficiency of the
Arithmetic Logic Units (ALU). Addition is the fundamental
operational unit of all arithmetic logic units (ALUs). So, using
parallel prefix three operand binary adders, which are more
efficient than other adders and the Propagator generator,
which has a great delay performance, we have presented an
addition technique in this study. The suggested adder
outperforms the current three operand parallel prefix adder in
terms of hardware efficiency (1.1534) and delay efficiency
(1.07291).