In the ever-evolving landscape of digital systems, the need for efficient and high-performance comparators has become increasingly vital. This paper presents the design and implementation of an N-bit comparator circuit, where N represents the number of bits for comparison. The comparator is a crucial component in digital systems, finding applications in areas such as arithmetic operations, data sorting, and decision-making processes. The proposed N-bit comparator leverages advanced logic technologies to achieve enhanced speed, reduced power consumption, and improved reliability. The design incorporates a combination of parallel comparison architecture and optimized logic gates to ensure efficient operation for multi-bit inputs.
", "languages": [ { "id": "eng", "title": { "en": "English" } } ], "publication_date": "2024-06-12", "publisher": "Zenodo", "references": [ { "reference": "1.\tTang, X., Shen, L., Kasap, B., Yang, X., Shi, W., Mukherjee, A., ... & Sun, N. (2020). An energy-efficient comparator with dynamic floating inverter amplifier. IEEE Journal of Solid-State Circuits, 55(4), 1011-1022." }, { "reference": "2.\tChua, C., Kumar, R. B. N., & Sireesha, B. (2017). Design and analysis of low-power and area efficient N-bit parallel binary comparator. Analog Integrated Circuits and Signal Processing, 92(2), 225-231." }, { "reference": "3.\t Tyagi, P., & Pandey, R. (2020). High\u2010speed and area\u2010efficient scalable N\u2010bit digital comparator. IET Circuits, Devices & Systems, 14(4), 450-458." }, { "reference": "4.\t\"Rajora, R., Sharma, K., & Sharma, A. (2023, April). 1-Bit Comparator Designed by Multithreshold FinFET based Sleep Transistor Technique in 18nm. In 2023 International Conference on Distributed Computing and Electrical Circuits and Electronics (ICDCECE) (pp. 1-5). IEEE." }, { "reference": "5.\tZahoor, F., Hussin, F. A., Khanday, F. A., Ahmad, M. R., Nawi, I. M., & Gupta, S. (2021, July). Carbon nanotube field effect transistor and resistive random access memory based 2-bit ternary comparator. In 2020 8th International Conference on Intelligent and Advanced Systems (ICIAS) (pp. 1-6). IEEE." }, { "reference": "6.\t\"Karunakaran, S., Pavan, K., & Reddy, P. R. (2021, December). VLSI Implementation of a High Speed and Area efficient N-bit Digital CMOS Comparator. In 2021 Second International Conference on Smart Technologies in Computing, Electrical and Electronics (ICSTCEE) (pp. 1-4). IEEE." } ], "resource_type": { "id": "publication-article", "title": { "de": "Zeitschriftenartikel", "en": "Journal article" } }, "rights": [ { "description": { "en": "The Creative Commons Attribution license allows re-distribution and re-use of a licensed work on the condition that the creator is appropriately credited." }, "icon": "cc-by-icon", "id": "cc-by-4.0", "props": { "scheme": "spdx", "url": "https://creativecommons.org/licenses/by/4.0/legalcode" }, "title": { "en": "Creative Commons Attribution 4.0 International" } } ], "subjects": [ { "subject": "digital, systems, design, comparator, comparison" } ], "title": "Design and Implementation of Comparator circuit using Advanced Logic Technologies" }, "parent": { "access": { "owned_by": { "user": "109382" }, "settings": { "accept_conditions_text": null, "allow_guest_requests": false, "allow_user_requests": false, "secret_link_expiration": 0 } }, "communities": { "default": "cc506192-c304-4290-a3db-482a17492334", "entries": [ { "access": { "member_policy": "open", "members_visibility": "public", "record_submission_policy": "open", "review_policy": "open", "visibility": "public" }, "children": { "allow": false }, "created": "2020-06-26T10:39:10.818761+00:00", "custom_fields": {}, "deletion_status": { "is_deleted": false, "status": "P" }, "id": "cc506192-c304-4290-a3db-482a17492334", "links": {}, "metadata": { "curation_policy": "", "page": "Our journals are peer reviewed, each of which broadly contributes to
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