Bohan Yang
Vladimir Rozic
Milos Grujic
Nele Mentens
Ingrid Verbauwhede
2017-10-20
<p>Applications of true random number generators (TRNGs) span from art to numerical computing and system<br>
security. In cryptographic applications, TRNGs are used for generating new keys, nonces and masks. For this reason, a TRNG is an essential building block and often a point of failure for embedded security systems. One type of primitives that are widely used as source of randomness are ring oscillators. For a ring-oscillator-based TRNG, the true randomness originates from its timing jitter. Therefore, determining the jitter strength is essential to estimate the quality of a TRNG. In this paper, we propose a method to measure the jitter strength of a ring oscillator implemented on an FPGA. The fast tapped delay chain is utilized to perform the on-chip measurement with a high resolution. The proposed method is implemented on<br>
both a Xilinx FPGA and an Intel FPGA. Fast carry logic components on different FPGAs are used to implement the fast delay line. This carry logic component is designed to be fast and has dedicated routing, which enables a precise measurement. The differential structure of the delay chain is used to thwart<br>
the influence of undesirable noise from the measurement. The proposed methodology can be applied to other FPGA families and ASIC designs.</p>
https://doi.org/10.5281/zenodo.897897
oai:zenodo.org:897897
Zenodo
https://zenodo.org/communities/hector
https://zenodo.org/communities/eu
https://doi.org/10.5281/zenodo.897896
info:eu-repo/semantics/openAccess
Creative Commons Attribution Non Commercial No Derivatives 4.0 International
https://creativecommons.org/licenses/by-nc-nd/4.0/legalcode
AsianHOST, Asian Hardware Oriented Security and Trust Symposium, Bejing, China, 19-20 October, 2017
On-chip jitter measurement for true random number generators
info:eu-repo/semantics/conferencePaper