Conference paper Open Access

The Monte Carlo PUF

Vladimir Rozic; Bohan Yang; Jo Vliegen; Nele Mentens; Ingrid Verbauwhede


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  <dc:creator>Vladimir Rozic</dc:creator>
  <dc:creator>Bohan Yang</dc:creator>
  <dc:creator>Jo Vliegen</dc:creator>
  <dc:creator>Nele Mentens</dc:creator>
  <dc:creator>Ingrid Verbauwhede</dc:creator>
  <dc:date>2017-09-06</dc:date>
  <dc:description>Physically  unclonable  functions  are  used  for  IP protection,  hardware  authentication  and  supply  chain  security. While many PUF constructions have been put forward in the past decade,  only  few  of  them  are  applicable  to  FPGA  platforms. Strict  constraints  on  the  placement  and  routing  are  the  main disadvantages  of  the  existing  PUFs  on  FPGAs,  because  they place  a  high  effort  on  the  designer.  In  this  paper  we  propose a  new  delay-based  PUF  construction  called  Monte  Carlo  PUF, that  does  not  require  low-level  placement  and  routing  control. This construction relies on the on-chip Monte Carlo method that is applied for measuring the delays of logic elements in order to extract  a  unique  device  fingerprint.  The  proposed  construction allows a trade-off between the evaluation time and the error rate.
The Monte Carlo PUF is implemented and evaluated on Xilinx Spartan-6 FPGAs.

 </dc:description>
  <dc:identifier>https://zenodo.org/record/897887</dc:identifier>
  <dc:identifier>10.5281/zenodo.897887</dc:identifier>
  <dc:identifier>oai:zenodo.org:897887</dc:identifier>
  <dc:relation>info:eu-repo/grantAgreement/EC/H2020/644052/</dc:relation>
  <dc:relation>doi:10.5281/zenodo.897886</dc:relation>
  <dc:relation>url:https://zenodo.org/communities/hector</dc:relation>
  <dc:rights>info:eu-repo/semantics/openAccess</dc:rights>
  <dc:rights>http://creativecommons.org/licenses/by-nc-nd/4.0/legalcode</dc:rights>
  <dc:title>The Monte Carlo PUF</dc:title>
  <dc:type>info:eu-repo/semantics/conferencePaper</dc:type>
  <dc:type>publication-conferencepaper</dc:type>
</oai_dc:dc>
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