Conference paper Open Access

The Monte Carlo PUF

Vladimir Rozic; Bohan Yang; Jo Vliegen; Nele Mentens; Ingrid Verbauwhede

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  "publisher": "Zenodo", 
  "DOI": "10.5281/zenodo.897887", 
  "title": "The Monte Carlo PUF", 
  "issued": {
    "date-parts": [
  "abstract": "<p>Physically\u00a0 unclonable\u00a0 functions\u00a0 are\u00a0 used\u00a0 for\u00a0 IP protection,\u00a0 hardware\u00a0 authentication\u00a0 and\u00a0 supply\u00a0 chain\u00a0 security. While many PUF constructions have been put forward in the past decade,\u00a0 only\u00a0 few\u00a0 of\u00a0 them\u00a0 are\u00a0 applicable\u00a0 to\u00a0 FPGA\u00a0 platforms. Strict\u00a0 constraints\u00a0 on\u00a0 the\u00a0 placement\u00a0 and\u00a0 routing\u00a0 are\u00a0 the\u00a0 main disadvantages\u00a0 of\u00a0 the\u00a0 existing\u00a0 PUFs\u00a0 on\u00a0 FPGAs,\u00a0 because\u00a0 they place\u00a0 a\u00a0 high\u00a0 effort\u00a0 on\u00a0 the\u00a0 designer.\u00a0 In\u00a0 this\u00a0 paper\u00a0 we\u00a0 propose a\u00a0 new\u00a0 delay-based\u00a0 PUF\u00a0 construction\u00a0 called\u00a0 Monte\u00a0 Carlo\u00a0 PUF, that\u00a0 does\u00a0 not\u00a0 require\u00a0 low-level\u00a0 placement\u00a0 and\u00a0 routing\u00a0 control. This construction relies on the on-chip Monte Carlo method that is applied for measuring the delays of logic elements in order to extract\u00a0 a\u00a0 unique\u00a0 device\u00a0 fingerprint.\u00a0 The\u00a0 proposed\u00a0 construction allows a trade-off between the evaluation time and the error rate.<br>\nThe Monte Carlo PUF is implemented and evaluated on Xilinx Spartan-6 FPGAs.</p>\n\n<p>\u00a0</p>", 
  "author": [
      "family": "Vladimir Rozic"
      "family": "Bohan Yang"
      "family": "Jo Vliegen"
      "family": "Nele Mentens"
      "family": "Ingrid Verbauwhede"
  "type": "paper-conference", 
  "id": "897887"
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