Logic gates with a single graphene transistor

The operation of four basic two-input logic gates fabricated with a single graphene transistor is demonstrated. Single-transistor operation is obtained in a circuit designed to exploit the charge neutrality point of graphene to perform Boolean logic. The type of logic function is selected by offset of the input digital signals. The merits and limitations of the fabricated gates are assessed by comparing their performance with that of conventional logic gates. © 2009 American Institute of Physics. DOI: 10.1063/1.3079663

The exponential decrease in the minimum feature size of integrated circuits 1 initiated a search for novel materials and devices at the nanometer scale. Nanoelectronic devices based on carbon nanostructures, such as carbon nanotubes ͑CNTs͒ and graphene, are a promising alternative to Si-based devices due to their small size and extraordinary properties. 2,3 Although CNTs are now well-established as efficient channels for field-effect transistors ͑FETs͒ ͑Ref. 4͒ they have not been successfully implemented in large-scale integration electronics mainly due to a difficulty in their precise positioning on a chip. 5 Graphene, if epitaxially grown, 6,7 transfer printed, 8 or deposited from a solution 9 on a large wafer, does not suffer from this limitation as it can be patterned by Si-compatible lithographic techniques. 10 The high mobility of carriers in graphene 11,12 could allow fabrication of transistors operational in a sub-10 nm regime in which the ultimate limits of Si technology would probably be reached. 13 However, intrinsic graphene is a semimetal, 14 implying a very small current on/off ratio of graphene transistors. 15 If graphene devices were to replace conventional Si devices, new approaches in bandgap engineering 10,[16][17][18] or circuit design would be needed, with the most attractive possibility being to implement the same functionality with fewer transistors. [19][20][21][22] Here we demonstrate the latter approach by realizing four basic logic gates with just one graphene transistor. This was obtained by exploiting the existence of a maximum in the transfer resistance of a graphene transistor. Most of the fabricated logic gates, such as the exclusive OR ͑XOR͒ gate, require at least four conventional FETs. 23,24 The fabricated device is shown in Fig. 1. Graphene flakes were deposited by mechanical exfoliation of highly oriented pyrolitic graphite on a highly doped Si substrate with 300 nm of thermally grown dry SiO 2 on top. 14 The flakes were exfoliated by wafer dicing tape as it leaves almost no adhesive residue on the substrate. The flake shown in Fig. 1 was identified as monolayer graphene by Raman spectroscopy. 25 The flake was contacted by four Cr͑5 nm͒/ Au͑50 nm͒ electrodes patterned by e-beam lithography. The electrical measurements were performed in a conventional FET configuration, with two neighboring electrodes acting as source and drain contacts, the other two electrodes not con-nected, and metal contact evaporated on the back of the substrate as gate.
The measured resistance R between the source and drain contacts on the monolayer graphene as a function of the applied back-gate voltage V G is shown in Fig. 2. Monolayer graphene not subjected to further treatment generally shows p-type behavior at small gate voltages, which has been attributed to hole doping by physisorbed ambient impurities such as water 14 and oxygen. 26 In doped samples the transition between p-and n-type conduction occurs not at zero but at a positive gate voltage, as seen in Fig. 2 where the resistance peak is shifted to V G = 22.85 V. Due to a small overlap between valence and conduction bands and formation of electron-hole puddles, 27 graphene undergoes ambipolar transition without carrier depletion, in contrast with semiconducting CNTs. 28 As a consequence, graphene transistors cannot be turned off and they do not exhibit the drain current saturation effect as conventional FETs do. 29 Instead, they stay in the Ohmic regime even at very large drain biases, functioning as simple voltage controlled resistors whose resistance R depends solely on the applied gate voltage V G . In addition, the change in drain current I D caused by the change in the gate voltage V G is relatively small. In the investigated drain-source ͑two-probe͒ configuration, this change is further suppressed because the resistance R includes also lead and contact resistances that limit the maximum drain current at a given drain voltage V D . 30 In the investigated sample, the total contact resistance of all four electrodes was found to be 2.2 k⍀. In order to evaluate the upper limit of performance of the suggested logic gates, samples were measured at cryogenic temperatures. At higher temperatures the principle of a͒ Electronic mail: roman.sordan@como.polimi.it. operation will not be changed even though the change in resistance will be damped.

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The existence of a maximum in the transfer curve R versus V G can be exploited to design different logic gates with just one graphene transistor, as shown in Fig. 3. The input stage is designed such that the gate voltage V G is an arithmetic mean of the two inputs, i.e., V G = ͑V A + V B ͒ / 2. Since digital inputs V A and V B can have one of two discrete values: low V L ͑Boolean 0͒ and high V H Ͼ V L ͑Boolean 1͒, the gate voltage V G can take one of three possible discrete values: V L ͑both inputs 0͒, V H ͑both inputs 1͒, and a value half way between V I = ͑V L + V H ͒ / 2 ͑inputs different͒. If the voltage levels V L and V H are chosen such that the maximum of the transfer curve is at V G = V I and R has a smaller ͑and identical͒ value at V G = V L or V H ͑these three operating points are denoted by circles in Fig. 2͒, then an XOR gate is obtained. 31 In this case, the resistance R is high ͑1͒ for different inputs and low ͑0͒ when both inputs are the same. Similarly, 32 a NOT-AND ͑NAND͒ gate is obtained if the voltage levels are chosen such that the resistance R is high for V G = V L or V I and low for V G = V H . An OR gate is obtained if the resistance R is low for V G = V L and high for V G = V I or V H . Finally, a NOT gate is obtained if the resistance R is high for V G = V L and low for V G = V H . The complete truth table of the designed logic gates is given in the inset of Fig. 2.
In order to be useful in a real digital circuit, the logic function must be presented as a change in voltage levels. For that purpose, the drain contact of the graphene transistor is connected via a pull-up resistor R D to a supply voltage V DD , which makes a simple voltage divider. The output drain voltage is then given by V D = V DD / ͑1+R D / R͒. Consequently, the output voltage V D is low ͑high͒ if the resistance R is low ͑high͒. Figure 4 shows measured output drain voltages in logic gates in which the input voltage levels V L and V H and power supply V DD are chosen to correspond to the voltage levels used in conventional complementary metal-oxide semiconductor ͑CMOS͒ circuits; the total gate voltage swing V H − V L and supply voltage V DD are 5 V. The actual logic function is determined by the midvalue V I , as shown in Fig. 2. The pull-up resistor R D is chosen to maximize the output voltage swing. Since a change in drain voltage ‫ץ‬V D / ‫ץ‬R = R D V DD / ͑R + R D ͒ 2 as a function of R D has a maximum value at R D = R, the value of R D = 4.8 k⍀, which corresponds to the resistance maximum in Fig. 2, is used in all measurements. Under these conditions, stable and separated output logic levels are obtained for all logic functions, as shown in Fig. 4. However, in all cases, the output drain voltage swing ͑e.g., 80 mV in case of a NOT gate͒ is much smaller than the input gate voltage swing ͑5 V͒ because of the very small voltage gain A v = ‫ץ‬V D / ‫ץ‬V G of the fabricated logic gates ͑in the whole range of the gate voltage ͉A v ͉ Ͻ 0.025͒. Such a small gain is due to a very small change in the transfer resistance around the charge neutrality point  1 1 1 1  1 0 1 1 1  1 1 0 0 1 0   FIG. 2. ͑Color online͒ Transfer curve R vs V G of the monolayer graphene shown in Fig. 1 at T = 1.5 K. Three equidistant operating points ͑with a total gate voltage swing of 5 V͒, which correspond to different functions of the logic gate shown in Fig. 3, are marked by symbols. The offset V I ͑V G of the middle point͒ determines the type of the function. An XOR gate ͑circles͒ is obtained for V I = 22.85 V, a NAND gate ͑squares͒ for V I = 24.20 V, an OR gate ͑triangles͒ for V I = 21.55 V, and a NOT gate ͑rhombuses͒ for V I = 33.00 V. Inset: truth table of all presented gates. Logic levels A and B correspond to the digital inputs shown in Fig. 3. 3. A two-input ͑A and B͒ logic gate incorporating one monolayer graphene transistor. R is the output resistance of the graphene transistor, which depends on the gate voltage V G ͑as shown in Fig. 2͒.

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Sordan, Traversi, and Russo Appl. Phys. Lett. 94, 073305 ͑2009͒ ͑⌬R / R Ͻ 7%͒, i.e., due to inability to turn off the graphene transistor. Although small gain also suppresses noise, the logic gates do not have a noise margin, nor do they have a well defined threshold voltage as the gain is always less than 1. Moreover, small output voltage swing makes fabricated gates prone to noise, which can be seen from the waveforms in Fig. 4. The main advantage of the proposed concept is the possibility of realizing different logic gates with just one graphene transistor. Although such a low transistor count seems very attractive, there are several other factors that should be considered in estimating a figure of merit. First, the present logic gates are always conducting, i.e., the output stage dissipates a static power, V DD 2 / ͑R + R D ͒ϳV DD 2 / ͑2R D ͒, in contrast with CMOS logic gates in which the output stage dissipates zero static power. The static dissipation could be reduced by using a graphene transistor with a higher resistance, but this would increase the output transient response time making this gate slower than a state-of-the-art CMOS gate, 33 whose output resistance is ϳ736 ⍀ / ͑w / m͒, where w / m is the width of the transistor in micrometers. In the present case, the output resistance R O = R D / 2 = 2.4 k⍀ of the logic gate and the total parasitic capacitance C O ϳ 3 nF of the measurement equipment connected to the output limit the clock rate to f O =1/ ͑2R O C O ͒ϳ22 kHz, which was confirmed by measurements. In principle, by loading the output with a typical gate capacitance of C O ϳ 10 fF͑w / m͒, 33 the clock rate of f O ϳ 6.6 GHz ͓for ͑w / m͒ϳ1͔ could be obtained. Further increase in f O by reduction in transistor length ͑to reduce R O ͒ will be hampered by contact resistance. As in CMOS technology, the clock rate will eventually be limited by power dissipation rather than intrinsic transistor parameters. 34 Second, if inputs are different then the logic gates dissipate additional static power ͑V H − V L ͒ 2 / ͑2R G ͒ = V DD 2 / ͑2R G ͒ in the input stage. The input dissipation could be minimized by increasing the resistance R G at the expense of increasing the input transient response time. Hence, there is a tradeoff between the total static dissipation and the highest possible clock rate both in the input and output stages. Third, input and output logic voltage levels are not the same, so the logic gates could not be cascaded without level shifters, which introduce additional transistors. This problem could be mitigated to some extent by decreasing the input voltage level V I from the present value of ϳ23 V to V DD / 2 ϳ V O by annealing the transistor. 35 Although annealing offers a simple way of tuning the position of the charge neutrality point, the resistance maximum of transistors exposed to air slowly drifts back to the original position. The permanent solution would be to use a thinner insulator with a higher dielectric constant, 36 in which the same charge is accumulated at lower gate voltages. However, resistance change cannot be increased by any of these methods so the mismatch between the input and output voltage swing would prevent direct cascading of the logic gates as long as gapless graphene is used.
In conclusion, four basic logic gates ͑XOR, NAND, OR, and NOT͒ are designed and fabricated with a single graphene transistor operated close to the charge neutrality point. The logic function is chosen by the choice of input logic voltage levels and operation of all logic gates is demonstrated. Although further improvements are required to approach the performance of conventional Si CMOS logic gates, the fab-ricated logic gates offer an attractive alternative to conventional gates due to their minimal transistor count.
We thank Dirk Obergfell for showing us the mechanical exfoliation technique and Daniel Chrastina and Giovanni Isella for the preparation of the substrates.