Conference paper Open Access

The next Generation of Exascale-class Systems: the ExaNeSt Project

R. Ammendolay; A. Biagioni; P. Cretaro; O. Frezza; F. Lo Cicero; A. Lonardo; M. Martinelli; P. S. Paolucci; E. Pastorelli; F. Simula; P. Vicini; G. Taffoni; J. Goodacree; M. Lujn; J. Navaridas; J. P. Saiz; N. Chrysos; M. Katevenis


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  <dc:creator>R. Ammendolay</dc:creator>
  <dc:creator>A. Biagioni</dc:creator>
  <dc:creator>P. Cretaro</dc:creator>
  <dc:creator>O. Frezza</dc:creator>
  <dc:creator>F. Lo Cicero</dc:creator>
  <dc:creator>A. Lonardo</dc:creator>
  <dc:creator>M. Martinelli</dc:creator>
  <dc:creator>P. S. Paolucci</dc:creator>
  <dc:creator>E. Pastorelli</dc:creator>
  <dc:creator>F. Simula</dc:creator>
  <dc:creator>P. Vicini</dc:creator>
  <dc:creator>G. Taffoni</dc:creator>
  <dc:creator>J. Goodacree</dc:creator>
  <dc:creator>M. Lujn</dc:creator>
  <dc:creator>J. Navaridas</dc:creator>
  <dc:creator>J. P. Saiz</dc:creator>
  <dc:creator>N. Chrysos</dc:creator>
  <dc:creator>M. Katevenis</dc:creator>
  <dc:date>2017-07-06</dc:date>
  <dc:description>The ExaNeSt project started on December 2015 and is funded by EU H2020 research framework (call H2020-FETHPC-2014, n. 671553) to study the adoption of low-cost, Linux-based power-efficient 64-bit ARM processors clusters for Exascale-class systems. The ExaNeSt consortium pools partners with industrial and academic research expertise in storage, interconnects and applications that share a vision of an European Exascale-class supercomputer. Their goal is designing and implementing a physical rack prototype together with its cooling system, the storage non-volatile memory (NVM) architecture and a low-latency interconnect able to test different options for interconnection and storage. Furthermore, the consortium is to provide real HPC applications to validate the system. Herein we provide a status report of the project initial developments.</dc:description>
  <dc:identifier>https://zenodo.org/record/823595</dc:identifier>
  <dc:identifier>10.5281/zenodo.823595</dc:identifier>
  <dc:identifier>oai:zenodo.org:823595</dc:identifier>
  <dc:relation>info:eu-repo/grantAgreement/EC/H2020/671553/</dc:relation>
  <dc:relation>doi:10.5281/zenodo.823594</dc:relation>
  <dc:rights>info:eu-repo/semantics/openAccess</dc:rights>
  <dc:rights>https://creativecommons.org/licenses/by-nc-nd/4.0/</dc:rights>
  <dc:subject>Exascale system</dc:subject>
  <dc:subject>supercomputer</dc:subject>
  <dc:subject>rack prototype</dc:subject>
  <dc:subject>non-volatile memory</dc:subject>
  <dc:subject>low-latency interconnect</dc:subject>
  <dc:subject>real HPC applications</dc:subject>
  <dc:subject>European Union</dc:subject>
  <dc:subject>Horizon 2020</dc:subject>
  <dc:subject>Euratom</dc:subject>
  <dc:subject>Euratom research &amp; training programme 2014-2018</dc:subject>
  <dc:title>The next Generation of Exascale-class Systems: the ExaNeSt Project</dc:title>
  <dc:type>info:eu-repo/semantics/conferencePaper</dc:type>
  <dc:type>publication-conferencepaper</dc:type>
</oai_dc:dc>

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