Conference paper Open Access

The next Generation of Exascale-class Systems: the ExaNeSt Project

R. Ammendolay; A. Biagioni; P. Cretaro; O. Frezza; F. Lo Cicero; A. Lonardo; M. Martinelli; P. S. Paolucci; E. Pastorelli; F. Simula; P. Vicini; G. Taffoni; J. Goodacree; M. Lujn; J. Navaridas; J. P. Saiz; N. Chrysos; M. Katevenis


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    "creators": [
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        "affiliation": "INFN Sezione di Roma Tor Vergata, and Electronic Engineering Dept., University of Roma Tor Vergata, Italy", 
        "name": "R. Ammendolay"
      }, 
      {
        "affiliation": "INFN Sezione di Roma, Italy", 
        "name": "A. Biagioni"
      }, 
      {
        "affiliation": "INFN Sezione di Roma, Italy", 
        "name": "P. Cretaro"
      }, 
      {
        "affiliation": "INFN Sezione di Roma, Italy", 
        "name": "O. Frezza"
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      {
        "affiliation": "INFN Sezione di Roma, Italy", 
        "name": "F. Lo Cicero"
      }, 
      {
        "affiliation": "INFN Sezione di Roma, Italy", 
        "name": "A. Lonardo"
      }, 
      {
        "affiliation": "INFN Sezione di Roma, Italy", 
        "name": "M. Martinelli"
      }, 
      {
        "affiliation": "INFN Sezione di Roma, Italy", 
        "name": "P. S. Paolucci"
      }, 
      {
        "affiliation": "INFN Sezione di Roma, Italy", 
        "name": "E. Pastorelli"
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      {
        "affiliation": "INFN Sezione di Roma, Italy", 
        "name": "F. Simula"
      }, 
      {
        "affiliation": "INFN Sezione di Roma, Italy", 
        "name": "P. Vicini"
      }, 
      {
        "affiliation": "INAF, Osservatorio Astronomico di Trieste", 
        "name": "G. Taffoni"
      }, 
      {
        "affiliation": "University of Manchester, England", 
        "name": "J. Goodacree"
      }, 
      {
        "affiliation": "University of Manchester, England", 
        "name": "M. Lujn"
      }, 
      {
        "affiliation": "University of Manchester, England", 
        "name": "J. Navaridas"
      }, 
      {
        "affiliation": "University of Manchester, England", 
        "name": "J. P. Saiz"
      }, 
      {
        "affiliation": "FORTH - Foundation For Research & Technology, Hellas", 
        "name": "N. Chrysos"
      }, 
      {
        "affiliation": "FORTH - Foundation For Research & Technology, Hellas", 
        "name": "M. Katevenis"
      }
    ], 
    "description": "<p>The ExaNeSt project started on December 2015 and is funded by EU H2020 research framework (call H2020-FETHPC-2014, n. 671553) to study the adoption of low-cost, Linux-based power-efficient 64-bit ARM processors clusters for Exascale-class systems. The ExaNeSt consortium pools partners with industrial and academic research expertise in storage, interconnects and applications that share a vision of an European Exascale-class supercomputer. Their goal is designing and implementing a physical rack prototype together with its cooling system, the storage non-volatile memory (NVM) architecture and a low-latency interconnect able to test different options for interconnection and storage. Furthermore, the consortium is to provide real HPC applications to validate the system. Herein we provide a status report of the project initial developments.</p>", 
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    "grants": [
      {
        "acronym": "ExaNeSt", 
        "code": "671553", 
        "funder": {
          "acronyms": [
            "EC"
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          "doi": "10.13039/501100000780", 
          "links": {
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          "name": "European Commission"
        }, 
        "links": {
          "self": "https://zenodo.org/api/grants/10.13039/501100000780::671553"
        }, 
        "program": "H2020", 
        "title": "European Exascale System Interconnect and Storage"
      }
    ], 
    "keywords": [
      "Exascale system", 
      "supercomputer", 
      "rack prototype", 
      "non-volatile memory", 
      "low-latency interconnect", 
      "real HPC applications", 
      "European Union", 
      "Horizon 2020", 
      "Euratom", 
      "Euratom research & training programme 2014-2018"
    ], 
    "license": {
      "id": "cc-by-nc-nd-4.0"
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    "notes": "To appear in: the Proceedings of the Euromicro Conference on Digital System Design (DSD 2017), Vienna, Austria, 30 August - 1 September, 2017", 
    "publication_date": "2017-07-06", 
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