Conference paper Open Access

The next Generation of Exascale-class Systems: the ExaNeSt Project

R. Ammendolay; A. Biagioni; P. Cretaro; O. Frezza; F. Lo Cicero; A. Lonardo; M. Martinelli; P. S. Paolucci; E. Pastorelli; F. Simula; P. Vicini; G. Taffoni; J. Goodacree; M. Lujn; J. Navaridas; J. P. Saiz; N. Chrysos; M. Katevenis


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  <identifier identifierType="DOI">10.5281/zenodo.823595</identifier>
  <creators>
    <creator>
      <creatorName>R. Ammendolay</creatorName>
      <affiliation>INFN Sezione di Roma Tor Vergata, and Electronic Engineering Dept., University of Roma Tor Vergata, Italy</affiliation>
    </creator>
    <creator>
      <creatorName>A. Biagioni</creatorName>
      <affiliation>INFN Sezione di Roma, Italy</affiliation>
    </creator>
    <creator>
      <creatorName>P. Cretaro</creatorName>
      <affiliation>INFN Sezione di Roma, Italy</affiliation>
    </creator>
    <creator>
      <creatorName>O. Frezza</creatorName>
      <affiliation>INFN Sezione di Roma, Italy</affiliation>
    </creator>
    <creator>
      <creatorName>F. Lo Cicero</creatorName>
      <affiliation>INFN Sezione di Roma, Italy</affiliation>
    </creator>
    <creator>
      <creatorName>A. Lonardo</creatorName>
      <affiliation>INFN Sezione di Roma, Italy</affiliation>
    </creator>
    <creator>
      <creatorName>M. Martinelli</creatorName>
      <affiliation>INFN Sezione di Roma, Italy</affiliation>
    </creator>
    <creator>
      <creatorName>P. S. Paolucci</creatorName>
      <affiliation>INFN Sezione di Roma, Italy</affiliation>
    </creator>
    <creator>
      <creatorName>E. Pastorelli</creatorName>
      <affiliation>INFN Sezione di Roma, Italy</affiliation>
    </creator>
    <creator>
      <creatorName>F. Simula</creatorName>
      <affiliation>INFN Sezione di Roma, Italy</affiliation>
    </creator>
    <creator>
      <creatorName>P. Vicini</creatorName>
      <affiliation>INFN Sezione di Roma, Italy</affiliation>
    </creator>
    <creator>
      <creatorName>G. Taffoni</creatorName>
      <affiliation>INAF, Osservatorio Astronomico di Trieste</affiliation>
    </creator>
    <creator>
      <creatorName>J. Goodacree</creatorName>
      <affiliation>University of Manchester, England</affiliation>
    </creator>
    <creator>
      <creatorName>M. Lujn</creatorName>
      <affiliation>University of Manchester, England</affiliation>
    </creator>
    <creator>
      <creatorName>J. Navaridas</creatorName>
      <affiliation>University of Manchester, England</affiliation>
    </creator>
    <creator>
      <creatorName>J. P. Saiz</creatorName>
      <affiliation>University of Manchester, England</affiliation>
    </creator>
    <creator>
      <creatorName>N. Chrysos</creatorName>
      <affiliation>FORTH - Foundation For Research &amp; Technology, Hellas</affiliation>
    </creator>
    <creator>
      <creatorName>M. Katevenis</creatorName>
      <affiliation>FORTH - Foundation For Research &amp; Technology, Hellas</affiliation>
    </creator>
  </creators>
  <titles>
    <title>The Next Generation Of Exascale-Class Systems: The Exanest Project</title>
  </titles>
  <publisher>Zenodo</publisher>
  <publicationYear>2017</publicationYear>
  <subjects>
    <subject>Exascale system</subject>
    <subject>supercomputer</subject>
    <subject>rack prototype</subject>
    <subject>non-volatile memory</subject>
    <subject>low-latency interconnect</subject>
    <subject>real HPC applications</subject>
    <subject>European Union</subject>
    <subject>Horizon 2020</subject>
    <subject>Euratom</subject>
    <subject>Euratom research &amp; training programme 2014-2018</subject>
  </subjects>
  <contributors>
    <contributor contributorType="Funder">
      <contributorName>European Commission</contributorName>
      <nameIdentifier nameIdentifierScheme="info">info:eu-repo/grantAgreement/EC/H2020/671553/</nameIdentifier>
    </contributor>
  </contributors>
  <dates>
    <date dateType="Issued">2017-07-06</date>
  </dates>
  <resourceType resourceTypeGeneral="Text">Conference paper</resourceType>
  <alternateIdentifiers>
    <alternateIdentifier alternateIdentifierType="url">https://zenodo.org/record/823595</alternateIdentifier>
  </alternateIdentifiers>
  <relatedIdentifiers>
    <relatedIdentifier relatedIdentifierType="DOI" relationType="IsPartOf">10.5281/zenodo.823594</relatedIdentifier>
  </relatedIdentifiers>
  <rightsList>
    <rights rightsURI="https://creativecommons.org/licenses/by-nc-nd/4.0/">Creative Commons Attribution-NonCommercial-NoDerivatives</rights>
    <rights rightsURI="info:eu-repo/semantics/openAccess">Open Access</rights>
  </rightsList>
  <descriptions>
    <description descriptionType="Abstract">&lt;p&gt;The ExaNeSt project started on December 2015 and is funded by EU H2020 research framework (call H2020-FETHPC-2014, n. 671553) to study the adoption of low-cost, Linux-based power-efficient 64-bit ARM processors clusters for Exascale-class systems. The ExaNeSt consortium pools partners with industrial and academic research expertise in storage, interconnects and applications that share a vision of an European Exascale-class supercomputer. Their goal is designing and implementing a physical rack prototype together with its cooling system, the storage non-volatile memory (NVM) architecture and a low-latency interconnect able to test different options for interconnection and storage. Furthermore, the consortium is to provide real HPC applications to validate the system. Herein we provide a status report of the project initial developments.&lt;/p&gt;</description>
    <description descriptionType="Other">To appear in: the Proceedings of the Euromicro Conference on Digital System Design (DSD 2017), Vienna, Austria, 30 August - 1 September, 2017</description>
  </descriptions>
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