Conference paper Open Access

The next Generation of Exascale-class Systems: the ExaNeSt Project

R. Ammendolay; A. Biagioni; P. Cretaro; O. Frezza; F. Lo Cicero; A. Lonardo; M. Martinelli; P. S. Paolucci; E. Pastorelli; F. Simula; P. Vicini; G. Taffoni; J. Goodacree; M. Lujn; J. Navaridas; J. P. Saiz; N. Chrysos; M. Katevenis


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{
  "DOI": "10.5281/zenodo.823595", 
  "abstract": "<p>The ExaNeSt project started on December 2015 and is funded by EU H2020 research framework (call H2020-FETHPC-2014, n. 671553) to study the adoption of low-cost, Linux-based power-efficient 64-bit ARM processors clusters for Exascale-class systems. The ExaNeSt consortium pools partners with industrial and academic research expertise in storage, interconnects and applications that share a vision of an European Exascale-class supercomputer. Their goal is designing and implementing a physical rack prototype together with its cooling system, the storage non-volatile memory (NVM) architecture and a low-latency interconnect able to test different options for interconnection and storage. Furthermore, the consortium is to provide real HPC applications to validate the system. Herein we provide a status report of the project initial developments.</p>", 
  "author": [
    {
      "family": "R. Ammendolay"
    }, 
    {
      "family": "A. Biagioni"
    }, 
    {
      "family": "P. Cretaro"
    }, 
    {
      "family": "O. Frezza"
    }, 
    {
      "family": "F. Lo Cicero"
    }, 
    {
      "family": "A. Lonardo"
    }, 
    {
      "family": "M. Martinelli"
    }, 
    {
      "family": "P. S. Paolucci"
    }, 
    {
      "family": "E. Pastorelli"
    }, 
    {
      "family": "F. Simula"
    }, 
    {
      "family": "P. Vicini"
    }, 
    {
      "family": "G. Taffoni"
    }, 
    {
      "family": "J. Goodacree"
    }, 
    {
      "family": "M. Lujn"
    }, 
    {
      "family": "J. Navaridas"
    }, 
    {
      "family": "J. P. Saiz"
    }, 
    {
      "family": "N. Chrysos"
    }, 
    {
      "family": "M. Katevenis"
    }
  ], 
  "id": "823595", 
  "issued": {
    "date-parts": [
      [
        2017, 
        7, 
        6
      ]
    ]
  }, 
  "note": "To appear in: the Proceedings of the Euromicro Conference on Digital System Design (DSD 2017), Vienna, Austria, 30 August - 1 September, 2017", 
  "publisher": "Zenodo", 
  "title": "The next Generation of Exascale-class Systems: the ExaNeSt Project", 
  "type": "paper-conference"
}

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