Conference paper Open Access
The next Generation of Exascale-class Systems: the ExaNeSt Project
R. Ammendolay; A. Biagioni; P. Cretaro; O. Frezza; F. Lo Cicero; A. Lonardo; M. Martinelli; P. S. Paolucci; E. Pastorelli; F. Simula; P. Vicini; G. Taffoni; J. Goodacree; M. Lujn; J. Navaridas; J. P. Saiz; N. Chrysos; M. Katevenis
The ExaNeSt project started on December 2015 and is funded by EU H2020 research framework (call H2020-FETHPC-2014, n. 671553) to study the adoption of low-cost, Linux-based power-efficient 64-bit ARM processors clusters for Exascale-class systems. The ExaNeSt consortium pools partners with industrial and academic research expertise in storage, interconnects and applications that share a vision of an European Exascale-class supercomputer. Their goal is designing and implementing a physical rack prototype together with its cooling system, the storage non-volatile memory (NVM) architecture and a low-latency interconnect able to test different options for interconnection and storage. Furthermore, the consortium is to provide real HPC applications to validate the system. Herein we provide a status report of the project initial developments.
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ExaNeSt_dsd17.pdf
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- Publication date:
- July 6, 2017
- DOI:
-
- Keyword(s):
- Exascale system supercomputer rack prototype non-volatile memory low-latency interconnect real HPC applications European Union Horizon 2020 Euratom Euratom research & training programme 2014-2018
- Grants:
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European Commission:
- ExaNeSt - European Exascale System Interconnect and Storage (671553)
- License (for files):
- Creative Commons Attribution-NonCommercial-NoDerivatives