A Beyond 100-Gbps Polymer Microwave Fiber Communication Link at D-Band

A D-band (110-170 GHz) ultra high data rate link is presented and characterized. The circuits are realized in a commercial 130 nm silicon germanium (SiGe) BiCMOS process. The 3-dB bandwidth for both transmitter (Tx) and receiver (Rx) is between 125 - 165 GHz, resulting in a 40 GHz bandwidth. The communication link has demonstrated transmissions up to 102 Gbps using 8-phase shift keying (PSK) modulation over a one meter long foam-cladded polymer microwave fiber (PMF) with a bit error rate (BER) of <inline-formula> <tex-math notation="LaTeX">$2.1\times 10^{-3}$ </tex-math></inline-formula>. Using direct quadrature phase shift keying (QPSK), 56 Gbps was reached with a BER <inline-formula> <tex-math notation="LaTeX">$< 10^{-12}$ </tex-math></inline-formula>. Total chip area for Tx and Rx combined, including pads, is 4.2 mm<sup>2</sup>.


I. INTRODUCTION
F OLLOWING the rapid development of new commercial semiconductor processes with a maximum frequency of oscillation well above 300 GHz [1], new applications at frequencies above 100 GHz are rapidly researched and developed. Such applications include wireless backhaul [2], [3] [4], wireless access [5], radar and radiometer sensors, wireless energy distribution and harvesting, IoT etc. Several of these applications require throughput in data rate well above 10 Gbps, even up to 100 Gbps. For high data rate, long range wired communication, optical fiber communication is the leading option, but for shorter ranges like chip-to-chip or module-to-module (up to 10 meters), sub-THz communication over a plastic fiber is an interesting alternative due to its potentially low cost. Other advantages are less sensitivity to temperature variations and better mechanical ruggedness. The polymer microwave fiber (PMF) is a good candidate to fill this need, due to its low cost, flexibility and robustness. Using PMFs in combination with millimeter wave chipsets allows for larger tolerance in alignment and temperature restrictions [6].
Frequencies above 100 GHz is preferred for the signal to stay confined to the fiber and not be sensitive to bends [7]. To further improve the confinement and decrease sensitivity, foam-cladding around the fiber core can be used, it also allows Manuscript  the fiber to be touched without affecting the signal [8]. Work has been presented at D-band (110 -170 GHz), showing the potential of these short range high data rate links, with data rates up to 27 Gbps over a one meter long PMF [9], [10] [11]. Over a shorter distance (5 cm), 30 Gbps has been achieved [12]. At H-band (220 -325 GHz) 35 Gbps was demonstrated over a 30 cm dielectric waveguide [13]. In [14] longer distances (three and four meters) were demonstrated using dual-band.
In this work, a commercial 130 nm SiGe BiCMOS process is used to create a competitive high data rate communication link at D-band. Previous work achieved data rates up to 40 Gbps using 16-quadrature amplitude modulation (QAM) [15]. Development towards a wider bandwidth, more importantly covering the upper side of D-band has been a priority in this work. The upper side of D-band was prioritized due to insights gained in [16]. A 3-dB bandwidth of 40 GHz was achieved in these designs, making it possible to transfer ultra high datarates at a low modulation order. In combination with a one meter long foam-cladded PMF, it forms a link that has demonstrated data rates above 100 Gbps using 8-phase shift keying (PSK).
The paper is structured as following: a brief description of the technology and topology of the design in Sec. II, followed by presentation of the measurement results both in frequency domain and time domain in Sec. III. In Sec. IV the limitations of the system is discussed. The performance is summarized and compared with previous published results in Sec. V.

II. TECHNOLOGY AND CIRCUIT DESIGN
In this work, both the transmitter (Tx) and receiver (Rx) are designed and fabricated using a 130 nm SiGe BiCMOS process (B11HFC) developed by Infineon technologies. The process features high speed npn HBTs with maximum f t /f max of 250 GHz/370 GHz [17]. The process features six metal layers to route the RF signal and DC bias. The forth layer (m4) from the bottom is used as ground, with exception of the baluns, where the bottom layer is used (m1). The stack of the B11HFC process is displayed in Fig. 1.
The block diagrams of the transmitter and receiver can be seen in Fig. 2, showing that the three main parts of the circuits are frequency multipliers, amplifiers and mixers.

A. Wideband Amplifier Design
The power amplifiers (PA) and low noise amplifier (LNA) uses the same six-stage common emitter topology. The amplifier is designed to have a flat gain with a large bandwidth, 1549-8328 © 2023 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.
See https://www.ieee.org/publications/rights/index.html for more information.  covering the entire D-band. A simplified schematic can be seen in Fig. 3. For the PA the transistor sizes are getting larger at each stage ranging between 4 µm and 10 µm. All transistors share the same collector supply, Vcc, which is of the order 1.8 V. The collector currents are set by a common current mirror base supply, Q4. The current consumption of the amplifier is typically between 20-40 mA depending on the required gain and output power. The amplifiers include interstage matching utilizing high-pass networks including shorted stubs (L5, L6, L8) and two capacitors (C4, C5) to get a flat gain across the entire bandwidth. For the input and output a matching, an L-type series-parallel transmission line match is used. The photo of the LNA is shown in Fig. 4. In Fig. 5, the measured S-parameters are plotted. The mid-band gain of the amplifier is 12.4 dB and the bandwidth is 125-179 GHz (54 GHz), the input/output reflection is less than -10 dB over the full band. The measured P sat is 4.1 dB m at 140 GHz in good agreement with the simulation when using the HICUM-model. The simulated noise figure of the amplifier is 11 dB in the mid of the D-band.

B. Frequency Multiplier Design
Both the Tx and Rx uses an off-chip local oscillator (LO) that is one forth of the carrier frequency, thus a frequency quadrupler is included in the chipsets. The quadrupler consists of two cascaded frequency doublers. In Fig. 6 the schematic of the E-band (60-90 GHz) doubler is plotted. Each doubler has an emitter coupled pair which is differentially fed. The differential signal is realized using a passive Marchand balun and the transistor pair is class-B biased. The combined waveform from the collectors is rich in the second harmonic, while the fundamental and uneven harmonics are ideally canceled out. The output from the combined collectors is fed to the emitter of a cascoded transistor to achieve a higher output power. Stub matching is implemented both at input and output.
The D-band doubler schematic is shown in Fig. 7. All transistors are internally biased through resistors and diod ladders.
The suppression of the uneven harmonics is dependent of the balun design. A conventional Marchand balun will give a good performance, but needs to be optimized to achieve full balance (phase, balance and input match). An offset of the transmission lines in the baluns were introduced to compensate the difference between in gain. The offset between the transmission lines can be seen in Fig. 8. The output branch that is bounded to the input first will get more power, which is why an offset (between the metals) is introduced. Using this method the phase offset can be preserved, while a better amplitude matching is achieved.
Simulated S21 for the baluns are plotted in Fig. 9 and Fig. 10. The baluns are designed to be as wideband as possible, to be able to cover a wide frequency range, thus enable wideband communication. The lower frequency band balun exhibit a higher insertion loss due to the difference in layout to also optimize for a smaller sized circuit. In Fig. 11 a photo of the frequency quadrupler is depicted.
The measured output power from the quadrupler is plotted in Fig. 12. The DC bias is 3 V and the current is 25 mA, giving a DC power consumption of 75 mW for the quadrupler. The input power is 3 dB m to saturate the quadrupler.

C. Mixer Design
Aiming for an IQ differential IF configuration, both the up-converter mixer and the down-converter mixer was realized with two identical double-balanced Gilbert cells. Fig. 13 shows the schematic of the up-converter mixer. As can be seen in the Gilbert Cell 1, the differential IF input signals are fed into the bases of the lower level transistor pair Q1 and Q2 (size: 6 µm) through off-chip DC blocks, so as to operate at the frequency down to the baseband. At the LO port, the single-ended LO input signal is firstly converted into four quadrature phased signals through an on-chip Marchand balun in combined with two 90 degree 3-dB couplers, and one branch of differential LO signals are further applied to the bases of the upper level transistors Q2-Q6 (size: 2.5 µm). The transistor pair Q1 and Q2 work as the transconductance stages, which convert the input baseband signals at the bases into currents at the collectors. The upper level transistors Q3-Q6 operate as switches and generate mixing products of IF and LO at the collectors. The desired RF outputs will be added up through the Marchand balun, while the LO will be canceled. In order to simplify the biasing, the mixer is internally biased and controlled by the current mirror pair Q1 and Q2, while the bases of the transistors are voltage biased through the transistor diodes stack-up. The designed D-band IQ-differential up-converter mixer occupies an area of 700 × 650 µm 2 , and the chip photo is shown in Fig. 14. With an IF input frequency of 2 GHz and an LO power of 5∼7 dBm,   a typical conversion gain of around -3 dB was measured for the entire D-band, as is shown in Fig. 15, while better than 20 dB side-band suppression was achieved.
The down-converter mixer shares a similar Gilbert mixer core cell as the up-converter mixer. The schematic is shown in Fig. 16. The single-ended RF input is differentially fed into the bases of the lower level transconductance stage through an on-chip Marchand balun. Considering the parasitic parameters at high frequency of RF and the linearity, an optimized transistor size of 0.22 µm×4 µm is chosen for Q1 and Q2. The down-converted IF outputs are obtained through an emitter-follower stage and further optimized with the help of a series connected microstrip line TL1 and a small shunt capacitor C1. Similar like the up-converter mixer, the internal biasing network is applied to the down-converter mixer and only one external voltage bias of V C−M I X is needed. The D-band IQ-differential down-converter mixer occupies an area of 700 × 700 µm 2 , and the chip photo is shown in Fig. 17.
With an LO power of 5∼7 dBm, Fig. 18 shows the measured conversion gains of the LSB and USB. For the entire D-band, a typically conversion gain of 0 dB was obtained while the side-band suppression is around 15 dB.

D. Fully Integrated Tx and Rx
The above presented frequency multiplier, mixers and amplifier were designed and optimized for 50 port impedance to facilitate a simple matching between subcircuits. The layout of the sub-circuits were designed to fit together, without using long transmission lines between to avoid unnecessary loss in the integrations.   The chip photo of the transmitter and receiver is shown in Fig. 19. The total chip area for Tx and Rx combined is 4.3 mm 2 .

III. MEASUREMENT RESULTS
Measurements were done both in frequency domain and in time domain as a link communication demonstration. Both were done on-wafer using Cascade probe stations and GGB picoprobes.

A. Frequency Domain Measurements
For the frequency domain measurements, a Keysight PNA-X (67 GHz N5247A) was used together with a VDI D-band extender WR 6.5 at the output of the Tx and as the input for the Rx. The LO was provided by a Keysight signal generator (Agilent 67 GHz PSG E8257D) which was synchronized to the PNA-X.
1) Evaluation of the Tx: The conversion gain for the transmitter was measured with an input IF power of -15 dB m and an LO power fed into the quadrupler of 4 dB m . The IF was a fixed sinusoidal at 4 GHz and both the lower sideband (LSB) and the upper sideband (USB) was measured sweeping the RF frequency between 110 -170 GHz. The single-ended IF input was split into the four channels using a commercial  hybrid (Marki QH-0440)and two baluns (Marki BAL-0050). The quadrature-phase IF signals were further connected to the GSSGSSG probe through external DC blocks.
As can be seen from the Fig. 20, a typical conversion gain of around 10 dB was measured between 125 -165 GHz, which corresponds to an RF bandwidth of 40 GHz, and a sideband suppression of around 20 dB was achieved. The highest sideband suppression (25 dB) was around 152 GHz. During the link measurements direct I/Q modulation is used, but the sideband suppression is also a measure of I/Q (im-) balance. I/Q imbalance is a result of either an amplitude difference between I and Q, or a phase difference that is deviating from the ideal 90 degrees. The result is a distortion of the signal and can be measured in a signal-to-distortion ratio (SDR). SDR is given by; where ϵ R is the amplitude error and φ R is the phase error. For an SDR above 20 dB the phase error has to be lower than 6 degrees or the amplitude error less than 10 % [18]. Known  distortion can be dealt with, but it is increasingly difficult to implement at high data rates, in real-time, which is why it can be seen as noise in those cases. In Fig. 21, the saturated output power of the Tx is measured using the LSB with a 4 GHz sinusoidal IF. The peak output power is 0 dB m .
To investigate the IF bandwidth a sweep (4 GHz -30 GHz) of the IF frequency was done for both LSB and USB, using -15 dB m IF power and 4 dB m LO input (to the quadrupler). The results can be found in Fig. 22. The difference in gain between 5 GHz and 20 GHz is only 4 dB, and some gain can still be seen at 30 GHz IF. The input power at the IF port was swept using constant IF frequency (4 GHz) and RF (152 GHz). Conversion gain and RF output power is plotted in Fig. 23. To avoid compression, the input power at IF should be kept below -15 dB m .
The output spectrum of a modulated 5 Gbd QPSK signal was captured by a Rohde & Schwarz Signal Source Analyzer (FSUP50) via an external signal analyzer mixer (SAM-170). The output spectrum is displayed in Fig. 24. The LO leakage can be seen at the center of the signal, which is a result of phase and/or amplitude mismatch when the RF output signal is combined.
2) Evaluation of the Rx: Similar measurements were done for the receiver, using two baluns and a hybrid to combine the four IF ports. With the IF frequency of 4 GHz and an input power of -20 dB m , the measured conversion gain for both LSB and USB can be seen in Fig. 25. A conversion gain of more than 10 dB was obtained at the RF frequency range of  The simulated value is about 10 dB higher than the measured value, which is in majority due to a lower conversion gain than expected in the up converter mixer. 125-165 GHz, while the side-band suppression was typically 15 dB, with 20 dB at most.
The IF bandwidth was measured with a fixed input RF frequency of 152 GHz. The result is plotted in Fig. 26. Compared to the Tx, the Rx has a higher gain but worse sideband suppression. It drops 10 dB in gain between 5 GHz     An input power sweep was done for the Rx, with a 152 GHz LO. In Fig. 27 both IF output power and conversion gain is plotted. Compression starts around -18 dB m .

B. Time Domain Measurements
The transmitter and receiver link was setup using a one meter PMF, to validate and measure the performance of the link. The PMF including transitions was provided by Huber+Suhner. The fiber has a rectangular polytetrafluoroethylene (PTFE) core with a cross section of 2.1 mm by 1.2 mm   The measured S-parameters and group delay of the fiber is plotted in Fig. 28 and Fig. 29. The measurements were done using a Keysight PNA-X (67 GHz N5247A) together with VDI extenders (WR-6.5), and include the waveguide transitions to and from the fiber.
The difference in group delay over the signal bandwidth has to be small in comparison to the symbol period in order to avoid symbol interference. Pulse shaping of the baseband  signal on the transmitter side and equalization/filtering on the receiver side can be used in order to compensate for this. Reflections and variations in Fig 28 and Fig. 29 could be due to the fact that the fiber is cut by hand.
The data input was provided by a Keysight M8195A arbitrary waveform generator (AWG), where a pseudorandom binary sequence (PRBS-10) was generated using root raised cosine pulse shaping with a roll off of 0.7. Direct I/Q modulation was used during the link measurements.
The LO was provided by a Keysight signal generator (Agilent 67 GHz PSG E8257D), which was shared by Tx and Rx using a power splitter. A Teledyne LeCroy LabMaster 10-100Zi was used to capture the output signal from the Rx. The bandwidth of the oscilloscope is 36 GHz which is smaller than the measured bandwidth of the transmitter and receiver and can be considered a limitation in this measurement setup. Fig. 30 is a block diagram of the setup.
The setup for the measurement is shown in Fig. 31. The Tx can be seen to the right which is connected to the Rx on the left. The output is then captured by the oscilloscope. Carrier frequencies between 151 GHz and 153 GHz were used during the link measurements. The DC power consumption for the Tx is 437 mW, and for the Rx it is 556 mW.  In Table I, an estimation of the power levels for the link is made. The noise floor of the 36 GHz bandwidth of the oscilloscope is approximately -68 dB m .
Captured eye diagrams and IQ constellation for QPSK modulations can be seen in Fig. 32, 33 and 34 for data rates of 28 GBd, 34 Gbd and 40 GBd, corresponding to 56 Gbps, 68 Gbps and 80 Gbps.
The measured bit error rate (BER) for different baudrates for QPSK modulation is depicted in Fig. 35.
The eye diagrams and IQ constellations for 8-PSK modulation can be seen in Fig. 36 and 37 for data rates of 26 GBd and 34 GBd, corresponding to 78 Gbps and 102 Gbps.    Transmissions with QAM-16 modulations were also tested. In Fig. 38 10 GBd is transmitted corresponding to 40 Gbps.  The spectrum of the output signal from the Rx was captured by the oscilloscope. The signal was QPSK modulated with baudrates of 15, 25 and 30 Gbd. The spectras can be seen in Fig. 39. The bandwidth of the signal is less than the baudrate. The RRC pulse shaping of the signal done by the AWG is decreasing the signal bandwidth, which means the signal will  be less sensitive to the dispersive effects of the PMF. It can also be seen that the noise floor is much lower than the signal power, meaning it should not impact the SNR.
Captured waveforms when only I or Q channel is used and both channels are used can be seen in Fig. 40. 10 Gbd QPSK modulated data was used and a carrier of 151 GHz. In the first case the input to the Q channel was turned off, second case I channel was turned off. It can be seen that a small part of the I channel is leaking to the Q channel and conversely. The quality of the signal is slightly degraded in both channels when they are used simultaneously.

IV. DISCUSSION
The bandwidth of the measurement setup is a factor that cannot be neglected, but that is an "outside the system" limitation. Thus, to increase the datarate even more in the future, a higher modulation order is the solution, which means a larger SNR is required.
The input power (≈ −17.7 dB m ) at the Rx is not enough to saturate the circuit according to Fig. 27, and verified using an attenuator after the PMF, before the Rx. The input power to the oscilloscope is far from the noise floor (as seen in Fig. 39), eliminating that as a limitation.
In Fig. 24 some LO leakage can be noticed, which may limit the SNR, thus higher modulation orders. By adding a bias tee to the I+ and Q+ port a small voltage change (a few mV) could significantly improve the LO leakage. Fig. 41 shows the output spectrum of a 5 GHz continuous wave (CW), with 90 degree offset between channels to show sideband suppression as well, where the one on the left is without bias tee, and the one on the right is with bias tee.
Another limitation can be found in Fig. 40, where some crosstalk between the channels can be seen. This can be removed through signal processing, but it is challenging to do in real time at high datarates.
The potential of the link is clearly be seen in the large bandwidth, and further improvements can possible be made by focusing on minimizing the LO leakage and crosstalk between the channels.

V. CONCLUSION
In this work a high datarate, short range communication link has been designed in a commercial 130 nm SiGe BiCMOS process and evaluated. The link is measured to support data rates up to 102 Gbps with a BER=2.1 * 10 −3 using 8-PSK modulation and 56 Gbps with a BER< 10 −12 using QPSK modulation. The 3-dB bandwidth is 40 GHz, which is larger than the measurement setup equipment, which may add some limitations in the performance. The performance in comparison to other PMF links can be seen in Table II. It can be seen that this link has the highest datarate, more than double, for these distances in this frequency range.
The chipset is designed for PMF communication, and is suitable for short distance, ultra high speed chip-to-chip or module-to-module communication, for example in-cabin vehicle communication for autonomous vehicles. It is potentially a low cost, robust solution using a commercial process.