Faster-Than-Real-Time Hardware Emulation of Extensive Contingencies for Dynamic Security Analysis of Large-Scale Integrated AC/DC Grid

The rapid expansion of modern power systems has brought a tremendous computational challenge to dynamic security analysis (DSA) tools which consequently need to process extensive contingencies. In this work, hardware emulation is investigated to accelerate the DSA solution of a large-scale AC/DC system deployed on the field-programmable gate arrays (FPGAs) faster-than-real-time (FTRT) execution. Electromagnetic transient (EMT) modeling of the DC grid is conducted since the fast converter dynamics require a small time-step for accuracy; in contrast, the transient stability (TS) simulation is applicable to the AC grid which tolerates a much larger step size. To coordinate the 2 different types of simulation, an interface based on dynamic voltage injection is proposed to integrate the AC and DC grids, in addition to maintaining a low hardware latency. An emulation platform consisting of multiple FPGA boards is established so that with a proper allocation it has a sufficient capacity to accommodate the system under study which has 6 ACTIVSg 500-bus systems interconnected by a 6-terminal DC grid. The efficacy of the proposed FTRT hardware emulation platform is demonstrated by 2 case studies with more than 5500 contingencies analyzed in total, where an FTRT ratio of more than 208 is achieved for the hybrid AC/DC grid, while it is over 277 times for a single 500-bus system. Furthermore, the FTRT dynamic emulation results, including the security indices, are validated by the simulation tool DSATools/TSAT.

(HVDC) systems, making the modeling, simulation, protection, and control of the network significantly more complex. The increasing scale of a power system also demands that more contingency scenarios be taken into consideration during DSA. To mitigate the adverse impacts of a variety of disturbances on the actual power system, online DSA is widely utilized to continuously monitor the grid and take remedial actions [1], [2].
The contingency screening type is a major factor that influences the speed of DSA. A typical contingency analysis applies the power flow calculation or state estimation, which only provides a single-state security index for contingency ranking [2], [3]. Due to the relatively low computational burden, the power-flow based contingency analysis methods are widely utilized in high-speed DSA [4]- [6]. However, more stringent criteria have been proposed by the North American Electric Reliability Corporation (NERC) [7], which brings many challenges for conducting fast contingency analysis. Since it is computational onerous to evaluate all the contingencies at a time, a subset is usually selected for analysis in traditional contingency screening methods such as the performance index contingency ranking [8]. However, when a larger subset is required for the contingency analysis of a large-scale grid, it is difficult to achieve real-time execution. Meanwhile, the power-flow based contingency ranking methods fall short of provision of subsequent dynamic process after a disturbance, and are hence excluded for predictive control in an energy control center. Therefore, the transient stability (TS) simulation is adopted for DSA purpose. It enables the representation of the dynamic characteristics of all power system components in time-domain, which is a direct and precise method attributing to the utilization of detailed dynamic models [9]- [11].
The processing hardware is another aspect that limits the performance of DSA tools, which nowadays are usually supported by high-performance CPUs or multiprocessors for efficient simulation or even real-time execution [12]- [14]. Although presently CPU-based commercial DSA simulators are prevalent in stability analysis, the massive scale of the target power system, as well as the huge number of contingencies to be analyzed, always poses a significant challenge to the simulation efficiency. The utilization of the multiprocessors or supercomputers is a straightforward solution for real-time DSA due to the sufficient hardware resources and high processing frequency [15]. However, as many as 24,000 CPU cores may be needed to realize a near real-time simulation of a real power grid containing 3,000 generators [14], which is inconvenient and expensive for commercial use. Although parallel algorithms are utilized for accelerating transient stability simulation [16]- [21], the execution time will still increase along with the dimension of the admittance matrix [22], [23].
In this work, a multi-FPGA-based DSA platform is proposed to provide fast and accurate contingency screening data for a large-scale AC/DC grid by faster-than-real-time (FTRT) emulation. Compared with currently available commercial real-time (RT) simulation tools, the FPGA-based platform has the following advantages. The most straightforward difference between an FTRT emulation platform and RT simulators is the computation speed. RT simulation implies that the hardware must solve the model equations within an interval of the time-step. On the other hand, FTRT is stricter in terms of hardware latency, and the platform runs at least several times faster than a RT simulator. FTRT emulation can meet all the requirements of RT simulation, while the RT simulation tools are unable to reach FTRT due to their scalability and computational speed limits. Secondly, the capability and scalability of the FPGA-based FTRT emulation platform are better than RT simulators. For example, the 141-bus system with 38 generators is simulated using the RTDS simulator, and 4 PB5 racks were needed [24]. In order to reduce the hardware resources and reduce the cost, only 5 buses and 2 generators were simulated on RTDS , while the rest of the system parts were simulated on FPGA boards. As shown later in this paper, two 500-bus systems with 180 generators in total can be executed on a single Xilinx VCU128 board, which demonstrates the FPGA's capability in emulating a large power system. The reconfigurability and the sufficient hardware resources allow the entire grid to be deployed on the platform after proper system partitioning and allocation. Meanwhile, a specific AC/DC grid interface using dynamic voltage injection is proposed to maintain a constant admittance matrix despite the HVDC converter outputs being time-varying, which consequently reduces hardware resources utilization and expedite the emulation. As a result, the FTRT DSA emulation is more than 208 times faster than real-time.
Since the FTRT emulation enables a high computation speed above real-time, the grid can be emulated much faster and therefore it can accelerate planning schedules, predict the upcoming disturbances, and help in devising new control strategies. The proposed FTRT emulation can also be used in the energy control center to provide sufficient time to take remedial actions, recommend an optimal control strategy to mitigate adverse impacts, and enhance the overall stability and security of the system.
The rest of the paper is organized as follows: Section II introduces transient stability simulation, including modeling and solution of the AC grid. The DC grid modeling and its interfacing technique are specified in Section III. Section IV illustrates the hardware design on the proposed multiple FPGA based platform. The emulation results of more than 5500 contingencies, as well as their analysis and validation, are provided in Section V. Section VI presents the conclusion and prospective work.

A. Transient Stability Problem
The transient stability simulation for DSA is based on a set of differential algebraic equations (DAEs). The dynamic processes of the synchronous generators in a power transmission system can be summarized asẋ The network including transmission lines, transformers, and various loads are represented by the algebraic equation (3).
where x refers to the vector of state variables of the synchronous generator, u represents the vector of the inputs, such as the mechanical torque (T m ) from governor, and field voltages (E fd ) calculated in the exciter model. (2) provides the initial conditions of the synchronous machines, which can be obtained from the solution of the power flow data. The accuracy of the transient stability simulation is highly dependent on the solution strategies of the DAEs, which can be roughly classified into two categories: implicit and explicit integration methods. The former is essentially iterative methods such as Newton-Raphson, which has a higher accuracy under large time-steps. However, a large dimension of the DAEs may lead to more iterations in every single time-step and consequently extra execution time. Furthermore, due to the inherently sequential iterations until convergence, the iterative method is not suitable for parallel processing in FPGAs. Therefore, the explicit method 4th-order Runge-Kutta (RK4) is adopted in the hardware emulation for the high efficiency and low hardware resource demand, as given below x n+1 = x n + 1 6 (RK 1 + 2RK 2 + 2RK 3 + RK 4 ), (8) where x n+1 represents the vector of state variables for next timestep, and h refers to the emulation time-step, which is defined as 1 ms in this work.

B. Formulation of Synchronous Generators
To achieve high fidelity, a detailed 9 th -order synchronous generator model, which includes two mechanical equations, four electrical equations containing 2 windings on the d-axis and 2 damping windings on the q-axis, and an excitation system, is applied for dynamic security analysis.
The 2 mechanical and 4 electrical equations describing the generator are given aṡ and the excitation system model given in Fig. 1 is comprised of the following power system stabilizer (PSS) and automatic voltage regulator (AVR) equationṡ As an expansion of (1), the time-varying quantities in (9)-(17) contribute to vectors u and x, and the remaining coefficients such as ω R , H, D, R fd , R 1d , R 1q , R 2q , T R , K stab , T ω , T 1 , and T 2 are constant parameters of generators and the excitation system.
The detailed mechanical equations and swing equations of a synchronous machine are given above. In a practical power transmission system, the mechanical power is provided by the turbine governing system. In order to obtain a higher accuracy of the dynamic security analysis results, a four-stage governor system is also included as given in Fig. 2. To reduce the computational burden and execution time of the hardware emulation, the governor system equations are solved by Forward Euler with a time-step of 1 ms, which are not included in the 9 th -order DAEs.

C. AC Network Equations
The AC network mainly comprises transmission lines, transformers, loads, and shunt capacitors. The transmission lines and the transformers are represented as lumped π models. The fixed loads and shunt capacitors are treated as the admittance which is associated with the buses, given as where V Bus refers to the voltage of the local bus, P Load is the active power of the load, and Q Load represents the reactive power of the load or the shunt capacitor. Following the derivation of the admittance matrix of the AC network, the output current of the generators can be solved by the following matrix equations: where the subscription N and R refer to the generator nodes and the remaining nodes, respectively. Due to the absence of current injections to the non-generator buses, the current vector . The relationship of the generator output voltages and currents can also be derived by the network equations in (19), given as: where (19) are not yet known. The algebraic equations (21) and (22) provide the relationship between I N and U N by expressing voltages e d and e q as functions of the known state variables and the components of the currents.
where r a , X aq , X 1q , X 2q , X ad , X fd , and X 1d are constant parameters of the synchronous machine. After solving the I N and U N by combining (21)-(20), the non-generator bus voltages group in vector U R can be calculated directly.

A. HVDC Converter Average Value Model
The configuration of a 3-phase (N+1)-level modular multilevel converter (MMC) interconnecting the AC grid and DC grid is given in Fig. 3(a), where each phase contains 2 arms and each arm has N half-bridge submodules (HBSMs) and an arm inductor. In order to reveal the dynamics of the MMCs, the electromagnetic transient (EMT) simulation with a time-step of 200μs is selected for emulating the HVDC grid, which can meet the requirements of DSA. The time-step of 200μs also leads to The FPGA-based hardware FTRT emulation prefers the models that induce low latency, and therefore, the average value model (AVM) of MMCs is adopted for contingency screening due to its simplicity in addition to the capability of being interactive with a basic converter controller to study its impact on the primary system. The HBSMs are simplified into controlled voltage sources as shown in Fig. 3(b). When the upper switch S 1 is turned on, the capacitor is inserted; while it is bypassed when S 2 is turned on. Assuming that the capacitor voltages are well balanced in each arm, which means the average values of capacitor voltages are equal, given as the equivalent voltage source of an arbitrary submodule (SM i ) can be expressed as where S i refers to the switching function that takes the value 1 when the submodule capacitor is inserted and 0 when the SM is bypassed. As a result, the arm voltage can eventually be derived by the switching functions given as Since the well-balanced condition in the AVM yields no circulating current, the differential term in (25) can be neglected and the AC side output voltage is formulated as where S ui and S li represent the switching functions of upper and lower arms, respectively. In the HVDC grid, the reactive components such as the capacitor and inductor expressed by ordinary differential equations should be discretized for EMT simulation. The one-step integration method Trapezoidal rule is adopted for HVDC grid numerical calculation so that a discrete-time Norton equivalent circuit is utilized. The impedance of the capacitor and inductor take the form of Z C = Δt/2C and Z L = 2L/Δt, respectively. The corresponding current sources of the Norton equivalent circuit are given as Since the small time-step Δt guarantees the accuracy of EMT emulation, higher order integration methods are not adopted to reduce the computational burden.

B. AC-DC Grid Interface
The single-line diagram of the hybrid AC/DC grid is shown in Fig. 4, where the 6 ACTIVSg 500-bus systems [25] connect with a 6-terminal (6-T) HVDC system. MMC 1 and MMC 2 operate as inverter stations and connect with AC System 1 and 2 via Bus 9, respectively, while the remaining four terminals, all acting as rectifier stations, each delivers 100 MW active power from the connected AC grid via Bus 142. Since the AC grid undergoes transient stability simulation with a time-step of 1 ms, and the EMT emulation with a time-step of 200μs is applied to the HVDC system, the latter part should be calculated five times more frequent than the former before data synchronization to keep numerical stability. Furthermore, the distinct emulation strategies prompts an interface based on dynamic voltage injection strategy which enables the two types of simulations to be compatible in one program, in addition to maintaining a constant admittance matrix that results in acceleration of the hardware emulation.
The synchronous machines can not only be represented in detail by Park's equation as given in (9)-(14), but also constant voltage sources in the D-Q frame when their dynamics are not concerned. The HVDC converter stations in the EMT simulation can be treated as time-varying voltage injections to the AC grid, which are equivalent to the non-detailed machines in transient stability simulation. The dynamic voltages U Dm and U Qm in Fig. 4(b) of the HVDC converter stations are directly delivered to the AC grid and integrated with the AC network equations without updating the admittance matrix. Due to the voltage injection method, (20) can be expanded as: where the subscription n refers to the synchronous machine nodes represented by the detailed Park's equations, m are the nodes where converter stations locate, and n + m denotes the N generator nodes in (20). As the voltages calculated by the HVDC system are in D-and Q-axis, (29) which is based on complex numbers yields 4 real matrix equations: where G and B refer to the real part and the imaginary part of the corresponding Y matrix. Following the solution of DC grid, the components U Dm and U Qm in the above equations are known, while the values of U Dn and U Qn associated with the detailed synchronous machines are not directly known. After each step of integration, the synchronous voltages can be evaluated by the state variables. Since the values of U Dn and U Qn are available after (30) and (31) are solved, the subsequent equation (32) and (33) can then be solved. Meanwhile, the calculated current vectors I Dm and I Qm in D-Q frame are sent to the HVDC system for its next time-step emulation, as given in Fig. 4(b).

IV. HARDWARE EMULATION ON MULTI-FPGA PLATFORM
The proposed hybrid AC/DC grid is implemented on the integrated Xilinx Virtex UltraScale+ TM FPGA platform, which includes 2 VCU118 boards equipped with XCVU9P FPGA and 2 VCU128 boards containing XCVU37P FPGA. System 1 and 2in Fig. 4(b) are deployed on the 2 VCU118 boards, respectively. Due to abundant hardware resources of VCU128 boards, System 3 and 4 including the 6-T HVDC system are implemented on VCU128 Board 1, while the remaining 2 AC systems (System 5 and 6) are calculated on VCU128 Board-2. The reconfigurability of the FPGAs enables each circuit part or subsystem to be designed as a hardware module, and allows programming its function according to the application. After linking the hardware modules and designing the parallel components properly, the integrated AC/DC grid can be executed on the proposed platform.
The subsystems and functions which consist of the proposed integrated AC/DC grid written in C/C++ code are transformed into hardware modules by Xilinx Vivado high-level synthesis (HLS) tool. Then they, termed as IP cores, are imported into Vivado for block-level design. Due to the dynamic voltage injection strategy, the PCC voltages in the D-Q frame are chosen as the communication data among different FPGA boards, which is realized by the build-in IP Aurora 66B/64B core. The hardware block diagram along with the data stream is given in Fig. 5. Table I provides the latency and the hardware resource utilization of each circuit part in the proposed integrated AC/DC system, where the latency is defined in clock cycles which is 10 ns under the FPGA frequency of 100 MHz. The total latency of the AC grid can be calculated as 29 + 196 + 114 + 21 = 360T clk , with a transient stability time-step of 1 ms, the FTRT ratio of the AC system is over 1ms 360×10ns = 277. Since the hardware modules PQcontrol, MMCAVM, and MMCCNT can be solved in parallel, the overall hardware delay is determined by their maximum latency which is 96 T clk, resulting in an FTRT ratio of 200μs 96×10ns = 208. Thus, the overall FTRT ratio of the hybrid AC/DC grid as Case I is determined by the EMT emulation part, which gives a final 208 times speedup over real-time. In contrast, if a single ACTIVSg 500-bus system without DC grid is analyzed as Case II, the FTRT ratio of the pure AC grid is more than 277, where six 500-bus systems can be executed concurrently in the integrated FPGA boards. Fig. 6 provides the hardware platform for FTRT emulation. The functions which represent the target power transmission system and the initial conditions of the synchronous generators are downloaded from the host computer via the Joint Test Action Group (JTAG) interface. Since multiple FPGA boards are assembled, data communication among them is also a challenge in emulating such a complex system. The Xilinx Virtex UltraScale+ TM series FPGA boards provide efficient communication ports, such as Quad Small Form-factor Pluggable (QSFP), Samtec FireFly interfaces, which can significantly accelerate the communication speed, since both interfaces can provide a maximum bidirectional communication rate of 4×28 Gbps, which can be utilized for delivering the current operating conditions from real power transmission system or other FPGA boards, making the proposed FTRT emulation suitable for online DSA in the energy control center. Once a disturbance is detected, the real-time operation data from the field will be delivered to the control center. Meanwhile, there could be hundreds of scenarios being emulated in the FTRT emulation platform for a comprehensive study. Since a more than 208 FTRT ratio can be achieved, the power control center has sufficient time to come up with optimal strategies for contingencies in various subsystems that help maintain the stability of the entire system.
The scalability of the proposed FTRT emulation is demonstrated by interconnecting four FPGA boards in realizing the FTRT emulation, and more FPGA boards can be connected along with a further expansion of the AC/DC grid. Table I indicates that the hardware resources such as DSP and LUT of VCU128 board are nearly full for two 500-bus systems with 180 generators. Although the Network module will increase along with the size of the system, its influence can be neglected if multiple synchronous generators are included since the Network module is only calculated once in a single time-step. The hardware resource utilization is proportional to the synchronous generators, and therefore, a Xilinx VCU128 board is able to accommodate about 180 generators with excitation and governor system in parallel. With a larger power system scale, the multiple FTRT emulators can be employed in the dynamic security assessment for HIL emulation or predictive control.

A. Dynamic Security Index
The contingency screening for dynamic security analysis is based on the system in Fig. 4. The transient stability analysis focuses on the rotor angle stability, voltage stability, and frequency stability, and the rotor angle stability is described as the power angle-based stability margin (ASM), which is defined as follows for each AC grid in the system.
where δ max is the maximum angle separation of any two generators in the same AC subsystem at the same time in the post-fault response, which is illustrated in Fig. 7(a). The transient stability index of a contingency is chosen as the smallest index among all 6 AC grids. ASM is directly proportional to rotor angle separation so it provides an indication of severity of a disturbance. A smaller-than-zero ASM indicates that the δ max is larger than 360 unit, which means the generators lose synchronism and the system is under unstable condition, while ASM>0 corresponds to a secure system status.

B. Case 1: Hybrid AC/DC Grid
At t = 1 s a three-phase-to-ground fault lasting 180 ms occurs at Bus 16in System 1, the imminent impacts including severe disturbances to the rotor angles, bus voltages, and frequencies, as shown in Fig. 7(a), (b), and (c). Fig. 7(a) demonstrates that the maximum angle separation (δ max ) is less than 360 unit, and therefore, the system is under secure condition. Although one of the frequencies exceeds the ±1% threshold after the three-phase fault, it restores to the normal operation eventually. Fig. 7(d), (e), and (f) provide the emulation results after a long-term over-load. At 1 s, a 90% over-load occurs to the load at Bus 392in System 1. There are no significant impacts on the rotor angles of the synchronous generators as given in Fig. 7(d). However, the bus voltages and the frequencies of the generators keep decreasing after the over-load disturbance and cannot be recovered by the generators' control system. The whole system enters the unstable condition at around 9 s when the frequencies reach below 59.4 Hz. The dashed lines represent the results calculated from the simulation tool TSAT , while the solid lines refer to the FTRT emulation results from FPGA boards. The zoomed-in plots in Fig. 7(b) and (f) demonstrate that the accuracy of the proposed FTRT emulation since the waveforms of the hardware emulation are identical to TSAT off-line simulation results. Fig. 8(a) provides ASM results calculated from FTRT emulation under 1890 three-phase-to-ground fault contingencies in System 1. The x-axis denotes the fault duration ranging from 100 ms to 300 ms, and the y-axis is the fault locations at Bus 1 to 90, which are generator buses. As mentioned, the ASM results below zero represent the unstable conditions, and therefore, the whole system may come to an insecure state if a three-phase-to-ground fault lasting more than 250 ms occurs at Bus 17. Fig. 8(b) demonstrates the frequencies after 9 s of the overload happening on the load number 1 to 90 with various overload percentages. It shows that the entire system is insecure regardless of which bus is overloaded by more than 80% for 9 s.
Aiming at demonstrating the accuracy of the proposed FTRT emulation, Table II gives the contingency screening results and errors for 90 300-ms three-phase-to-ground faults at each generator bus. The relative errors given in Table II are calculated by the following formula: The maximum relative error among the 90 contingencies is 0.49 %, which thoroughly demonstrates the accuracy of the proposed method.

C. Case 2: Purely AC Grid
In Case 2, the 6-T HVDC system is omitted, and a single ACTIVSg 500-bus system is taken into consideration. The utilization of the integrated FPGA platform enable six contingencies to run concurrently in the FTRT emulation platform with , and (f) show the emulation results of 90% generation reduction on Generator 1. Fig. 9(f) indicates that the frequencies of synchronous generators keep decreasing and cannot be restored. Fig. 10(a) gives the ASM results for 1890 open circuit contingencies that occur on each generator bus under various fault duration, which demonstrates that the entire system is more likely to be insecure with a longer fault. Fig. 10(b) provides 900 ASM results for various generation reduction percentages of each generator. Although the ASM results show that the system is secure, the frequencies after the generation reduction will not be restored without extra power injection as given in Fig. 9(f). It indicates that the proposed DSA platform may reveal more potential risks with the utilization of time-domain emulation. The contingency screening results for 90 open circuit faults are given in Table III. The maximum relative error is merely 0.81%, which demonstrates that the accuracy of the proposed FTRT emulation is suitable for online DSA in the energy control center.

D. Accuracy Validation
In order to validate the the accuracy of the proposed modeling and hardware implementation approaches, an underdamped case is emulated. Fig. 11(a), (b), and (c) provide the emulation results for an underdamped excitation system, where the PSSs for all synchronous generators have been removed. At t = 1s, a three-phase-to-ground fault lasting 180 ms occurs on Bus 17, the generator rotor angles start to oscillate without recovery. The zoomed-in plots in Fig. 11(a), (b), and (c) demonstrate that the FTRT emulation results are matched well with the results calculated from TSAT in an underdamped system. Furthermore, the emulation results are also provided to validate the accuracy of the proposed FTRT emulation under a three-phase-to-ground fault which is cleared near the critical clearing time (CCT), as given in Fig. 11(d), (e), and (f). As Fig. 8(a) shows the CCT of the three-phase-to-ground fault at the bus of Bus 17 is 250 ms. Therefore, Fig. 11(d), (e), and (f) provides the emulation results of a three-phase-to-ground fault lasting 249ms at Bus 17. Fig. 11(d), (e), and (f) indicate that the fault causes a severe oscillation including rotor angles, bus voltages, and frequencies. The zoomed-in plots demonstrated the accuracy of the proposed FTRT emulation can still be guaranteed even when the fault is cleared near the CCT. Meanwhile, the ASM results for two serious three-phase-to-ground faults calculated from FTRT emulation and TSAT are provided in Table IV, which indicates that the accuracy of the proposed method can be guaranteed for the contingencies that are cleared around the CCT. The emulation time-step Δt is another important factor, which could influence the performance and accuracy of the FTRT emulation. As mentioned, 1 ms is utilized in the AC grid for DSA, while the time-step of 200μs is adopted in the HVDC part for EMT emulation. The adoption of 200μs is justified by the type of study in this work, where the converter system-level dynamics such as output power and reactive power, instead of the converter electromagnetic transient details, are the main focus. In the dynamic security assessment, the commonly used time-step ranges from 1 ms to 10 ms. A dramatic computational advantage can be achieved with the time-step of 200μs, and a 200μs 96×10ns = 208 FTRT ratio can be obtained. On the other hand, with the time-step of 50μs, the FTRT emulation can still be achieved, given as 50μs 96×10ns = 52. The emulation results of output active power of the MMC 1 and 3 under various time-steps and relative errors are given in Fig. 12. Fig. 12(b) indicates that there is no significant improvement in emulation accuracy under the time-step of 50μs. However, the acceleration has a significant drop if 50μs is adopted. Therefore, after a trade-off between the emulation accuracy and computational speed, the 200μs is selected as the emulation time-step of the HVDC grid.

VI. CONCLUSION
This paper proposed a screening strategy of extensive contingencies in faster-than-real-time mode of execution for a comprehensive dynamic security analysis of large-scale integrated AC/DC grid. Due to the pipelined hardware design method and parallelism of AC/DC grid modules, the EMT and TS co-simulation is introduced to provide more detailed operation conditions of the integrated AC/DC grid for dynamic security analysis. A dynamic voltage injection interface for AC/DC grid is proposed, which enables the EMT and TS co-simulation executing as one program without updating the admittance matrix in every time-step. The proposed interface strategy is also suitable for the data communication among FPGA boards as its less data transferred, which can further accelerate the FTRT emulation by reducing the communication delay. An FTRT ratio of 208 can be obtained for the hybrid AC/DC grid, while the FTRT ratio is over 277 times for a pure AC system. The contingency screening results of the more than 5500 contingencies from the FTRT DSA hardware emulation platform are well matched with those of TSAT off-line simulation. Therefore, a guaranteed accuracy and execution speed of the proposed FTRT emulation methodology suggest its importance in planning and operation of a practical power system in scenarios such as online DSA.