The NEORV32 RISC-V Processor

What's Changed

• Remove signal initalizations by @tmeissner in https://github.com/stnolting/neorv32/pull/464
• Upgrade on-chip-debugger by @stnolting in https://github.com/stnolting/neorv32/pull/463
• ⚠️ rework CPU debug spec ISA configuration; ✨ enhance trigger module by @stnolting in https://github.com/stnolting/neorv32/pull/465
• [sw] rename library functions by @stnolting in https://github.com/stnolting/neorv32/pull/467
• [rtl] OCD: update DTM and DM by @stnolting in https://github.com/stnolting/neorv32/pull/468
• Fix value of SYSINFO_SOC_IO_ONEWIRE in NEORV32_SYSINFO_SOC_enum by @tmeissner in https://github.com/stnolting/neorv32/pull/469
• [rtl] CPU: logic optimization by @stnolting in https://github.com/stnolting/neorv32/pull/470
• [sw/example/demo_spi_irq]: make read/write data pointer and busy flag… by @akaeba in https://github.com/stnolting/neorv32/pull/471
• [rtl] update TRNG by @stnolting in https://github.com/stnolting/neorv32/pull/472
• [rtl/test_setups] add on-chip debugger test setup by @stnolting in https://github.com/stnolting/neorv32/pull/473
• :warning: rework watchdog timer (WDT) by @stnolting in https://github.com/stnolting/neorv32/pull/474
• [rtl] VHDL cleanups by @stnolting in https://github.com/stnolting/neorv32/pull/476
• :warning: Rework CPU counters by @stnolting in https://github.com/stnolting/neorv32/pull/477
• [sw] cleanup and update software framework by @stnolting in https://github.com/stnolting/neorv32/pull/478

Full Changelog: https://github.com/stnolting/neorv32/compare/v1.7.9...v1.8.0