A 2‐mA charge‐balanced neurostimulator in 0.18‐μm/1.8 V standard CMOS process

This paper presents a programmable neurostimulator 4 × VDD with 7.2 V operating voltage in a 0.18‐μm/1.8 V CMOS process. The output voltage compliance exceeds 6.2 V. A current gain control is designed to adjust bias current. A 5‐bit current mode digital‐to‐analog converter (DAC) is used to set delivered current in current driver. A high output impedance current mirror is designed to guarantee charge balancing. The charge mismatch after biphasic stimulation is about 0.14%. Moreover, current mirrors are turned off after stimulation to decrease power consumption. The headroom voltage is about 1 V for all the voltage drivers and the current mirrors. The proposed neurostimulator occupies 0.95 × 0.95 mm2 with a maximum current range of 0–2000 μA and a power consumption less than 60 μW.

ENS is based on electrical injecting charge to the nerve tissues to evoke action potentials as a means of modulating the neural activity. The charge can be injected either by voltage-mode stimulation (VMS) or by current-mode stimulation (CMS). In VMS, charge injection is performed by a constant voltage, which is applied between the stimulating electrode and return electrode. 32 The VMS has the advantage of higher energy efficiency 33,34 but has the disadvantage of a lack of control over the charge delivered to the tissue due to variability of the neurological impedance. 35 The impedance of neural tissue can significantly change over time and particularly in the period immediately after implantation. 36,37 The CMS is widely in neural stimulation for its precise charge control. In CMS, the charge is delivered by a constant current source, and its quantity is directly controlled by the amplitude and duration of the stimulation under variable impedance. [38][39][40] Higher voltage compliance of the current-mode stimulators allows delivering a wider range of currents to the load. 41 However, there are several challenges facing neural stimulator design. Reducing the size of the device and power consumption and safe electrical stimulation are some of the crucial issues that should be addressed in the design of ENS.
Two major challenges in the design process are size reduction and power consumption. The voltage drop across electrodes themselves consumes part of the power, and the rest of the power is consumed through heat dissipation. The latter should be minimized to improve power efficiency. 14,40,42 An important issue in the neural stimulators is the voltage compliance. For high current stimulation such as deep brain stimulation, where tissue impedance is high, voltage compliance exceeds from chip's supply voltage, and current mirror and driver become saturated. For injecting proper current to the neural tissue, two general methods are proposed. First method uses high voltage (HV) technology in order to get desired voltage compliance resulting expense of area and power consumption. 21,[43][44][45][46][47] The second method used stack transistor to tolerate high supply voltage in low voltage process. The benefit of stacking technique is that the stimulator can be fully integrated with digital peripherals without changing technology. 14,22,[48][49][50] In Ghovanloo and Najafi, 40 in order to achieve HV compliance, a CMOS current source, which uses MOS transistor in deep triode region as voltage-controlled resistor, is proposed. The resistor is implemented as NMOS transistor. The NMOS dynamic resistance changes almost directly with its gate-source voltage and therefore controls stimulus current.
One of the prime concern in the design of the neural stimulators is the safe long-term electrical stimulation. A net charge above a small "safe charge injection" threshold will cause tissue destruction and has to be avoided under all conditions. 51 Hence, charge-balanced biphasic stimulation pulses are used to recover delivered charge and thus mitigate toxicity from electrochemical reactions occurring at the metal-tissue interface.
Several charge-balancing circuits have been proposed to achieve safely charge-balanced biphasic stimulation. Passive and active charge balancing are two general methods to cancel the residual average mismatch charge. 16,[52][53][54][55][56][57][58][59][60][61][62][63][64][65][66][67][68][69] In passive charge-balancing technique, a large dc-blocking capacitor is inserted in series with each electrode. For functional electrical stimulation (FES) applications, these capacitors are about a few microfarads. 52 These capacitors cannot be fully integrated with stimulation circuitry and must be implemented off-chip. Off-chip dc-blocking capacitors are a serious limitation for developing multichannel implantable stimulators. To overcome this problem, high-frequency current-switching (HFCS) was proposed for dc blocking. 53 In this technique, the stimulation current pulse during cathodic phase was generated by summation of the two high-frequency current pulse trains. The proposed approach could reduce the capacitance value to the picofarad range. A few charge balancing based on electrode shortening has also been implemented in other works. 25,56,63,64 In this method, the electrodes are shorted after stimulation period for a certain period of time. Since the current mismatch and the electrode impedance are not known and also vary over time, the discharge time is not known.
Several active charge balancing circuits have also been proposed in the literatures, 16,45,54,55,[57][58][59][60]65 including pulse insertion, 45 charge balancing based on offset regulation, 16,55,59,60 and digital approach to balance charge mismatch. 57 In Song et al., 58 an active charge balancing was proposed, which is based on combination of the instantaneous charge balancing during negative phase and the offset current regulation after the biphasic stimulation.
In Lee et al., 65 charge balancing was achieved by sharing the closed loop path of the adaptive supply to push or pull small current pulses after stimulation in the tissue in order to keep residual charges within safety limit. In Luo and Ker, 66 two novel current memory cells with sample and hold technique were proposed to provide the charge mismatch less than 25%. In this method, the output current of a digital-to-analog converter (DAC) was sampled by a memory cell in the first phase. Then, the path of DAC was disconnected, and the stored current from the memory cell flowed to another memory cell. In the third phase, anodic, interphase delay, and cathodic part of the stimulation signal were generated. In the final stage, the anodic and cathodic electrodes were shorted to ground. This method employed capacitor in current memory cell, which will cause to decrease the area efficiency. In Hsieh and Ker, 67 a discharge circuit in each stimulus driver was designed to release unbalance charge in tissue by shortening the electrodes to ground. Dynamic current copy technique was also used for equalizing the current for both the anodic and the cathodic phases. 68 In this technique, the current of one driver for the other driver was duplicated during a calibration phase preceding the stimulation. At the end of the second stimulation phase and after a gap, all the electrodes are grounded. In Pu et al., 69 a time base charge balancing circuit was proposed to reduce charge imbalance. It consisted of a voltage-to-time converter and a compensation current source/sink. It used a feedback mechanism to monitor the residual voltage on the stimulating electrode. Then, the residual voltage was converted to time using a voltage-to-time convertor. Charge balancing was achieved by repetitive injection of the current pulses whose durations were controlled by the voltage-to-time convertor.
In Luo and Ker, 66 two novel current memory cells with sample and hold technique were proposed to provide the charge mismatch less than 25%. In this method, the output current of a digital-to-analog converter (DAC) is sampled by a memory cell in the first phase. Then, the path of DAC is disconnected, and the stored current from the memory cell flows to another memory cell. In the third phase, anodic, interphase delay, and cathodic part of the stimulation signal are generated. In the final stage, the anodic and cathodic electrodes are shorted to ground. This method uses capacitor in current memory cell, which decreases the area efficiency. In Hsieh and Ker, 67 a discharge circuit in each stimulus driver was designed to release unbalance charge in tissue by shortening the electrodes to ground. Dynamic current copy technique was also used for equalizing the current for both the anodic and the cathodic phases. 68 In this technique, the current of one driver for the other driver was duplicated during a calibration phase preceding the stimulation. At the end of the second stimulation phase and after a gap, all the electrodes are grounded. In Pu et al., 69 a time base charge balancing circuit was proposed to reduce charge imbalance. It consisted of a voltage-to-time converter and a compensation current source/sink. It used a feedback mechanism to monitor the residual voltage on the stimulating electrode. Then, the residual voltage was converted to time using a voltage-to-time convertor. Charge balancing was achieved by generating and repetitive injection the compensation current pulses whose durations were controlled by the voltageto-time convertor.
In this paper, a programmable current micro-stimulator, which uses high output impedance current mirror, is proposed. The circuit utilizes current gain control to adjust referenced current for the specific application. Moreover, 5-bit current mode DAC is used to change the current amplitude for the desired target. In order to mirror DAC current precisely, a high output impedance current mirror based on gain boosting technique is used. By this technique, the target current remains constant during tissue and electrode impedance changes. Moreover, the anodic and cathodic charges are balanced after biphasic stimulation. To achieve HV compliance, a stacked H-bridge current driver is used. The frequency and voltage amplitude of stimulus pulses are controlled by the logic circuits and the DAC current, respectively. To reduce the power consumption, the current driver and current mirror are turned off after stimulation.
This paper is organized as follows; in Section 2, a proposed structure is explained. Transistor level design is presented in Section 3. Post-layout simulation results are reported in Section 4, and finally, the paper is concluded in Section 5. Figure 1 shows the two topologies of neurostimulator drivers. In the dual-supply voltage architecture (2 Â V DD and À2 Â V DD ), the biphasic pulses were generated by the current sourcing/sinking to/from one electrode ( Figure 1A). In a multichannel stimulator using the dual-supply voltage architecture, a common ground electrode is shared across channels. This sharing technique reduces the number of stimulation electrodes to N-1 for N channel neurostimulator. When using low voltage CMOS process in a stacked configuration to provide a high-voltage compliance, the maximum voltage compliance is 2 Â V DD as shown in Figure 1A, where V DD is the supply voltage. In this case, the voltage compliance is limited by 2 Â V DD . For high-voltage compliance applications, the H-bridge with single-supply voltage is preferred. In this case, for each channel, two electrodes are needed to generate biphasic pulses ( Figure 1B). The driver circuitry reverses the current direction through the tissue. The benefit of this technique is that the voltage compliance is two times more than that in the dual-supply voltage architecture. In the current study, single-supply voltage with low voltage CMOS process in a stacked configuration is employed to provide high-voltage compliance. A combination of high output impedance current mirror and HV-tolerant current driver is proposed to reduce the charge mismatch between the anodic and cathodic currents. Figure 2 shows the proposed structure of the neural stimulator. The reference current is generated by reference current generator. This current is adjusted by current gain control for the specific application. The 5-bit current mode DAC is used to provide the necessary current resolution for the desired target. DAC output is mirrored to the high output impedance current mirror. This structure guarantees constant stimulus current to be delivered to the tissue. The proposed structure uses single supply voltage to generate biphasic pulses. The benefit of this technique is that the voltage compliance is two times more than that in the dual-supply voltage architecture. However, this technique can be used for bipolar stimulation in which two electrodes are required for each stimulation channel. This will cause to increase the number of stimulation electrodes, which is a major limitation for applications that require a large number of electrodes. In a multichannel stimulator using the dual-supply voltage architecture, only one electrode is required for each stimulation channel and a common ground electrode, which is shared across all channels. To tolerate high-voltage power supply, we employ a high-voltage current driver implemented in the low voltage CMOS process. 70 Furthermore, to control the voltage at each terminal, a HV bias circuit proposed by Luo and Ker 66 is used here. Two level shifters are used to convert low level voltage to high level voltage with DC offset of 3 Â V DD . In order to avoid short circuit current in output stage, a non-overlap clock phase is used to drive the level shifters.

| CIRCUIT DESIGN
3.1 | Current reference and gain control Figure 3 depicts the proposed circuits of the current reference and gain control. A capacitive coupled network is used in the current reference for fast startup. 70,71 In the current study, the reference current is set to 4 μA (I ref ). The current gain control consists of I GC1 and I GC2 to generate current for different applications. For this purpose, we set the values of I GC1 and I GC2 to 1 and 8 μA, respectively. I GC1 can be used for low current applications such as epilepsy suppression in rat and I GC2 for high current stimulation such as epilepsy suppression in human.

| DAC
A 5-bit binary weighted current mode DAC is used to generate desired stimulation current. In this structure, one bit in the digital input directly turns a relative current source on or off. 72 The amplitude of the stimulation current can be changed according to digital code receiving from the external control unit. Figure 4 shows the schematic of the DAC in which the maximum currents (I DAC ) are 31 and 248 μA based on I GC1 and I GC2 values, respectively.
F I G U R E 3 The current reference and gain control circuit

| High output impedance current mirror
In order to mirror DAC current, a high output impedance current mirror based on gain boosting technique is designed. For reducing the DAC transistor sizes, the output transistors of current mirror are properly sized to mirror 8 Â I DAC . However, the gain boosting technique causes to increase power consumption. To mitigate this problem, the op-amp in feedback loop is turned off after biphasic stimulation. Figure 5A shows the schematic representation of high performance current mirror in which maximum mirrored current are 248 and 1984 μA based on I GC1 and I GC2 , respectively. The output impedance can be written as: where g m1 , r ds1 , r ds2 , and A are transconductance of M 1 , output resistance of M 1 , output resistance of M 2 , and DC gain of the op-amp, respectively. To the best of author's knowledge, the other proposed advanced current mirrors cannot mirror high current precisely in the same technology. The amplifier used in the current mirror is folded cascade due to high DC gain, [73][74][75][76] which is shown in Figure 5B.

| HV current driver
To achieve high-voltage-tolerant power supply, a current driver, which is based on stacked transistors and high output impedance current mirror, is proposed ( Figure 6). As shown in Figure 6, two current mirrors are implemented at the bottom of the current driver in order to mitigate switching error due to clock feed through and charge injection. 66 Moreover, one of the high output impedance current mirror can be used as an auxiliary current mirror. Moreover, using two current mirrors enables the current gain control block to be able to adjust the stimulation current for the low and high current applications. This topology reduces current error, which is calculated in Section 4. The output stage is composed of four PMOS-stacked transistors for the pull-up switch and three NMOS-stacked transistors as well as a high output impedance current mirror for pull-down switch. The proposed strategy can withstand to four times the nominal supply The high-voltage current driver voltage (4 Â V DD ). The stacked transistors are driven by a bias circuit to limit the maximum voltage across each terminal of the stacked by the nominal supply voltage (V DD ), which is specified by the industry limit (Figure 7). The high output impedance current mirror guarantees the anodic and cathodic currents to be equal. Since, mismatches of the transistor parameters are undeniable during fabrication. We also used electrode shorting technique to remove the extra charges after biphasic stimulation. 49,50,66 The switches based on NMOS transistors are used to pull down extra charges to the ground. A self-adaption bias circuit, which was proposed by Lee et al., 65 is used here.
An important issue in switching procedure is the parasitic elements, which can cause unexpected shortcomings. The source inductance (L S ) and drain inductance (L D ) are two main parasitic elements, which exhibit significant restriction in switching performance. The instantaneous rate in current over time di=dt ð Þ can be high during switching off. Therefore, the parasitic inductance would produce a high turn-off surge voltage v ¼ L Á di=dt ð Þ . Moreover, the voltage spikes, which are produced during the switching, can cause instantaneous current spike and may induce tissue damage. In addition, this spike may harm the transistor because the terminals' potential differences exceed the maximum tolerable range of transistors. Hence, these unwanted spikes should be suppressed. Reducing the switching speed leads to a smooth transition and minimizing the charge buildup and the current spike level. In the proposed high-voltage-tolerant buffer, the PMOS switching transistor (M S1 and M S2 ) is synthesized by a chain of the scaled inverters. This chain of inverters is connected to M S1 and M S2 gates. Using this method, a large series resistance is added to the resistance of the gate and the time constant increases. Thus, the switching speed is decreased, and smooth transition is achieved. In addition, extending the falling or rising time of the applied pulses to the gate of the transistors can help suppress the spikes.
To develop high-voltage-tolerant driver in low-voltage process using stacked transistors strategy, the maximal voltage of the upper stacked transistor should be limited by the breakdown voltage of the parasitic well diode. In order to decrease overdrive voltage of the stacked transistor, and increase the output voltage compliance, the substrates of the stacked transistors are connected to their source terminals. Moreover, the stacked transistors are implemented with the 1.8 V PMOS and NMOS process with the deep n-well layer. Figure 8 shows an NMOS transistor with the deep n-well layer.
F I G U R E 7 Terminal voltage of the transistor M PD3

| High-voltage level shifter
The level shifter employed in this study is shown in Figure 9. 66

| POST-LAYOUT SIMULATION RESULTS
The design and simulation were performed using 0.18-μm/1.8 V 1P6M CMOS process. The open loop frequency response of the folded cascade op-amp is shown in Figure 10. It can be seen that the DC gain and phase margin of designed op-amp are about 83 dB and 60 , respectively. Figure 11 shows the 2-mA full-scale output of both the anodic and cathodic current sources. The results demonstrate that a perfect linearity between input and output currents is obtained. Moreover, no biphasic current mismatch is observed. Figure 12 shows the output current source versus the voltage across the current source. It can be seen that the current source requires a minimum 0.1 V to maintain a constant current output at 128 μA and 0.3 V for the current output of 1984 μA. The output impedance of the current source indicated in Figure 12 is above 14 MΩ. Figure 13A shows the lumped circuit model of the electrode-tissue interface, where the loading of stimulator is 1.7 kΩ in series with parallel 100 nF capacitor and 10-MΩ resistor. The electrode model current is depicted in Figure 13B without using the chain of inverters (for the gates of M S1 and M S2 ). Figure 13C shows the voltage and the  Figure 14 shows the residual voltage on 100 nF capacitor at 2-mA stimulus current for biphasic stimulation, where the stimulator loading is 1 kΩ resistor in series with the parallel 100 nF capacitor and 10 MΩ resistor. The accumulated residual voltage at the end of 10 biphasic stimulations is about 42.2 mV. Hence, the average residual voltage for one cycle of biphasic stimulation is 42:2mV=10 ¼ 4:22mV, which is within the safety of ≈±100 mV. A residual voltage of 11.89 mV for one-cycle biphasic stimulation was reported by Luo and Ker. 66 The injected charge in one biphasic stimulation cycle is about 1984 μA Â 160 μs ffi318 nC that results in charge error of 4.22 mV Â 100 nF = 0.422 nC. Hence, the charge mismatch is about 0.422 nC/318 nC ffi0.14%. After shorting operation, the residual charge of the capacitor is discharged as 66 where q t ð Þ is the residual charge after shorting operation in t seconds, q 0 ð Þ is the residual charge before shorting operation, and R and C are the resistance and capacitor of the electrode model, respectively. The charge error is 0.422 nC; the time constant is 1 KΩ Â 100 nF = 100 μs. The shorting time is 1000 À 480 = 520 μs (with the period of 1000 μs, anodic, cathodic, and inter-phasic delay time of 160 μs). Thus, the residual charge is about e -5:2 . At the end of shorting time, the residual average DC current is calculated as 0:422nC Â e -5:2 =1ms = 2.3 nA.
The physical layout of the proposed stimulator is shown in Figure 15, which occupies 600 Â 600 μm 2 active core area. The total area in the presence of the all pads is about 950 Â 950 μm 2 . The size of all pads including electrostatic discharge (ESD) protection is 100 Â 100 μm 2 . Table 1 shows the current mismatch and power consumption at the different process corners for the different temperatures. The results show the robustness of the proposed design during different temperatures. Table 2 shows a primary comparison of the proposed neurostimulator with other stimulators. It can be seen that the charge mismatch is less than 0.14%, which resulted from post-layout simulation. However, it should be noted that the mismatch reported in many previous works was experimental results while the value reported in the current study was the result of post-layout simulation. We also define a figure of merit (FOM) to evaluate better performance of the design as follows:

| CONCLUSION
A HV-tolerant neurostimulator is designed and post-layout simulated in 0.18-μm 1.8 V low voltage CMOS technology.
Using H-bridge with two separate electrodes and single supply voltage, the voltage compliance is increased. Moreover, the high output impedance current mirror is used to guarantee charge balancing in anodic and cathodic phases. To decrease power consumption, the current mirror is turned off after biphasic stimulation. Based on the operating voltage, a maximum current range of 0-2000 μA and a power consumption less than 60 μW were achieved. Table 2 shows the current mismatch and power consumption at the different process corners for the different temperatures. The results show the robustness of the proposed design. Compared to Luo and Ker,66 which was based on 0.18-μm/3.3 V low voltage CMOS process, the proposed stimulator only consumes 0.95 Â 0.95 mm 2 while 66 occupying 1.2 Â 0.9 mm 2 . The designed stimulator occupies 600 Â 600 μm 2 active core area.

DATA AVAILABILITY STATEMENT
Data are available on request from the authors. Authors confirm that they have no primary function other than research and education.