A 0.6V$-$1.8V Compact Temperature Sensor with 0.24{\deg}C Resolution, $\pm$1.4{\deg}C Inaccuracy and 1.06nJ per Conversion

This paper presents a fully-integrated CMOS temperature sensor for densely-distributed thermal monitoring in systems on chip supporting dynamic voltage and frequency scaling. The sensor front-end exploits a sub-threshold PMOS-based circuit to convert the local temperature into two biasing currents. These are then used to define two oscillation frequencies, whose ratio is proportional to absolute-temperature. Finally, the sensor back-end translates such frequency ratio into the digital temperature code. Thanks to its low-complexity architecture, the proposed design achieves a very compact footprint along with low-power consumption and high accuracy in a wide temperature range. Moreover, thanks to a simple embedded line regulation mechanism, our sensor supports voltage-scalability. The design was prototyped in a 180nm CMOS technology with a 0{\deg}C $-$ 100{\deg}C temperature detection range, a very wide supply voltage operating range from 0.6V up to 1.8V and very small silicon area occupation of just 0.021$mm^2$. Experimental measurements performed on 20 test chips have shown very competitive figures of merit, including a resolution of 0.24{\deg}C, an inaccuracy of $\pm$1.4{\deg}C, a sampling rate of about 1.5kHz and an energy per conversion of 1.06nJ at 30{\deg}C.


I. INTRODUCTION
T EMPERATURE sensors are crucial to allow dynamic thermal management (DTM) in complex Systems on Chips (SoCs) [1]- [4].Multiple sensors are distributed across the die to identify potential hot/cold-spots, and the collected temperature information is used to keep the operation of the chip within the target thermal condition, thus ensuring both Manuscript received February.XXX, 2022.This work has been partially supported by the Ministero dell'Istruzione, dell'Universit à e della Ricerca (MIUR) CrossLab Departments of Excellence Grant, and in part by the ECSEL Joint Undertaking (JU) under grant agreement No 876362.The JU receives support from the European Union's Horizon 2020 research and innovation programme and Finland, Austria, Belgium, Czechia, Germany, Italy, Latvia, Netherlands, Poland, Switzerland.
© 2022 IEEE.Personal use of this material is permitted.Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works.DOI: 10.1109/JSEN.2022.3171106performance and reliability [2]- [4].The temperature safety can be maintained while accommodating dynamic voltage and frequency scaling (DVFS), powering on/off different portions of the system and/or implementing other adaptive thermal adjustments like fan speed regulation [1], [5], [6].Some proposed temperature sensors [7]- [20] exhibit the required sensing accuracy for proper DTM.A typical requirement for multi-core systems is a modest absolute inaccuracy of 8 °C and a more constrained relative inaccuracy of 3 °C [8], [21].Additional requirements are imposed by recent technology trends, such as multi-processor chips, 3-D integration and multi-supply voltage architectures [7].Particularly: 1) Small size is a highly desired feature to enable very dense thermal monitoring, as required in state-of-the-art VLSI designs.In fact, due to the ever-increasing level of integration of modern SoCs, the number of possible hot/cold-spots is rapidly growing with the consequent growth in the number of required temperature sensors for effective DTM (e.g., more than 60 in the POWER9 systems [5]).Moreover, a compact footprint is further important to ensure flexibility in the design process, since the optimal sensor locations (e.g., very close to the possible hot/cold-spots) often are identified only in the later stages of the design phase and, typically they are in very dense areas of the chip [8].2) Robustness is essential: A temperature sensor needs to maintain its sensing accuracy under voltage and process variations.In fact, overestimating the temperature can cause unnecessary performance throttling, while underestimating can lead to reliability issues.3) Broad supply voltage scalability is a further requirement [7].Today's SoCs often implement DVFS techniques to tune performance while managing power consumption, especially for digital portions of the system.The supply voltage can be dynamically modulated down to near threshold levels when reduced performance allows saving energy.It is therefore desirable that temperature sensors support supply voltage scalability in order to share the same power grids with the digital circuits.Unfortunately, some of the previously proposed temperature sensors turned out to be not enough voltage scalable [9], [11], [14]- [16], [19], and/or do not support sub-1 V operation [8], [15]- [17], [19], [22].
This paper introduces a small-area fully-integrated CMOS temperature sensor, suitable for aggressive circuit placement (i.e., very close to target hot/cold-spots) in SoCs.A lowcomplexity PMOS-based sensing circuit converts the local temperature into two sub-threshold biasing currents.These are then used to define two oscillation frequencies, whose ratio increases linearly as the temperature rises.Such frequency ratio is then translated into a digital output code, through a digital back-end, based on binary counters.Thanks to a simple embedded line regulation mechanism, the proposed design can operate in a wide power supply range, thus resulting to be appealing for those systems which support multi-supply voltages and/or DVFS.When fabricated in 180 nm CMOS for the target 0 °C -100 °C temperature range, our design exhibits a compact footprint of about 0.02 mm 2 and a supply voltage operating range from 0.6 V to 1.8 V.Moreover, it consumes less than 1.6 µW (V DD =0.6 V and T emp=25 °C), with an energy per conversion of 1.05 nJ.The above results were achieved with an inaccuracy constrained within ±1.4 °C, and a resolution of 0.24 °C.
The remainder of the paper is organized as follows.Section II details the temperature sensor design.Section III presents measurement results over 20 test samples.Section IV compares our proposal with some recent CMOS-based competitors proposed in the literature.Finally, Section V concludes the work.

II. PROPOSED TEMPERATURE SENSOR
Inherited from the temperature-to-digital conversion methodology exploited in [13], [14], the sensor relies on three main processing blocks, as shown in Fig. 1. 1) The temperature-to-current converter (TCC) represents the sensing element of the proposed circuit.It generates two sub-threshold currents, I H and I L (with I H > I L ), whose ratio I H /I L has an increasing linear dependence with the temperature.
2) The current-to-frequency converter (CFC) consists of two independent ring oscillators controlled by mirrored I H and I L currents.The ratio of the two oscillation frequencies (i.e., f H /f L ) is maintained linear with temperature.3) Finally, the frequency-to-digital converter (FDC) generates the digital temperature code, based on the f H /f L ratio.
The voltage scalability of the sensor derives from two stacked native (i.e., zero threshold voltage transistors) NMOS devices [12], which provide line regulation for the supplysensitive TCC and CFC blocks.Indeed, these are powered in the sub-threshold region by an almost stable virtual V DD (V V DD ), regardless of the actual V DD and temperature.In our 180 nm implementation, the V V DD is about 440 mV across very large temperature (0 °C-100 °C) and power supply (0.6 V-1.8 V) variations.Differently, the FDC circuit, being based on not-critical digital circuitry (i.e., intrinsically more robust to temperature and voltage variations) is powered directly by the V DD .

A. Temperature-to-Current Converter
The proportional-to-absolute-temperature (PTAT) behavior of the current ratio I H /I L is obtained thanks to the lowcomplexity circuit shown in the inset of Fig. 2. Such circuit is organized in two branches, including only five diodeconnected PMOS devices.The left (right) branch is implemented with 3 (2) identically sized transistors, so that the V V DD is equally partitioned between them resulting in ).Since all the devices of the TCC operate in the sub-threshold region, with a source-to-drain voltage, V SD , larger than four thermal voltages V T = k B T /q (k B is the Boltzmann constant, T is the absolute temperature, and q is the electron charge), their source current I S can be expressed as [23]: where W/L is the aspect ratio of the device, I 0 is the technology dependent subthreshold current which can be obtained by extrapolating the current for V GS = V th , V th is the threshold voltage and n is the subthreshold factor.Thus, the current ratio I H /I L can be written as: where we have assumed that I 0 and V th for transistors M1 and M2 are the same.
Based on the value assumed by the term −qV V DD /6nk B , the exponential can be well approximated by a linear relation in a bounded temperature range (e.g.0 °C-100 °C), according to: with m = 16.1 1/ °C, p = 2.55 for our design, and T emp expressed in °C.The obtained model equation ( 2) is plotted in Fig. 2, where it can be appreciated the good agreement with simulation results.

B. Current-to-Frequency Converter
As shown in Fig. 3(a), the CFC exploits two current-starved ring oscillators to convert the mirrored version of the I H and I L currents into two digital pulse signals, whose frequency ratio f H /f L maintains a linear PTAT trend.
In general, the oscillation period T osc of a current-biased ring oscillator can be expressed as [13]: where N is the number of stages in the ring oscillator, C L is the load capacitance of a single delay cell, ∆V is the output voltage amplitude, I bias is the biasing current, while t f all and t rise are the falling and the rising times of a single stage.Both t f all and t rise should be sufficiently small compared with (C L ∆V )/I bias so that the oscillation frequency can be approximated as proportional to I bias /(C L ∆V ).In this case, f H /f L (= T osc,L /T osc,H ) provides a similar PTAT characteristic as I H /I L .
In our design, both the ring oscillators use the same delay cell topology (see Fig. 3(a)), based on a standard CMOS inverter loaded by a NMOS capacitor.The latter limits the oscillation frequency, while avoiding excessive increasing in the number of delay cells.As an additional benefit, the added capacitance at the output node of each inverter helps in increasing the linearity of the oscillation frequency with the biasing current (as from ( 4)).The two ring oscillators have been designed with a proper number of stages (13 and 7 for the slow and the fast oscillators, respectively) and delay stage sizing.As shown in Fig. 3(a), decoupling MIM capacitors (400 fF) were introduced at the supply voltage nodes of the two oscillators to reduce the impact of the switching noise on the oscillation frequency.
Simulation results of the FDC circuit driven by the TCC are shown in Fig. 3(b-c).From Fig. 3(b), as temperature increases from 0 °C to 100 °C, f L (f H ) spans from 17 kHz (4.3 MHz) to 31.8 kHz (9.6 MHz).As shown in Fig. 3(c), the adjusted-R 2 of 0.99995, evaluated on the f H /f L ratio, leads to a tolerable error after a two-point calibration, with 10 °C and 90 °C as temperature references.

C. Voltage Regulation
A low-complexity voltage regulation mechanism has been implemented to improve line and temperature sensitivities of TCC and CFC blocks.This has been achieved by interposing two series-connected native NMOS devices between V DD and the TCC+CFC circuits, as depicted in Fig. 1.In this way, the source of the lower native transistor corresponds to the virtual supply voltage V V DD seen by the TCC and CFC blocks.Note that, the stack of two native transistors will always be operated in sub-threshold, given that both have V G = V th = 0V and V S > 0V .The use of two long channel transistors in series to implement the voltage regulator block, makes its I(V, T ) characteristic essentially insensitive to variations of the external V DD .Moreover, such approach also leads to an almost stable V V DD with temperature variations.In order to better explain this, we rely on the scheme reported in Fig. 4, where the regulator (REG) and the TCC and CFC circuits (LOAD) are modeled independently.For the regulator, an I(V, T ) characteristic in the following form is assumed: in which the DIBL effect is neglected (i.e., the V DS impact on I D ).Such a kind of regulator is capable to provide an almost constant V V DD to a load a circuit whose I(V, T ) relation can be expressed in the following form: which is reasonable for CMOS circuits operated in subthreshold regime, such as the TCC and CFC blocks in our design.
In Fig. 5(a), the DC V-I curves for regulator and load, simulated at different temperatures, are depicted.The analytical expression of these curves can be easily obtained by writing ( 5) and ( 6) in their respective logarithmic forms.The crossing points between the two curve families represent the load conditions for different temperatures.From this plot, it can be easily understood how the V V DD is essentially stable as temperature changes, despite the supply current exponentially increases with temperature.Analytically, by manipulating ( 5) and ( 6), one can put the V V DD in the following form:

REG
with in which all the terms β eq , k B T q , α R and α L are individually a function of the temperature.In fact, we have verified that the α R α L ratio is essentially constant, while the β eq term has an almost 1/T dependence which compensates the linear term in k B T q .The aforementioned fitting parameters have been extracted for the regulator and load circuits at the different temperatures, and the corresponding analytical expression for V V DD and the supply current are reported in Fig. 5(b): when the temperature raises from 0 °C to 100 °C, although an about 7 times current increase is observed, the corresponding change in the voltage is of about 3%.The extracted model equations are consistent with the sensor front-end simulations reported in Fig. 6, which shows the behavior of V V DD voltage node and current drawn by the front-end (stacked native NMOS devices biasing TCC and CFC) sensor circuitry as a function of temperature for V DD ranging from 0.6 V to 1.8 V with a step of 100 mV.It can be easily observed that while the average current increases from about 0.6 µA @ T= 0 °C to 4.1 µA @ T= 100 °C (i.e., drawn current increases more than 6.9 times as temperature passes from 0 °C to 100 °C), the V V DD increases of less than 5% in the same temperature range.At the same time, V V DD stays quite constant for V DD spreading from 0.6 V to 1.8 V, as a consequence of long channel stacked NMOS devices used to screen the V DS dependence.From the above considerations, are then evident the benefits of the adopted low-complexity voltage regulation to improve both line and temperature sensitivities.
In deeply scaled process nodes (i.e.below 40-nm), native MOSFETs could not be available.In this case, the described voltage regulation can be realized by properly sized nMOS devices with regular V th (RVT), as long as they are biased with a stable gate voltage close to the V th , so that the V S > 0 leads them to operate in the sub-threshold regime.

D. Frequency-to-Digital Converter
The principle scheme of the digital back-end, responsible for generating the digital PTAT code, is shown in Fig. 7. Since the amplitude of the signals produced by the two ring oscillators in the CFC is constrained by the V V DD voltage level, both OSC H,L signals are up-converted to the V DD voltage domain by the compact and energy-efficient level shifter (LS) proposed in [24].Such circuit exhibits a very large voltage conversion range, and it is adaptive to change in V DD voltage level [24], rendering the whole temperature sensor fully compatible with DVFS systems.Frequency to digital conversion is then performed by two asynchronous counters.The Counter L acts as reference counter to set the time window of the temperature measurement sampling.This 5-bit counter defines a sampling time window of 16/F L seconds, since only 4 bits are used for counting while the MSB is exploited for triggering purpose.On the other side the resolution of the temperature sensor depends on Counter H, which was sized for 13-bit to prevent counting overflow over the temperature detection range from 0 °C to 100 °C, also considering some margin against undesired offsets due to process/mismatch variations.The timing diagram of the FDC block is shown in Fig. 8.When the START signal is triggered (note that, the START and the OSC L signals are synchronized), both counters begin counting upward until the transition to '1' of the DONE signal (i.e., the MSB of the reference counter), which happens after sixteen cycles of the slower oscillator.At this time, a temperature code is available at the output of the Counter H.Both the counters are reset by the START signal when a new temperature measurement is required.
In a general system, the FDC circuit can be shared between multiple sensor front-ends as shown in the sketch in Fig. 7.In this case, the back-end comprises two n-to-1 multiplexers, which take n output pairs from different sensor front-ends (i.e. each pair consists of the two signals at f H and f L frequencies) and pass the selected pair to the shared FDC.This allows to save precious silicon area when multiple thermal information is required for an effective DTM.
Fig. 9 reports simulated inaccuracy for the output temperature code in the target temperature detection range while considering different process corners and two-point calibration with 10 °C and 90 °C as temperature references.An absolute inaccuracy of -1.14 °C / 1.16 °C is observed at 50 °C for the FS/SF corners.Such result suggests a low susceptibility of the proposed design against process variability.

III. EXPERIMENTAL RESULTS
The fully-integrated temperature sensor was fabricated in a 180 nm CMOS technology node, while occupying a very small silicon area (less than 0.021 mm 2 ).The physical design is shown in Fig. 10(a), whereas a micrograph of the test chip is reported in Fig. 10(b).A silicon area of 14650 µm 2 is occupied by the voltage-regulated sensor front-end, while the FDC requires about 6300 2 .
Twenty test chips were measured in the target temperature range considering two-point calibration, with 10 °C and 90 °C as temperature references.Obtained results are summarized in Fig. 11.More precisely, Fig. 11(a) reports the temperature code of measured chips calibrated for V DD =600 mV.A very good linearity was found for all the samples with an average adjusted-R 2 of 0.9997, which is only slightly degraded with respect to that observed from the simulation results (see Fig. 3(c)).However, from Fig. 11(a), a noticeable difference can be appreciated in the slope coefficient from sample to sample.This prevents a simple 1-point calibration to be exploited when significantly high accuracy in the measurement must be guaranteed.The inaccuracy of the measurements as a function of the temperature is shown in Fig. 11(b).For all the measured samples, the inaccuracy is always maintained within the -1.45 °C/1.4 °C range.Also looking to the pessimistic 3σ data (about ± 2.5 °C), such measurement results are well within the acceptable accuracy specs for an effective DTM in stateof-the-art SoC [8], [21].Additional measurements performed on a single sensor are reported in Fig. 11(c-d).Here, the effect of voltage scaling was evaluated by considering a sweep on the V V DD from 0.6 V to 1.8 V with 100 mV step.Note that, for each supply voltage, an independent two-point calibration was considered.From Fig. 11(c), it can be observed that the digital temperature code differs significantly only at the highest temperatures, whereas, as shown in Fig. 11(d), the inaccuracy spans from -1.35 °C @ V DD = 1.5 V to 1.27 °C @ V DD = 0.8 V.The 3σ inaccuracy is within the ± 2 °C range.
Die-to-die variability in the target temperature detection range is fully evaluated in Fig. 12(a-c), by considering all test samples and 4 different supply voltage values (i.e., V DD =0.6 V, 1 V, 1.4 V and 1.8 V).From Fig. 12(a), the peak inaccuracy is within a range of 1.1 °C − 1.45 °C, with a median value close to 1.3 °C.This corresponds to a RMS inaccuracy in the range from 0.42 °C to 0.89 °C, as shown in Fig. 12(b).Whereas the achieved resolution (i.e., the inverse slope of the sensor output characteristics) shows very competitive values with a worst case of 0.22 °C for V DD = 1.8 V, as reported in Fig. 12(c).The measured average resolution is 0.132 °C, 0.131 °C, 0.138 °C and 0.139 °C for V DD equal to 0.6 V, 1 V, 1.4 V and 1.8 V, respectively.Indeed, the sampled temperature code can change in each measurement due to thermal noise.To properly evaluate the sensor resolution, the temperature code was measured 200 times at the fixed temperature of 25 °C for a typical sample.Fig. 13 reports the result of this experiment.The standard deviation σ of the samples is 0.24 °C (i.e. the noise-limited resolution), which corresponds to 1.84 LSB.
Sensitivity to unwanted voltage variations for the typical sample is characterized in Fig. 14, which shows inaccuracy as a function of supply voltage.A line sensitivity of 8.21 °C/ V at a temperature of 30 °C was measured by calibrating the sensor only at 0.9 V and then extracting the inaccuracy when supply changes in the ±200 mV (i.e., ±22%) range.However, when supply voltage of the sensor is changed as an effect of DVFS adjustment, the line sensitivity can be further reduced down to 0.56 °C/ V at 30 °C.In fact, in this case, the two temperature calibration points for each possible V DD (i.e.within the chip operating V DD range) can be easily pre-stored to define the actual calibrated characteristic (see Fig. 11(d)).
Finally, Fig. 15 shows the power consumption of the proposed sensor as a function of V DD for temperature ranging from 0 °C to 100 °C.Power increases almost linearly with the V DD , spreading from 1.57 µW (V DD = 0.6 V) to 5.61 µW (V DD = 1.8 V) at 25 °C.On the other side, power also increases with the temperature, reaching a maximum value of about 9 µW (V DD = 1.8 V and T emp= 100 °C).

IV. COMPARISON
Table I summarizes measurement results of the temperature sensor as compared to alternative CMOS designs [8]- [11], [13]- [16], [19], [25], [26].Experimental results provided for our design come from measurements on 20 test chips, while that of most of the competitors are based on a smaller number of samples (except for [8] and [26]).The circuits reported in [8], [15], [16], [19] do not support operation with sub 1 V voltages, while sensors discussed in [9], [14]- [16] show poor voltage scalability.On the contrary, our sensor supports the larger supply voltage operating range from 0.6 V to 1.8 V, while exhibiting a supply sensitivity of about 8 °C/ V.In addition, it does not require any external reference signal unlike the circuits reported in [25] and [26], which use a reference clock [26] and a reference voltage [25], respectively.Moreover, the proposed design exhibits a relatively small footprint of just 0.021 mm 2 .Indeed, it turns out to be the less area-hungry design in 180 nm and the third in absolute terms.
After a two-point calibration (i.e., with 10 °C and 90 °C as temperature calibration references), our sensor has a relative and a peak inaccuracy of 2.85% and of about 1.4 °C, respectively (both well within the required specs for multi-core systems [8], [21]) in the 0 °C − 100 °C temperature range.Such results are achieved without the need for additional non linearity correction logic, while exhibiting a noise limited resolution of 0.24 °C and an energy per conversion of only 1.06 nJ.Above results lead to a competitive resolution figure-of-merit (R-FoM), defined as Energy/Conversion × Resolution 2 [27].This can be graphically appreciated in Fig. 16, which shows the R-FoM/area trade-off for the compared designs.Reported results put our sensor in a position, where none of the competitors perform better in both

V. CONCLUSIONS
In this paper, we propose a fully-integrated CMOS temperature sensor suitable for dense thermal monitoring in advanced SoC.Its low-complexity circuit topology allows

Fig. 2 .
Fig. 2. Simulated I H /I L current ratio as a function of the temperature.In the inset: the temperature-to-current converter (TCC) circuit.

Fig. 3 .
Fig. 3. (a) Current-to-frequency converter (CFC), (b) simulated f H and f L vs. temperature and (c) simulated f H /f L frequency ratio as a function of temperature in the 0 °C-100 °C range, V DD = 600 mV.

Fig. 4 .Fig. 5 .
Fig. 4. Regulator and loading circuits model equations for the temperature sensitivity characterization of the V V DD .

Fig. 6 .
Fig.6.Simulated Virtual V DD and temperature-to-current converter + current-to-frequency converter drawn current for supply voltage ranging from 0.6 V to 1.8 V.

Fig. 10 .
Fig. 10.(a) Layout of the designed temperature sensor and (b) micrograph of the test chip.

Fig. 11 .
Fig. 11.Measured (a) digital output and (b) corresponding inaccuracy as a function of the temperature for V DD = 0.6 V in 20 test chips.Measured (c) digital output and (d) inaccuracy for a typical sample as a function of the temperature over the 0.6 V-1.8 V supply voltage range.

Fig.Fig. 16 .
Fig. Measured power as a function of supply voltage for temperature spreading from 0 °C to 100 °C.

TABLE I COMPARISON
WITH THE STATE-OF-THE-ART