Graphene‐Based Microwave Circuits: A Review

Over the past two decades, research on 2D materials has received much interest. Graphene is the most promising candidate regarding high‐frequency applications thus far due to is high carrier mobility. Here, the research about the employment of graphene in micro‐ and millimeter‐wave circuits is reviewed. The review starts with the different methodologies to grow and transfer graphene, before discussing the way graphene‐based field‐effect‐transistors (GFETs) and diodes are built. A review on different approaches for realizing these devices is provided before discussing the employment of both GFETs and graphene diodes in different micro‐ and millimeter‐wave circuits, showing the possibilities but also the limitations of this 2D material for high‐frequency applications.

The ORCID identification number(s) for the author(s) of this article can be found under https://doi.org/10.1002/adma.202108473.

DOI: 10.1002/adma.202108473
applications such as radio frequency identification (RFID) and near field communications (NFC) but also for intelligent reflecting surfaces (IRS). In addition, 2D materials have been shown to be excellent for sensing applications such as bio-, chemical-, nano-electro-mechanical, or high-bandwidth optoelectronic sensors. [2][3][4] These properties could be utilized in flexible electronic systems and smart wearable devices for biomedical purposes, environmental monitoring, and general sensor fusion and, when combined with 2D-based wireless communications, for applications in the Internet of Things or even 6G. In this review, we focus on the high-frequency potential of graphene-based devices and circuits and refer to the widely available literature on 2D sensors.
Graphene is a promising candidate for electronic applications among the family of 2D materials due to its outstanding electrical and mechanical properties. The high charge-carrier mobility and saturation velocity, [1,5] together with the ability for large-scale integration on different substrates make graphene a prime candidate for RF, millimeter-, and sub-millimeter-wave circuit applications. One advantage of graphene as an emerging technology that makes it appealing for new high-frequency applications is its mechanical flexibility due to its 2D nature. Last but not least, graphene can be integrated on different substrates without substantially changing the device operation characteristics and can thus be an add-on to cost-effective technologies which do not provide comparable highfrequency performance on their own. Nevertheless, graphene also has some drawbacks when used as a channel material in field effect transistors. [6,7] These are mainly associated with the lack of an electronic bandgap as will be discussed in this review. Table 1 shows a comparison of the electrical properties between intrinsic CVD-grown graphene, [8] silicon (Si), gallium nitride (GaN), and gallium arsenide (GaAs) at room temperature. Here, the focus is on properties relevant for high performance devices, that is, effective charge-carrier mass (m*/m 0 ), electron (μ e ), and hole mobility (μ h ), peak velocity (v peak ), and energy bandgap (E G ). The graphene properties are clearly superior compared to the established semiconductor materials that are used widely to realise high-frequency devices, with substantially one exception, the lack of an energy bandgap.
Beyond graphene, the family of 2D materials is growing constantly. The main branches are summarized in the graph in Figure 1 and classified according to their stability in various environments and temperatures. Of these, graphene

Introduction
The performance increases in recent communications standards in combination with the revolutionary research in new materials result in new application spaces and opportunities in high-frequency electronics. Particularly, 2D materials have attracted great attention due to their flexibility and ability for integration alongside with different substrates and form factors. Graphene, in particular, exhibits a high charge-carrier mobility, [1] which makes it interesting for high-frequency has received most of the attention with respect to high-frequency devices and circuits. Table 2 compares the measured electrical properties of graphene versus other 2D materials. The comparison clearly shows that graphene has the highest potential to be employed in high-frequency applications due to its outstanding carrier mobility compared to all other 2D materials in the table. [12,13] Nevertheless, these reported numbers are all below the theoretical intrinsic limit. Better results are typically obtained from 2D materials that are peeled off natural crystals versus materials grown by conventional semiconductor growth methods. Hence, the influence of material growth and subsequent processing is discussed in the first part of this review. We present different methods of growing and transferring graphene, with a focus on the quality, reproducibility, and variability of the grown graphene, because these aspects are crucial for device modeling and variabilitytolerant circuit design. The second part of the review covers the current state-of-the-art of graphene-based devices in microwave circuits. We discuss the reported graphene-based devices and circuit components, and in particular their modeling approaches for circuit design. In the following, we present and describe the implementation of different microwave circuits employing graphene-based devices and evaluate their performance with respect to commercial technologies. Our perspective on the potential and feasibility of graphene for realizing high-frequency circuits and for enabling applications beyond what is possible with classic semiconductors concludes this review.

Growth and Transfer of Scalable Graphene
Commercial applications of graphene-based electronic devices and circuits rely on the availability of high-quality, large-scale, and single-layer graphene. Meanwhile, wafer-scale process technology for transfer (or transferless growth), dielectric encapsulation, and electrical contacts [16][17][18][19] play also a significant role.
State-of-the-art devices in laboratory environment frequently employ exfoliated single-layer graphene flakes. However, this material is not scalable for high throughput or large graphene areas, especially on wafer-scale. Exfoliated graphene flakes typically have a maximum area of 3 × 10 5 μm [20] and cannot be placed deterministically across a wafer, therefore preventing industrial, wafer-scale fabrication processes.
In this section, we will review scalable technology for graphene growth and transfer, which is crucial for the application in microwave circuits. Table 1. Comparison between intrinsic graphene and other semiconductors in terms of m*/m 0 , μ e , μ h , v peak , and E G . Si GaN GaAs Graphene [8] Figure 1. 2D materials family. [9][10][11] Reproduced with permission. [12] Copyright 2020, American Chemical Society.

Graphene Growth by CVD
Large-area chemical vapor deposition (CVD) of graphene has been steadily improved upon in the form of graphite layer growth, even before the discovery of the field-effect in singlelayer graphene. During a standard graphene growth process, a metallic substrate (typically Cu) is heated inside a deposition chamber in a hydrocarbon-containing atmosphere. The elevated temperature and surface chemistry of the substrate causes the hydrocarbon precursor to decompose. Carbon settles on the Cu surface at nucleation sites and grows into single-layer graphene flakes at various orientations. Individual graphene patches originating from different nucleation sites eventually meet and cover the entire surface of the Cu substrate with the formation of grain boundaries. [21] The resulting large-area graphene is, therefore, typically of polycrystalline nature with domains ranging up to several millimeters. [21][22][23][24] Graphene grain boundaries present defects which lower the overall charge-carrier mobility of the active channel in elec-tronic devices. [21,25] A significant amount of research has therefore been aimed at the enlargement of domain sizes, with the ultimate goal of CVD-grown, wafer-scale, single-crystal, singlelayer graphene. [26,27] This has been mainly accomplished by a reduction of nucleation sites through adjustments in the CVD process parameters, prepatterning of the Cu surface, or seeding with exfoliated graphene flakes. [21] Growth on other metals has also been demonstrated to obtain uniform and large-area coverage of graphene on the growth substrate. However, the solubility of C in many metals other than Cu is comparatively high. C dissolved in the metal is released during the cooling step and precipitates at the metal surface in a process called "segregation growth mechanism" (Figure 2a). Unlike the surface adsorption-based growth process on Cu, growth on metals like Ni, Fe, or Au is therefore more challenging in terms of layer control. [21,28] CVD-grown graphene has demonstrated charge-carrier mobility above 350 000 cm 2 V −1 s −1 , [8] but the size of such material is still limited. However, a great effort has been devoted into this research direction to further improve the quality of scalable material, which is crucial for circuits applications.

Graphene Growth on Nonmetallic Substrates
For graphene-based electronics it is often necessary to deposit graphene on an insulator. The transfer step from Cu or other metallic surfaces also introduces additional chemical dopants Adv. Mater. 2022, 34, 2108473 Table 2. Comparison between intrinsic graphene and other 2D materials in terms of: μ e , μ h , and E G . MoS 2 [14] WS 2 [14] BP [15] B 2 Se 2 [15] Graphene [8] Figure 2. a) Schematic of segregation graphene growth on other metals with high carbon solubility. Carbon dissolves in the metal and migrates toward the surface during cooling, forming a graphene layer. Reproduced with permission. [29] Copyright 2008, American Institute of Physics. b) Epitaxial growth of graphene on SiC. Reproduced with permission. [30] [31] Copyright 2015, The Authors, published by Springer Nature. e) Multi-step graphene growth on a sapphire substrate, involving the deposition of a sacrificial crystalline metal layer and growth of the graphene. The crystalline metal layer makes seamless coalescence of the individual graphene flakes from different nucleation sites possible. Reproduced with permission. [32] Copyright 2021, Wiley-VCH. and mechanical stress, which further degrade the electrical characteristics of graphene. [26,32,33] Therefore, growth on insulating substrates is intensely researched.

Growth on SiC Substrate
Large-scale graphene can be synthesized by epitaxial growth on SiC surfaces (Figure 2b). During the decomposition process, Si sublimates off the surface, leaving the remaining C atoms to rearrange themselves into a mono-atomic layer. While this growth mode results in graphene with good mobility, the strong adhesion between substrate and graphene limits this process for many applications. [26,34]

Growth on Hexagonal Boronitride Substrate
Hexagonal boronitride (hBN) is suitable as a growth substrate because of its minimal lattice mismatch to graphene and good insulating properties. [35] Graphene growth has been demonstrated on Cu foils covered in exfoliated hBN flakes ( Figure 2c,d), which (at a thickness of a few mono-atomic layers) shield the catalytic capacity of the underlying Cu surface only a little. [28,31] Nevertheless, graphene growth on hBN faces the challenge of high-quality, large-scale hBN growth instead.

Growth on Sapphire Substrate
Metal-free, direct graphene growth on sapphire (Figure 2e) still poses a challenge, with state-of-the-art processes only recently reaching graphene diameters of up to 6 with mobilities around 2000 cm 2 V −1 s −1 . [26] Compared to Cu, sapphire shows less of a catalytic effect and thus makes higher process temperatures nec-essary, which in turn increase the roughness of the sapphire surface, eventually lowering the graphene growth rate and quality. The ultimate goal of growing wafer-scale, single-crystal, and single-layer graphene has not been reached yet and although many other alternative growth approaches have been demonstrated with varying advantages and disadvantages, CVD growth of graphene on Cu remains as the most promising for large-area, scalable, and low-cost growth with enabled transfer on arbitrary substrates (e.g., dielectrics, flexible substrate) for device fabrication.

Graphene Transfer
The transfer processes of CVD graphene have been investigated widely in literature, [36][37][38] as the quality of this processing step plays a significant role in attaining the unique electrical properties in high-performance devices. Figure 3 shows the commonly used large-area graphene transfer methods, where the methods are divided into two main categories as polymerassisted and direct-transfer methods. The polymer-assisted transfer indicates that the graphene is transferred to a target substrate with a polymer-based carrier material or supporting layer, which will be removed by chemical or physical means afterward to complete the transfer process. On the other hand, the direct transfer takes advantage of the binding force of the pretreated target substrate with the graphene to achieve the transfer process without involving an additional support layer. In the following, transfer methods listed in Figure 3 are explained.

Polymer-Assisted Transfer
Polymer-assisted transfer relies on coating of the graphene surface with a polymer such as poly(methyl methacrylate) (PMMA) as a protective layer and also for providing easy handling during the transfer. After the polymer coating, the Cu is removed in Cu etchants solutions, which leaves a floating PMMA−graphene stack on the surface of the solution, this process refers to Cu-etching-based transfer. The PMMA−graphene stack is then carried to DI water to rinse the etching solution leading to a clean graphene surface.
For wet transfer, after this step, the stack is transferred onto a target substrate and gradually heated to remove the water molecules trapped between the graphene and the substrate and to provide a good adhesion. This method is commonly referred to in the literature because known as reliable method. However, water molecules trapped in between the graphene and the transfer substrate can influence the characteristics of graphene and graphene devices as water molecules will cause additional doping. [39,40] For dry transfer, PMMA−graphene stack floating on DI water is taken out and dried before the transfer and stamped on the preheated target substrate. This method is also referred as semi-dry transfer since the Cu is etched by wet chemistry before the transfer and eliminates the additional doping on graphene surface due to water molecules. However, adhesion between the graphene and transfer substrate is the limiting factor and the quality of transfer, in comparison with the wet transfer, is not as reliable. [36] Figure 4 summarizes the above discussion comparing the wet and dry transfer.
Bubble-mediated transfer (Electrochemical delamination) (Figure 5a) is a technique to attain etching-free transfer of graphene. CVD graphene with supporting layer is placed at the cathode of an electrolysis cell, then the bubbles (H 2 ) generated by water electrolysis provide the peeling force to delaminate the supported PMMA/graphene layer from Cu. Delaminated PMMA/Cu stack then moves to the surface of the electrolyte due to the hydrophobic nature of PMMA and graphene, which can be transferred to the target substrate eventually. This transfer method is known to be low cost and time efficient. However, water electrolysis and thus bubble formation can cause damage on the graphene surface, which limits the reliability and scalability of the method. [42]

Direct Transfer
Roll-to-Roll Lamination: The roll-to-roll lamination method ( Figure 5b) allows transferring of large-area graphene with low cost while enabling the reusability of the growth substrate. In this method, graphene on Cu passing through hot rollers is laminated on the target substrate and the Cu is mechanically peeled off (or chemically etched). The roll-to-roll transfer technique has the potential to realize the large-scale industrialization of graphene transfer. However, the transfer is performed on thermally active lamination  foils such as polyethylene (PE) or poly(vinyl chloride) (PVC) or onto an arbitrary substrate which is coated with thermal lamination glue. This limits the substrate choice and also the cleanliness of the graphene. Additionally, for thin-film fabrication processes, temperature requirements are generally not satisfied by the laminating substrates and thermal lamination glue. [43][44][45][46][47] Wafer Bonding: In a recent study by Quellmalz et al., [49] largearea integration and wafer scale transfer of 2D materials was demonstrated by a wafer bonding method (Figure 5c). In this method, the target substrate is spin-casted by an adhesive layer and the bonding of the graphene on Cu foil is provided by controlling the process temperature and pressure to enhance the bonding energy between the graphene and the substrate layer, where the growth substrate Cu is removed afterward to accomplish the transfer. This method satisfies all ICCC standards defined above, and also allows stacking several layers of 2D materials such as hBN or MoS 2 to form heterostructures in a scalable way. One drawback of this method is the permanently remaining adhesive layer on the substrate after the transfer, which interfaces with the transferred 2D material and may affect the electrical properties of the 2D material due to doping and can limit the maximum usable temperature for further fabrication steps. However, the authors successfully showed a uniform graphene transfer and fabricated top-gated graphene-based fieldeffect transistors (GFETs) with moderate mobility. This method promises scalable transfer compatible for a wide range of application areas, spanning over electronics, sensing, and photonics.

Graphene-Based Devices and Their Modeling
In order to use graphene devices in circuit design, the graphenebased devices have to be characterized and modeled. In this section the structure as well as the different modeling approaches of reported state-of-the-art graphene devices is discussed.

Common Graphene Transistors
GFETs are mainly developed either as bottom-gated and topgated configurations. Each arrangement has unique development procedures, either regarding the synthesis methods of   [42] Copyright 2011, American Chemical Society. b) Reproduced with permission. [48] Copyright 2010, Springer Nature. c) Reproduced under the terms of the CC-BY Creative Commons Attribution 4.0 International license (https://creativecommons.org/licenses/by/4.0). [49] Copyright 2021, The Authors, published by Springer Nature.
graphene, such as mechanically exfoliation and CVD growth, or regarding the fabrication processes such as photolithography and electron beam lithography.

Bottom-Gated Configuration
The first GFET in the literature was developed in 2004 with a global bottom-gate configuration. [1] Since then, the bottomgated structure is widely used to form GFETs mainly due to two reasons. As illustrated in Figure 6, the final arrangement of a bottom-gated GFET leaves the graphene channel at the top forming thus conveniently an interface between the transistor and the environment. The overall device structure lends itself thus to sense and detect biomarkers or light, since the interaction between the exposed graphene layer and the light/biomarker alters the electrical characteristics of the graphene as function of type and amount of target substance. The presence of the substance can thus be quantitatively evaluated through measuring the change in the transport characteristics of the channel. The second reason is that after the graphene has been transferred, the amount of processing steps before encapsulation is minimized, resulting in higher quality graphene and thus better performing devices.
Despite the promising potential of graphene for high-frequency electronics, it is difficult to achieve high transconductance (g m ) with the bottom-gated GFET topology due to the resulting small gate capacitance. Moreover, it is challenging to attain current saturation in GFETs, which absence leads to poor DC gain (A V ) and large channel conductance (g DS ). [52] As a consequence, extremely high control voltages are required to reach usable g m -values and the maximum frequency of oscillation (f max ), yet such large input voltages are not likely to be seen in ordinary electronic applications. In order to improve g m and facilitate the integration of bottom-gated GFETs in RF electronics, it is either needed to engineer the bandgap, leading to low carrier mobility (⩽0.05 m 2 V −1 s −1 ), [53] or to engineer the velocity saturation to improve f max , for example, up to 70 GHz, [54] or the saturation current (I sat ≈ 20 A cm −1 ). [55] As depicted in Figure 7d, a single-layer graphene (SLG)based bottom-gated GFET has been developed to prove the effect of a dielectric layer on g m and the transfer characteristics. [50] It is clear from Figure 7e [50] Copyright 2009, IOP Publishing. g) Transport characteristics of h-BN based GFET with optical image inset and h) small-signal transconductance. Reproduced with permission. [51] Copyright 2010, IEEE. performance have been achieved by using a thin (72 nm) high-k dielectric (Al 2 O 3 ). The usual V-shape transfer characteristics and significant improvement in the transconductance have been realized with much lower control voltages. Alternatively, h-BN has been used to improve the performance of GFETs further. A chip microscopy image of a bottom-gated GFET based on a h-BN gate dielectric is depicted in Figure 7g. As shown in Figure 7g,h, this approach boosted the carrier mobility to above 1 m 2 V −1 s −1 with an associated intrinsic g m above 400 sm mm −1 . In another study, the saturation velocity has been increased by exploiting h-BN. [56] Thus, one can conclude that the introduction of high-k materials offers superior performances compared to plain SiO 2 .

Top-Gated Configuration
The other configuration for graphene transistor is the top-gated structure, which also is the most commonly employed device configuration used in RF applications. [57][58][59] This topology is the best choice for processes providing a thin oxide layer. A thin oxide layer is essential to enable stronger control over the doped carriers in the channel. Thus, channel modulation can be achieved with relatively low gate control voltages. However, developing the oxide layer on top of the graphene while preserving the graphene lattice structure and mobility is laborious. The first developed top-gated GFET from SLG is depicted in Figure 8a, where the inferior carrier mobility due to scattering introduced by the top-gate oxide is evident, as also demonstrated in Figure 8b. [60] Moreover, the mobility can be significantly degraded because of the charged impurities confined in the graphene-insulator interface. [51] There are studies on how to overcome the mobility degradation via the development of an alternative insulator layer on top of the graphene. Although h-BN has a dielectric constant of ≈3. 4, it has been one of the most appealing materials used as an oxide layer due to its hexagonal lattice structure, which is compatible with the one of SLG. [51] It has been demonstrated that the high mobility of graphene is preserved even if the SLG is sandwiched between layers of h-BN. [62] In another study, HfO 2 has been employed as insulating layer in a top-gated GFET structure, as shown in Figure 8c. The current saturation of the resulting device has been investigated for various gate lengths with values down to 100 nm, as presented in Figure 8d. The transfer curves of the GFETs in Figure 8e clearly indicate a shift of the Dirac point to positive voltage values for decreasing gate lengths. As shorter graphene channels require larger drain voltages, it has become necessary to apply high gate voltages to achieve the lowest Dirac point. [63] Control over the position of the Dirac point is crucial to adjust the operation of the transistor. In order to facilitate such control over the Dirac point, bottom gates have been fabricated together with top gates in GFETs. [64,65] As a consequence of this improved control, the series resistance could be reduced via the electrostatic dope of graphene, providing superior RF performance compared to top-gated GFETs. Moreover, high carrier mobility [64] and improved cutoff frequency [65] have been   [60] Copyright 2007, IEEE. c) Schematic of GFET with HfO 2 gate dielectric, and d) output characteristics, showing the current saturation and transfer characteristics of transistor with various channel lengths. c,d) Reproduced with permission. [61] Copyright 2011, American Chemical Society. demonstrated using a dual-gated device configuration. Figure 9a illustrates such a fabricated dual-gated GFET and its corresponding schematic. Figure 9b clearly indicates the control of the Dirac point by the integration of the bottom gate into the transistor. Figure 9c is the chip microscopy image of a specially designed dual-gated GFET optimized for RF applications that reaches a cutoff frequency of 50 GHz , as shown in Figure 9d, which exceeds that of a Si MOSFET with the same gate length.
Alternative GFET topologies have also been studied resulting in some improvements. Since the top gate introduces a parasitic capacitance, the gate has been buried into the substrate, lowering the fringing capacitance to improve the RF performance by increasing the vertical separation between the gate metal and the source/drain contacts. [66] Since the oxide deposition on top of the graphene is no longer needed in the buriedgate configuration, carrier mobility degradation is prevented. [67] On the other hand, the carrier mobility profile of graphene transistors has been improved by suspended gate configurations. A high carrier mobility of 4.4 m 2 V −1 s −1 has been achieved with a suspended graphene topology, as it provides an optimal interface to overcome substrate-associated scattering. [68]

Performance Assessment Based on Graphene Transistor Modeling
It is highly desired to have a physics-based model before a new device or system is development in order to predict the behavior of the device. Models generally facilitate the capabilities to test the theoretical aspect and soundness of the process in question, before the actual realization of the process. Specifically, a model allows assessing the performance of the overall structure. Since the models reflect the intrinsic transistor behavior, additional extrinsic capacitances are added to complete the model for high-frequency applications.
Both analytical and numerical models have been developed to reflect the behavior of real graphene transistors. [69] Figure 10a shows a dual-gated GFET structure, alongside with its detailed transistor model. The quantum capacitance C q has been implemented to represent variations due to the channel charge density and charge impurities around the Dirac point. The model has proven to be accurate by comparison with experimental data, as shown in Figure 10b.
As discussed in the previous section, the superior performance of the buried-gated arrangement in comparison to its top-gated counterparts has been additionally confirmed by corresponding device model representations. [67] The cross-section schematic of a top-gated transistor with its resistance model is depicted in Figure 10c. The series resistance, R s , is generated due to the top-gated topology, which disappears in the buriedgated structure. Moreover, Figure 10d exhibits the improvements of the transfer characteristics of the GFET by significant reduction of the specific access resistance with the buried gate. Such models have been developed and implemented using commonly employed platforms for circuit design and simulations Adv. Mater. 2022, 34, 2108473 Figure 9. a) Chip microscopy image and schematic view of dual-gated GFET and b) total resistances with respect to top gate voltage at various bottom gate potentials. a,b) Reproduced with permission. [64] Copyright 2009, AIP Publishing. c) SEM image of double channel graphene transistor with schematic view and d) RF performance of GFET, showing the current gain and cutoff-frequency (f t ). c,d) Reproduced with permission. [65] Copyright 2010, IEEE.
such as MATLAB, VHDL-AMS, and Verilog. [70] An extension of the dual-gated transistor model, provided in Figure 5a, to top or bottom-gated topologies can simply be realized by either addition or removal of the respective equivalent lumped elements.

Common Graphene Diodes
Diodes are indispensable circuit elements for RF electronic devices and are typically used as nonlinear devices for RF signal detection, frequency multiplication, and frequency translation. Schottky diodes have been the main components in high-frequency applications for a span of time because of their excellent characteristics. However, their incompatibilities with thin-film technology have restricted their applications in emerging technologies such as flexible electronics. On the contrary, metalinsulator-metal (MIM) diodes, due to their compatibility with thin-film processes, have become popular devices. Moreover, MIM diodes provide low zero-bias resistance, which results in higher operating frequencies compared to Schottky diodes. However, MIM diodes exhibit inferior performance compared to semiconductor-based diodes in terms of asymmetry and nonlinearity. [71] Therefore, graphene diodes based on the MIM diodes structure have been introduced by replacing one metal electrode with graphene.
The 2D metal-insulator-graphene (MIG) diode topology, the operation principle of the device, and the extension of the diode concept to a 1D MIG diode are covered in the following section.

2D MIG Diode
A typical MIG diode configuration is given schematically in Figure 11a. The thin-film compatibility of the MIG diode and its low series resistance has enabled the exploitation of MIG diodes in RF applications due to the high carrier mobility of graphene. [72][73][74] Moreover, the low junction capacitance and the low-energy-barrier oxide layer increased the potential of MIG diodes to be used in millimeter-wave (mmWave), sub-mmWave and terahertz (THz) applications.
Although the idea of the MIM diode configuration is exploited, the MIG diode employs a distinct operation principle. The functionality of the MIG diode is dominated by the modulation of the barrier height at the insulator-graphene interface via an applied bias. [77] As shown in Figure 11c, in the reverse bias the barrier height for electrons to transfer from M1 to M2 in the MIM structure, and from M to G in the MIG decreases with increasing reverse voltage until it reaches the potential difference between the work function (φ M ) of M1 and the conduction band edge of the insulator. In forward bias, the barrier height for electrons to transfer from M2 to M1 in the   [69] Copyright 2013, IEEE. c) Top-gated graphene transistor structure including resistance model and d) transfer characteristics of experimental data and model, emphasizing the influence of series resistance. c,d) Reproduced with permission. [67] Copyright 2019, IOP Publishing.
MIM structure is reduced until it reaches the potential difference between the work function of M2 and the conduction band-edge of the insulator. This creates the necessary asymmetry between forward and reverse operation. In the case of the MIG diode, the barrier height for electrons to transfer from graphene, G, to metal, M, decreases with increasing forward bias, which explains the high on-current and higher asymmetry for MIG diodes compared to MIM diodes. Thus, this different charge transfer method, that is, the lowering of the barrier with the induced bias in the MIG diode, solves the required trade-off between current density and asymmetry in MIM diodes. Therefore, the MIG diode yields higher performance than the MIM diode concerning asymmetry and nonlinearity. Moreover, MIG diodes have also been developed on top of flexible substrates such as Kepton and polyimide, paving the way for wearable graphene-based RF electronics. [78]

1D MIG Diode
Although the diffusion junction capacitance in typically stacked MIM and MIG diodes is acceptable low, the intrinsic junction capacitance in such diodes is large due to the parallel plate capacitance resulting from the configuration. As such, the maximum operation frequencies are limited by this capacitance. Moreover, since the capacitance and series resistance are inversely proportional in terms of area, a scaling of the diode does not improve the frequency of operation. Therefore, the 1D MIG diode was devised by exploiting the carrier emission from the edges of graphene to reduce the series resistance and improve f max and f t . [76,79] The arrangement of the 1D MIG diode is given schematically in Figure 11b. As it can be inferred from Figure 11d, the junction capacitance is significantly reduced by scaling down the junction area to a product of the SLG atom thickness times the contact width. Furthermore, the 1D MIG diode exhibits not only similar DC response as the 2D MIG diode, but provides approximately two orders of magnitude higher on current, as a result of its low junction capacitance and access resistance.
Based on published results, 1D MIG diodes outperform 2D counterparts also in terms of RF performance. The 1D diode cutoff frequency is calculated theoretically as 2.4 THz from numerical and experimental data. [80] Recently power detection via rectennas based on 1D MIG diodes on a flexible substrate has been demonstrated with a measured maximum responsivity of 80 V/W at 167 GHz and a minimum noise equivalent Adv. Mater. 2022, 34, 2108473   Figure 11. a) Schematic view of 2D MIG diode, b) schematic cross-section of 1D MIG diode and chip microscopy image is shown in the inset, c) barrier height versus applied bias voltage for both MIM and MIG diodes with their structure as inset. a−c) Reproduced with permission. [75] Copyright 2018, IEEE. d) Extracted junction resistance and junction capacitance values, and I-V characteristics of typical 1D MIG diode. Reproduced with permission. [76] Copyright 2019, American Chemical Society. power (NEP) of 80 pW Hz −0.5 . [81] These results prove the feasibility of energy harvesting and terahertz power detection on flexible substrates for application in, for example, wearable electronic devices enabled by graphene electronics.

Graphene-Based Diode Modeling
As graphene is a nonlinear material, simulation of graphenebased devices is not straight forward. Therefore, equivalent circuit models need to be extracted in order to predict the performance of devices and circuits based on these devices. The sketch of the cross-section of a four-finger MIG diode is depicted in Figure 12a alongside with an optical microscopy image and the small-signal model parameters of the intrinsic diode as inset.
A literature review reveals the limited effort has been put in so far in modeling MIG diodes. The most realistic, detailed, and well-developed model has been reported in ref. [82]. The overall small-signal model including the extrinsic parasitics is given in Figure 12b. The diode has been modeled as a series combina-tion of a linear capacitance, C 1 , and a bias-dependent, nonlinear capacitance, C 2 . In addition, a DC bias-dependent nonlinear junction resistance which is composed of the series combination of the leakage resistances, R 1 and R 2 , and the graphene sheet resistance, R G , has been included. For the diode, the physical implementation ensures that the linear series capacitance, C 1 , is larger than the nonlinear capacitance, C 2 , so that C 2 dominates the equivalent capacitance. On-wafer S-parameter measurements have been carried out from 10 MHz-70 GHz for fabricated diodes with different bias voltages ranging from −2 to 2 V. The accuracy of this model over the wide frequency range can be seen in Figure 12c where simulation and measurement data are compared. Accordingly, less than 1 dB of mismatch in magnitude and better than 2° of phase mismatch for return and insertion loss have been achieved, as shown in the insets.  includes frequency mixers, frequency multipliers, power detectors, amplifiers, and oscillators. On the other hand, due to the poor gain provided by GFETs, only few receiver and transmitter systems have been reported. The limited f T and f max of GFETs restricts the frequency of operation in GFET-based amplifiers. While in the reported frequency conversion circuits the nonlinearities of GFETs have been utilized to be able to operate the devices beyond their f T and f max . Another issue which affects the employment of GFETs in complex circuits and systems is the low reproducibility of matched devices as well as the low yield especially for GFETs with mechanically exfoliated graphene. Accordingly, the circuits and systems to date comprise only a low number of active devices within a single circuit. Circuits reported in literature based on graphene diodes operate at higher frequency. Since CVD-based graphene diodes have good reproducibility some of the reported circuits employ a few active components.

Amplifiers
Despite the already established promising characteristics of graphene, the performance regarding the design of amplifiers is intrinsically dependent and limited by the behavior of GFETs. Recently, the microwave performance of these devices has been improved significantly. [83] Nonetheless, graphene amplifiers have a quite limited power gain due to the zero bandgap in graphene, which leads to low current saturation. Moreover, parasitic resistances also degrades the maximum frequency of oscillation because of the fabrication contamination and imperfections.
In ref. [84], the first high-frequency GFET amplifier with a common-source configuration was demonstrated. This GFET amplifier employed an embedded metal gate structure to obtain a clear drain current saturation and thus, achieves a voltage gain of ≈5 dB and a 3 dB bandwidth greater than 6 GHz. However, a high output impedance was required in this design.
The first GFET amplifier with a 2 dB power gain was shown in ref. [85], and was achieved by optimizing the gate dielectrics and doping in the graphene channel under a 50 Ω load impedance. In 2011, a GFET amplifier with a power gain of 10 dB at 1 GHz was demonstrated in ref. [86], where an external inductor was used as an input matching network. Furthermore, the noise figure, NF = 6.4 dB, could be measured because the circuit provided sufficient power gain. In ref. [87], also an amplifier with a single-section LC input matching network was reported with a power gain of 1.84 dB at 191 MHz.
In conjunction with the gain, linearity parameters, such as the 1 dB gain compression (P 1dB ) or the third-order intercept point (IP 3 ), are also important factors in amplifier design. The linearity of GFET transistors has been discussed in refs. [84,88].
In order to enhance the operation bandwidth, a distrusted configuration can be adapted in microwave circuit designs. By means of this topology a significant bandwidth can only be reached, at the expense of large circuit size and high power consumption. Most importantly, the characteristics of each transistor used to form the artificial transmission lines must be as similar as possible, which is still a challenge in less mature technologies. A four-stage distributed GFET amplifier has been designed in ref. [89] based on CVD-graphene devices. Although a power gain of 4 dB over a 3.5 GHz-bandwidth has been simulated, no power gain could be measured in the fabricated design.
In ref. [90], a 3.4 dB GFET-based amplifier at 14.3 GHz was reported, where integrated transmission lines were used as matching networks. An amplifier design with a power gain of 8.34 dB at 5.5 GHz from the same research group has been reported in 2021. [91] The general challenge of implementing GFET amplifiers is that the graphene process is still immature and has many manufacturing difficulties, which lead to poor yield and large variation in the parameters of the device. The negative-image equivalent circuit technique [92] has been applied for a GFET amplifier design in ref. [93] in order to estimate the device parameters without developing a detailed device model and to manage process variations from fabrication run to fabrication run.
Several GFET transistors have been measured and the data analyzed to find a representative performance and estimate the spread in gain and impedance. The results show good prospects for future microwave and millimeter-wave amplifiers based on graphene technology. A fully integrated microwave GFET amplifier, as shown in Figure 13a, has been designed, fabricated, and characterized to demonstrate this design procedure. Its microscopy image is shown in Figure 13b. The measured results are plotted in Figure 13c where the transistor variations can be observed. Measured peak power gain of 4.2 dB at 10.6 GHz are achieved. Table 3 summarizes the performances of recent GFET amplifiers.

Power Detectors and Rectifiers
Power detectors are one of the direct applications for exploring the high carrier mobility in graphene. They are crucial elements in wireless communication systems, and many applications such as: RFID, automatic gain control, and energy harvesting, require sensitive, low-voltage drop, and low capacitance power detectors.
Employing GFETs in common-source (CS) configuration as linear power detector devices has been reported in refs. [95][96][97]. The demonstrated GFET power detectors are leveraging the nonlinear channel resistance property above the extrinsic f T and f max limitations of the employed device.
The main challenges of employing GFETs in power detectors are: The 3 dB detection bandwidth of GFET detectors is given by 1/(2πC t R t ) where C t is the total gate capacitance which consists of the gate-to-source capacitance, C gs , and gate-to-drain capacitance, C gd . R t is here the total resistance formed by the gate resistance, R g , in series with the source resistance, R s . Consequently, one limitation of using GFETs as power detectors comes from the excess capacitance, C gs , which limits the 3-dB detection bandwidth of the power detector.
Poor tangential signal sensitivity (TSS) and responsivity for frequencies where the transistor acts as a passive element with low current responsivity.
Graphene diodes have been successfully used also as power detectors. [98][99][100][101] In refs. [98] and [99], linear power detectors have been reported based on a single-graphene diode. Moreover, a linear-in-dB power detector employing three metal-insulatorgraphene diodes and designed for the frequency range 40-70 GHz has also been reported. In order to obtain both good input matching over a large bandwidth and high detection sensitivity, a linear distributed detector employing three graphene-diodes in an artificial transmission-line has been reported in ref. [101].
The power detector provides state-of-the-art performance from very low frequencies up to 70 GHz. Table 4 shows a performance comparison between different reported graphene-based power detectors.
Wireless power transfer (WPT) is highly demanded recently because it is able to provide energy without wired charging of devices. One of the key components in WPT is a rectifier which is used to convert the received alternating current (AC) to direct current (DC). The power conversion efficiency (PCE) of a rectifier, defined as η = P DC /P AC , where P DC is the output DC power and P AC is the input AC power, is one of the critical circuit parameters. Besides PCE, input matching, that is, the reflection coefficient, is also important for an RF/microwave rectifier. The difference between a power detector and a rectifier is the capability of providing output power, that is, V DC I DC instead of only voltage in detectors. Most of graphene rectifiers currently however require a high impedance output load, so that up to now basically only DC output voltage capability has been experimentally demonstrated.
Ballistic-and diode-based graphene rectifiers are two major approaches to realise a nonlinear device. Graphene is a suitable material to obtain ballistic transport which can be used to obtain ballistic-based rectifiers. [102][103][104][105][106] For ballistic transport the Adv. Mater. 2022, 34,2108473   devices must be planar and the active region should be smaller than a carrier mean free path to be in the ballistic operation regime. The operation principle is different than a diode-based rectifier because a ballistic rectifier does not require a doped junction or barrier structure. In 2015 [103] has presented a graphene rectifier in a semiballistic regime on a SiO 2 substrate. It showed a mobility of 1810 cm 2 V −1 s −1 which is much lower than the theoretical limit in graphene . The reduction in mobility was explained as the result of the forming of puddles on the SiO 2 substrate. In ref. [104], graphene was transferred on h-BN as substrate instead of SiO 2 to design a rectifier in full ballistic transport regime. Due to the encapsulation in h-BN a mobility of ≈200 000 cm 2 V −1 s −1 at room temperature was achieved. This significant improvement in mobility enabled the use of such devices in applications such as imaging. [105] Alternatively, diode-based graphene rectifiers have been reported on either rigid [107] or flexible substrates, [108][109][110] which rely on the nonlinear behavior of the device. The highest operation frequency is restricted by the parasitic capacitance and parasitic resistance of the device. By reducing the series resistance of the diode, for example, by employing the 1D MIG diode, terahertz diode-based rectifiers [107,109] have been achieved. A SPICEcompatible large-signal graphene-diode model, as illustrated in Figure 14, has been proposed in ref. [111] to carry out the circuit design as well as its optimization. With the large-signal model techniques to improve efficiency, for example, through harmonic tuning, become possible. In addition, to improve the power conversion efficiency, care has to be taken also in the design of the input matching. [112] Fan et al. [110] demonstrated a fully integrated and well matching CVD graphene rectifier, as shown in Figure 15. A measured reflection coefficient of −17.5 dB and output voltage of 93 mV has been achieved, as plotted in Figure 16. Note that by using a finite output load of 2.8 kΩ instead of a very high impedance load, DC output power could be obtained. [110] Nevertheless, all reported graphene rectifiers up to date hardly provide sufficient P DC which restricts their application in WPT. However, as suggested in ref. [110], with good reproducibility of CVD-graphene MMIC process, a rectifier array could become feasible to harvest sufficient energy at least for low-energy applications such as medical implants. Besides these two major rectifications, an alternative approach is to employ geometric asymmetry, that is, from a layout perspective, to obtain a significant nonlinearity as presented in ref. [113] where the device has a trapezoidal layout.

Frequency Multipliers
In the pursuit of achieving higher working frequencies, frequency multipliers are gaining an ever-increasing relevance in all technologies. They relax the requirements for the implementation of oscillators that can then be designed at lower frequencies, ultimately reducing the complexity of the circuit. Frequency multipliers can be implemented either to multiply Adv. Mater. 2022, 34,2108473   the frequency of the local oscillator directly, or to replace a mixer in the upconversion of the already modulated signal. [114] As they are usually passive designs, they are typically followed or preceded by an amplifier stage. The working principle in general is based on the nonlinearity of an active device to generate harmonics at multiples of the input frequency. Then, the harmonic component of interest is filtered out. Traditionally, diodes were used for this purpose, and later on in integrated designs transistors have also been used. [115] The nonlinearity of conventional diodes and transistors is reflected in the exponential relation of their I-V characteristics, between the input and output of the diode and between I ds and V gs in FETs. Nevertheless, in emerging technologies such as graphene, circuit design needs to be planned hand in hand with the intrinsic characteristics of the material in order to take full advantage of its promising new properties. Graphene alone presents a high nonlinear behavior under the influence of an electromagnetic field. In ref. [116], a linear metallic coplanar waveguide (CPW) is deposited directly on a monolayer graphene flake. The system under test presents the expected linear I-V relation, however, when characterized under a signal input up to 10 GHz and a DC bias voltage, the presence of harmonics is verified up to at least 40 GHz. The same structure without graphene presents no harmonic generation, as expected. The power level of the harmonic components is strongly dependent on the applied DC voltage, which is explained by the authors as coming from the strong nonlinear electromagnetic dependency of the Dirac fermions in the material ( Table 5).
One year prior to this work, in 2009, the first frequency multiplier based on GFETs was reported in ref. [117]. The GFET presented a back gate and employed exfoliated graphene, the rest of the components were externally connected. In this case, the circuit takes advantage of the ambipolar behavior of GFET devices, that is, the conduction of both holes and electrons that entail a symmetrical I-V relation with respect to the Dirac point, as shown in the V-shaped function in Figure 17a. As the function is even, the second-order term dominates and most of the power is expected to be transferred to the first harmonic frequency at the output, instead to the fundamental. This effect makes of GFETs excellent candidates for frequency doubling, without requiring complex differential topologies or highly selective filters.
Later on, in 2010 an improvement on the GFET by employing a top gate instead of back gate, led to an increase of the frequency response from 10 kHz to 200 kHz for a frequency doubler. [119] That same year, a top-gate GFET grown by  Figure 16. a,b) Simulated and measured input reflection coefficient (a) and output DC voltage versus input power (b). a,b) Reproduced with permission. [110] Copyright 2021, IEEE.
CVD is used in a hybrid circuit and achieves frequency doubling in the gigahertz range. [120] In 2012, the first work that reports a frequency doubler beyond the transit frequency of the GFET was published. [121] This is possible since the nonlinearity comes from the variable channel resistance caused by the graphene. Thus, since no transconductance is required, these designs can work beyond the f T of the used device. That same year, the first frequency doubler based on a GFET on flexible substrate was reported in ref. [122]. Again, in 2012, a direct application of the nonlinearities of graphene was approached in ref. [123]. A gap is created in a microstrip line and covered by a few-layer graphene film in order to design a frequency tripler. This same year, the first frequency tripler based on GFETs was demonstrated in ref. [124]. Whereas a single FET biased at the minimum conducting point results advantageous in doubler designs, in order to favor a tripling behavior this work presents a design built from two GFETs connected in series. The superposition of the two V-shaped transfer characteristics of graphene changes the I-V relation of the system to a W-shaped one. The new characteristics enable a modulation with higher power delivered to the third harmonic. A similar working principle is achieved in the design based on a double-gate GFET, as reported in ref. [125]. This work presents a frequency quadrupler that benefits from the symmetry of the transfer function of the transistor in order to achieve up to 50% of the output power transferred to the harmonic of interest. Further study regarding the purity of the harmonic of interest was carried out in ref. [126]. This work studied in simulation a frequency doubler based on three ambipolar GFETs, where the transistors are connected in series and their gates are shorted. Research in this regard is also continued in ref. [127], where an M-shape R-V g relation employing a single GFET is achieved. Here, the transistor is used to implement a frequency tripler for the first time with only one device and a spectral purity of 80%.  [113] Geo. asymmetry n n n Figure 17. Ambipolar-GFET frequency multiplier. a) Transfer characteristics of ambipolar GFETs. b) GFET-based circuit for frequency multiplication. a,b) Reproduced with permission. [117] Copyright 2009, IEEE. c) Photograph of the first integrated GFET-based frequency doubler. Reproduced with permission. [118] Copyright 2014, IEEE.
All GFET-based works mentioned so far are hybrid circuits, that is, only the active device is on-wafer and further components are connected externally or the circuit fully relies on the intrinsic behavior of the active device. The first and so far only fully monolithic integrated frequency doubler based on GFETs was reported in ref. [118] in 2014, as besides the GFET it also includes an on-chip spiral inductor used to apply the drain DC bias voltage, as shown in Figure 17c. Hence, this circuit does without additional components.
Two additional fully integrated designs based on MIG diodes have been presented so far. The first one, in ref. [128], is a single-balanced design implemented on quartz. It consists of two graphene diodes with an integrated BALUN and power combiner, as shown in Figure 18a. The second design, in ref. [72], uses a nonlinear transmission-line (NLTL) always on quartz to provide frequency multiplication. The concept of the NLTL relies on implementing an artificial transmission line with a characteristic impedance of 50 Ω as in Figure  18b. The variable capacitances to ground in the artificial line lowpass topology are provided by the MIG diode. The circuit contains a total of four diodes, as shown in Figure 18c, and performs either as doubler or tripler. The harmonic behavior of a different graphene-based diode has been reported in ref. [108]. Without additional matching, the spectral characteristics of a reduced graphene oxide diode (r-GO) are demonstrated for the third harmonic.
The performance comparison of the different cited designs is summarized in Table 6. As it has been shown, frequency multipliers in graphene are and have been intensively studied. This is due to the beneficial properties of graphene in order to intrinsically suppress spurious harmonic frequency components with reduced circuit complexity. Nevertheless, all this systems require an external signal generator, which leads to the next section, the need of frequency sources.

Oscillators
Oscillators are fundamental blocks of electronic systems. Their range of application encompasses from clock generation in microprocessors to carrier synthesis in communication transceivers, each requiring different topologies and performance. In general terms, an oscillator consists of a self-sustaining mechanism that is capable to grow its own noise until eventually a periodic output is generated. There are two ways of interpreting this working principle, either as a negative-feedback Figure 18. MIG-diode-based integrated frequency multiplier designs. a) Photograph of the MIG-diode-based balanced frequency doubler. Reproduced with permission. [128] Copyright 2019, IEEE. b) NLTL circuit diagram based on diodes. c) Photograph of the NLTL frequency multiplier based on a total of four MIG diodes. b,c) Reproduced with permission. [72] Copyright 2021, IEEE.
amplifier or as a one-port negative-resistance system. [129] Deepening in the extensive oscillator theory is beyond the scope of this work, nevertheless, an overview of the foundations is covered and shown in Figure 19. In Figure 19a, a linear unity-gain negative-feedback system where is considered. When H(s = jw 0 ) becomes equal to −1 the gain goes to infinity, and allows the circuit to sustain an output at w 0 . This is known as the "Barkhausen criteria" for oscillation, so that The second interpretation is presented in Figure 19b. A resonant tank is stimulated by a current impulse and the circuit is lossy due to the resistance, R p , that forces a decay in the oscillation. However, if this is compensated by an equivalent negative resistance, R p , in parallel, so that R p ||(R p ) = ∞, the oscillation would be sustained indefinitely over time. This negative resistance behavior has to be provided by an active circuit. Therefore,  Figure 19. a,b) Working principle of the oscillator as a unity-gain negative-feedback system (a) and a negative-resistance oscillator (b), together with the first integrated RO based on GFETs, with a total of three inverter stages and eight transistors. c) Three-stage GFET-based RO diagram. d) Optical microscopy image of the integrated RO. a−d) Reproduced with permission. [130] Copyright 2013, American Chemical Society.
the theory establishes that an oscillator system requires an active device or a combination of devices capable of providing positive gain, |A v |, that is, present a negative resistance over a particular frequency range.
Two main categories of oscillator circuits can be distinguished, ring oscillators (ROs) and LC-oscillators. Whereas ring oscillators are easier to integrate, LC oscillators require that the technology allows the implementation of resonant structures, that is, planar spiral inductors, plate or finger capacitors, and other complex high-Q components. Thus far, the only integrated reported designs for oscillators in graphene are ROs based on GFETs. Their best reported performance is compared in Table 7.
These three designs present a similar architecture that consists of an odd number of inverters, each with two GFETs, cascaded in a loop that provides the needed feedback. In addition, another inverter serves as buffer to isolate the oscillator from the loading by the measurement equipment, as shown in Figure 19c. The challenge of this topology when implemented with GFETs is to obtain transistors with sufficient positive voltage gain, and with repeatable performance over multiple devices. Ultimately, ROs represent the limit in performance for an IC technology, as the total inverter gate delay in ROs, τ, is used as the main speed metric of such technology. The sum of all single-stage delays, τ i , is the total delay, τ, and its inverse equals the maximum oscillation frequency, f o . In contrast to f T and f max , τ, which is mainly dependent on the on-state resistance, is valid in the large-signal regime and contemplates nonidealized and multiple-transistor conditions. Since the channel resistance and the gate capacitance scale with L, a theoretical f o ∝ L −2 relation is expected. Nevertheless, due to parasitic resistances and capacitances that do not follow the idealized dependency, both refs. [130] and [132] prove a f o ∝ L −1 dependency. However, ROs based on GFETs with lengths under 0.8 μm [133] have yet not been reported, as the achievable gain of those devices is not sufficient for sustaining an oscillation. [132] The only reported LC oscillator in graphene is an hybrid design working at 72 MHz. [122] The GFET is on-wafer, while the feedback is provided by external components and the circuit is tuned by a mechanical tuner. Interestingly, negative differential resistance (NDR) architectures based on a single and multiple GFETs have been reported. [134,135] Nevertheless, although they are promising for oscillators, among other circuits, these topologies have been only demonstrated as stand alone systems. Other graphene-based devices analogue to Gunn devices or tunnel diodes, which present negative resistance characteristics, are still lacking the literature. Therefore, progress in the development of oscillators is conditioned by intrinsic constraints of the GFET devices itself.

Mixers
The currently reported GFET mixers are realized as FET-resistive mixers which exploited the GFET nonlinear resistance rather than its transconductance. Additionally, the lack of current saturation in GFETs result in a high linearity of GFETbased resistive mixers. The passive nature of this approach enables the demonstration of mixers operating at frequencies above f T and f max of the used GFETs. However, the reported conversion loss (CL) of GFET-based mixers is relatively high compared to other technologies. This is caused by the dependence of the conversion efficiency of the FET-resistive mixers on the drain-to-source resistance, R ds which ideally changes from zero in the on-state to infinite in the off-state. In case of the GFET and because of its ambipolar behavior the on-off resistance-ratio is always low with high on-resistance and low offresistance. As a consequence, the reported CL values vary from 45 dB [136] to 18 dB [137] for a local oscillator power (LO) power (P LO ) of 8 dB m. This is the minimum reported CL so far for integrated GFET-based mixers. GFET-resistive mixers are implemented as either fundamental or subharmonic mixers employing mostly, a single-transistor due to yield and repeatability issues of the fabrication process. The used GFET is either connected to high-Q external passive components [136,[138][139][140][141] or integrated with passive lumped components or microwave filters. [137,[142][143][144] Graphene-diode-based mixers were reported in refs. [128,145]. In ref. [145], a single-diode-based downconversion mixer has been reported. The RF frequency range for this mixer is 1.7-4 GHz and the reported CL is 15 dB. In ref. [128], a double-balanced upconversion mixer was reported. The operation frequency is 6-12 GHz and the reported CL is 10 dB. The employment of graphene-diodes in mixer circuits resulted in lower conversion loss compared to GFET-based mixers due to the more favorable on-off resistance ratio of state-of-the-art graphene diodes. Table 8 summarizes the performance of the reported graphene-based mixer circuits.

Receivers
Based on the discussion in graphene-based devices section, the reported graphene-based receivers employing GFETs are providing a limited operating frequency range and low gain. In addition, the yield for exfoliated graphene is low and the reproducibility for multiple active devices is still low. In ref. [147], an integrated three-stages RF receiver frontend based on GFETs is reported that was designed to receive RF signals at 4.3 GHz with 10 dB of total system conversion loss. In ref. [148], a single GFET is used as an envelope detector to demodulate amplitude modulation (AM) signal at 2.4 GHz with 34 dB of conversion loss. Additionally, there are very simple receiver frontends with the purpose to demonstrate the ability to demodulate low data-rate, low-power AM, and amplitude shift keying (ASK) signals. [147,149] In ref. [149], four GFETs are used as power detectors combined with a passive six-port junction to form a direct conversion six-port receiver in the W-band. The photograph of the MMIC is shown in Figure 20. Using a suitable six-port architecture is one possible approach to perform down-conversion and demodulation of signal at frequencies which are higher than f T and f max of the used devices. Also graphene diodes have been successfully employed in a six-port receiver operating in the frequency range 2.1-2.7 GHz as reported in ref. [99]. Four graphene diodes were employed as power detectors. Whereas the six-port junction in ref. [149] is based on transmission lines, the implementation in ref. [99] uses lumped components to reduce the size of the junction at low frequencies.
Although all receivers based on graphene devices discussed so far provide conversion loss instead of gain, the concept of parametric downconversion proposed in ref. [128] by exploiting the intrinsic properties of the graphene quantum capacitance appears to be an approach to realize receivers with positive conversion gain. It has been demonstrated theoretically by using measurements-based graphene-diode models in simulations that positive conversion gain can be obtained because the concept relays on the symmetric nature of the CV characteristics of the quantum capacitance of graphene to convert the lower-sideband parametric downconversion to a subharmonic upper-sideband parametric downconversion. This unique feature of graphene is required to obtain conversion gain in a lower-sideband parametric down-conversion. Table 9 summarizes the performance of the reported graphene-based receivers.

Discussion and Conclusion
The semimetal graphene is a 2D material that has outstanding electrical and mechanical properties that promote its use in numerous applications, especially in the flexible electronics and high-frequency domains. In this review, we discussed and described the state-of-the-art in graphene growth and processing technology, research that started only in 2004. Accordingly, the technology is relatively immature compared to the well established semiconductor technologies like CMOS, SiGe, Figure 20. W-band GFET-based sixport receiver front-end. a) Conceptual diagram of the sixport receiver, b) optical microscopy image of the integrated receiver, and c) measurement results with 10MHz OOK signal at different f RF in the W-band. a−c) Reproduced with permission. [149] Copyright 2018, IEEE. and others. The quality, reproducibility, and variability of the graphene process technology has clear implications for the early adopters from the circuit design community, as fault-tolerant or adaptable design methodologies have to be employed.
We continued to provide an overview of the graphene-based devices in microwave circuit applications available in literature. GFETs were initially investigated for their high-frequency performance potential. However, based on intrinsic material physics, they have a distinct DC behavior that makes their use in conventional circuit architectures challenging. The challenges are mainly due to the lack of current saturation in the transistor output characteristics and the inability to switch the devices off. Graphene diodes, in contrast, can exploit the properties of graphene by providing acceptable switching characteristics from a circuit point of view that depend mainly on the quality of the used graphene material.
GFET-based circuits like oscillators are not able to operate from rail-to-rail and provide low intrinsic DC gain at the device level. In addition, the limited frequency figures-of-merit f T and f max in GFETs result in low oscillation frequencies and low output powers. We show examples of how these limitations in the oscillation frequency can be compensated by using graphene-diodes as frequency multipliers. The latter, however, are passive systems that present conversion losses, which represent a further challenge. Here, the employment of graphene in parametric circuits can provide a solution, in particular when making use of the unique C-V characteristics of the quantum capacitance of graphene.
Circuit concepts such as parametric circuits and six-port receivers with diodes have been introduced during the early semiconductor technologies, that is, before semiconductor transistors reached high maturity levels. It can be expected that graphene will have a similar evolution and that the technology will achieve manufacturing maturity. Therefore, improving and stabilizing the graphene transistor technology will make a breakthrough in the use of graphene for countless applications.
Boolean logic gates remain a challenge with GFETs due to the their high off-state currents. However, a large range of related 2D materials are semiconducting, like MoS 2 and other transition metal dichalcogenides. Highly performing transistors with 2D channels from these semiconductors have been demonstrated. When combined, one can imagine 2D materialbased systems where the frontend is designed with devices based on graphene, while the low-frequency base-band is provided by suitable semiconducting 2D materials with good switching performance.
Finally, further developments in graphene and 2D material process technology will continue to drive the full exploitation of their outstanding electrical properties and, therefore, their employment in more complex systems. It will require substantial efforts to develop these technologies at high technology readiness levels, as cost and complexity increase drastically once processes become industrial. The main building blocks toward high performance 2D (flexible) electronics are a) near-perfect growth, b) layer transfer, c) atomic layer etching, d) low ohmic electrical contacts, e) effective doping, and f) nonperformance limiting encapsulation. Once all of these process modules have reached high maturity, accurate and more complex models for graphene-and 2D material-based devices will become available, driving innovate high-performance circuits and systems beyond current silicon technology.