Yarza, Irune
Agirre, Irune
Mugarza, Imanol
PĂ©rez, Jon
2022-06-09
<p>Next generation dependable embedded systems are facing a dramatic increase of functionalities and software complexity, requiring heterogeneous high-performance embedded computing devices. The increased software and hardware complexity of such emerging systems, together with the novelty of the technology, poses serious concerns regarding system’s safety certification. Moreover, driven by the increased connectivity features, security has become a crucial aspect that shall be considered alongside safety. This article aims to define a safety and security collaborative analysis framework for the systematic analysis of heterogeneous high-performance embedded computing devices. In this direction, a safety and security collaborative analysis methodology is proposed, which is implemented following an incremental top-down strategy. Following this methodology, a generic safety-security model is built first, which is then tailored to a case study for the Zynq UltraScale+ Multi-Processor System-on-Chip (MPSoC) device.</p>
This is the author's version of the work. It is posted here for your personal use. Not for redistribution. The definitive Version of Record was published in Microprocessors and Microsystems, Volume 93, 2022, ISSN 0141-9331, https://doi.org/10.1016/j.micpro.2022.104572
https://doi.org/10.1016/j.micpro.2022.104572
oai:zenodo.org:6636395
eng
Zenodo
https://zenodo.org/communities/up2date
https://zenodo.org/communities/eu
info:eu-repo/semantics/openAccess
Creative Commons Attribution 4.0 International
https://creativecommons.org/licenses/by/4.0/legalcode
Microprocessors and Microsystems, 93(104572, ISSN 0141-9331,), (2022-06-09)
Safety
Security
High-performance
Dependable embedded systems
Multi-core architecture
Safety and security collaborative analysis framework for high-performance embedded computing devices
info:eu-repo/semantics/article