Safety and security collaborative analysis framework for high-performance embedded computing devices

Next generation dependable embedded systems are facing a dramatic increase of functionalities and software complexity, requiring heterogeneous high-performance embedded computing devices. The increased software and hardware complexity of such emerging systems, together with the novelty of the technology, poses serious concerns regarding system’s safety certification. Moreover, driven by the increased connectivity features, security has become a crucial aspect that shall be considered alongside safety. This article aims to define a safety and security collaborative analysis framework for the systematic analysis of heterogeneous high-performance embedded computing devices. In this direction, a safety and security collaborative analysis methodology is proposed, which is implemented following an incremental top-down strategy. Following this methodology, a generic safety-security model is built first, which is then tailored to a case study for the Zynq UltraScale+ Multi-Processor System-on-Chip (MPSoC) device.