PDL: A High-Level Hardware Design Language for Pipelined Processors

A Docker container which can be used to recreate the results from the PLDI '22 paper, PDL: A High-Level Hardware Design Language for Pipelined Processors.

This includes:

 - The source code of the PDL compiler and its test suite
 - A simulator for the baseline Chisel processor used in our evaluation
 - The PDL programs describing the RISC-V architectures described in our evaluation
 - A build system to generate the CPI results reported in the paper for the above architectures