Journal article Open Access

# Simulation of the Nanoscale Joint Surrounding Gate SOI MOSFET Characteristics

Nikolae V. Masalsky

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<dc:contributor>Blue Eyes Intelligence Engineering  and Sciences Publication(BEIESP)</dc:contributor>
<dc:creator>Nikolae V. Masalsky</dc:creator>
<dc:date>2020-10-30</dc:date>
<dc:description>In order to solve the current problem of increasing the efficiency of modern electronic circuits, the applicability of a nanoscale joint surrounding gate MOSFET with oval work area is discussed. The design and principle of its operation are considered. This concept involves of jointing the working areas of n-channel and p-channel MOSFETs. In fact, the JSMOSFET consists of two "glued" along the halves of MOSFETs: one - nchannel and the other - p-channel, but with one common gate. We analyze the applicability of the design of an oval-shaped protected area. In our case, the contact of two heterogeneously doped regions occurs in the plane passing through the small axis of the oval. The main channels are formed in zones associated with the large axis of the oval. This achieves the main goalincreasing the number of charge carriers. At the same time, the efficiency of short-channel effect suppression is maintained and a high current level of the transistor is provided in the strong inversion mode. By the developed TCAD model of a nanoscale joint surrounding gate MOSFET with an oval work area the electrophysical characteristics of several prototypes with different transverse dimensions were numerically calculated at a supply voltage of 0.5 V. From the simulation results, it follows that all prototypes are low-voltage devices that can function at voltages below 0.5 V in the gigahertz frequency range with a high gain. The proposed devices perform the function of inverting the input signal without distortion. From the comparison of modeling data, the scope scaling capabilities are determined. The obtained results create prerequisites for the development of the proposed transistor architecture, since electronic chips created on their basis will differ in low power supply voltage, high performance, and minimal occupied area, which meets modern requirements for transistors for analog and digital applications.</dc:description>
<dc:identifier>https://zenodo.org/record/5844292</dc:identifier>
<dc:identifier>10.35940/ijitee.K7831.1091220</dc:identifier>
<dc:identifier>oai:zenodo.org:5844292</dc:identifier>
<dc:language>eng</dc:language>
<dc:relation>issn:2278-3075</dc:relation>
<dc:rights>info:eu-repo/semantics/openAccess</dc:rights>
<dc:source>International Journal of Innovative Technology and Exploring Engineering (IJITEE) 9(12) 150-153</dc:source>
<dc:subject>nanoscale SOI MOSFET, surrounding gate, shortchannel effects, logic gate, low supply voltage</dc:subject>
<dc:subject>ISSN</dc:subject>
<dc:subject>Retrieval Number</dc:subject>
<dc:title>Simulation of the Nanoscale Joint Surrounding  Gate SOI MOSFET Characteristics</dc:title>
<dc:type>info:eu-repo/semantics/article</dc:type>
<dc:type>publication-article</dc:type>
</oai_dc:dc>

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