Journal article Open Access

# VLSI Implementation of Digital Filter using Novel RTSD Adder and Booth Multiplier

Debasis Behera; Asutosh Patnaik; Prabhat Kumar Barik; Girija Sankar Rath

### DataCite XML Export

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<identifier identifierType="URL">https://zenodo.org/record/5595580</identifier>
<creators>
<creator>
<creatorName>Debasis Behera</creatorName>
<affiliation>Assistant Professor, Dept. of Applied Electronics and  Instrumentation Engineering, C. V. Raman College of Engineering,  Bhubaneswar, India.</affiliation>
</creator>
<creator>
<creatorName>Asutosh Patnaik</creatorName>
<affiliation>Assistant Professor, Dept. of Applied Electronics and  Instrumentation Engineering, C. V. Raman College of Engineering,  Bhubaneswar, India.</affiliation>
</creator>
<creator>
<creatorName>Prabhat Kumar Barik</creatorName>
<affiliation>Assistant Professor, Dept. of Applied Electronics and  Instrumentation Engineering, C. V. Raman College of Engineering,  Bhubaneswar, India.</affiliation>
</creator>
<creator>
<creatorName>Girija Sankar Rath</creatorName>
<affiliation>Professor, NIT, Rourkela, Odisha, India.</affiliation>
</creator>
</creators>
<titles>
<title>VLSI Implementation of Digital Filter using  Novel RTSD Adder and Booth Multiplier</title>
</titles>
<publisher>Zenodo</publisher>
<publicationYear>2020</publicationYear>
<subjects>
<subject>Finite Impulse Response (FIR) filters, Redundant Ternary Signed-Digit (RTSD) adder, Booth Multiplier, low power and delay.</subject>
<subject subjectScheme="issn">2249-8958</subject>
</subjects>
<contributors>
<contributorName>Blue Eyes Intelligence Engineering  &amp; Sciences Publication (BEIESP)</contributorName>
<affiliation>Publisher</affiliation>
</contributor>
</contributors>
<dates>
<date dateType="Issued">2020-02-29</date>
</dates>
<language>en</language>
<resourceType resourceTypeGeneral="JournalArticle"/>
<alternateIdentifiers>
<alternateIdentifier alternateIdentifierType="url">https://zenodo.org/record/5595580</alternateIdentifier>
</alternateIdentifiers>
<relatedIdentifiers>
<relatedIdentifier relatedIdentifierType="ISSN" relationType="IsCitedBy" resourceTypeGeneral="JournalArticle">2249-8958</relatedIdentifier>
<relatedIdentifier relatedIdentifierType="DOI" relationType="IsIdenticalTo">10.35940/ijeat.C6562.029320</relatedIdentifier>
</relatedIdentifiers>
<rightsList>
<rights rightsURI="info:eu-repo/semantics/openAccess">Open Access</rights>
</rightsList>
<descriptions>
<description descriptionType="Abstract">&lt;p&gt;Finite Impulse Response (FIR) filters are most important element in signal processing and communication. Area and speed optimization are the essential necessities of FIR filter design. This work looks at the design of Finite Impulse Response (FIR) filters from an arithmetic perspective. Since the fundamental arithmetic operations in the convolution equations are addition and multiplication, they are the objectives of the design analysis. For multiplication, Booth encoding is utilized in order to lessen the quantity of partial products. Consequently, considering carry-propagation free addition strategies should improve the addition operation of the filter. The redundant ternary signed-digit (RTSD) number framework is utilized to speedup addition in the filter. The redundant ternary representation utilizes more bits than required to denote the single binary digit because of which most numbers have several representations. This special behavior of RTSD allows the addition along with the absence of typical carry propagation. Xilinx ISE design suite 14.5 is used for the design and validation of proposed method. From the implementation result, the proposed design of FIR filter is compared with other conventional techniques to show the better performance by means of power, area and delay.&lt;/p&gt;</description>
</descriptions>
</resource>

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