5594176
doi
10.35940/ijeat.C6203.029320
oai:zenodo.org:5594176
Blue Eyes Intelligence Engineering & Sciences Publication(BEIESP)
Publisher
Balasaraswathi. R
Undergraduate Student, Department of Electronics and Communication Engineering, National Engineering College, Tamil Nadu, India.
Harini kalyani. M,
Undergraduate Student, Department of Electronics and Communication Engineering, National Engineering College, Tamil Nadu, India.
Vivek Anand. I
Undergraduate Student, Department of Electronics and Communication Engineering, National Engineering College, Tamil Nadu, India.
Modeling and Execution of Floating Point Parallel Processing Operation for RISC Processor
Divya. D
Undergraduate Student, Department of Electronics and Communication Engineering, National Engineering College, Tamil Nadu, India.
issn:2249-8958
info:eu-repo/semantics/openAccess
Creative Commons Attribution 4.0 International
https://creativecommons.org/licenses/by/4.0/legalcode
Double precision , RISC, Floating –point ALU,Instruction decoder.
<p>The development of processors with sundry suggestions have been made regarding a exactitude definition of RISC, but the prosaic concept is that such a computer has a small set of simple and prosaic instructions, instead of an outsized set of intricate and specialized instructions. This project proposes the planning of a high speed 64 bit RISC processor. The miens of this processor consume less power and it contrives on high speed. The processor comprises of sections namely Instruction Fetch section, Instruction Decode section, and Execution section. The ALU within the execution section comprises a double-precision floating-point multiplier designed during a corollary architecture thus improving the speed and veracity of the execution. All the sections are designed using Verilog coding. Monotonous instruction format, cognate prosaic-purpose registers, and pellucid addressing modes were the other miens. RISC exemplified as Reduced Instruction Set Computer. For designing high-performance processors, RISC is considered to be the footing. The RISC processor has a diminished number of Instructions, fixed instruction length, more prosaic-purpose register which are catalogued into the register file, load-store architecture and facilitate addressing modes which make diacritic instruction execute faster and achieve a net gain in performance. Thus the cardinal intent of this paper is to consummate the veridicality by devouring less power, area and with merest delay and it would be done by reinstating the floating-point ALU with single precision section by floating- point double precision section. Video processing, telecommunications and image processing were the high end applications used by architecture.</p>
Zenodo
2020-02-29
info:eu-repo/semantics/article
5594175
1634996922.365338
759871
md5:9e1e4fbfc00e0234d05ecf65c7327c73
https://zenodo.org/records/5594176/files/C6203029320.pdf
public
2249-8958
Is cited by
issn
International Journal of Engineering and Advanced Technology (IJEAT)
9
3
3783-3789
2020-02-29