Journal article Open Access

# Heterogeneous Logic: a High Performance and Low Power Non-CMOS 4-1 Multiplexer

B. Jeevan; K. Sivani

### DataCite XML Export

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<identifier identifierType="URL">https://zenodo.org/record/5591786</identifier>
<creators>
<creator>
<creatorName>B. Jeevan</creatorName>
<affiliation>Department of EIE, KITS Warangal or Kakatiya University,  Warangal, India.</affiliation>
</creator>
<creator>
<creatorName>K. Sivani</creatorName>
<affiliation>Department of EIE, KITS Warangal or Kakatiya University,  Warangal, India.</affiliation>
</creator>
</creators>
<titles>
<title>Heterogeneous Logic: a High Performance  and Low Power Non-CMOS 4-1 Multiplexer</title>
</titles>
<publisher>Zenodo</publisher>
<publicationYear>2021</publicationYear>
<subjects>
<subject>Logic Styles, VLSI, Multiplexers, CMOS, Heterogeneous Logic.</subject>
<subject subjectScheme="issn">2249-8958</subject>
</subjects>
<contributors>
<contributorName>Blue Eyes Intelligence Engineering  &amp; Sciences Publication(BEIESP)</contributorName>
<affiliation>Publisher</affiliation>
</contributor>
</contributors>
<dates>
<date dateType="Issued">2021-10-22</date>
</dates>
<language>en</language>
<resourceType resourceTypeGeneral="JournalArticle"/>
<alternateIdentifiers>
<alternateIdentifier alternateIdentifierType="url">https://zenodo.org/record/5591786</alternateIdentifier>
</alternateIdentifiers>
<relatedIdentifiers>
<relatedIdentifier relatedIdentifierType="ISSN" relationType="IsCitedBy" resourceTypeGeneral="JournalArticle">2249-8958</relatedIdentifier>
<relatedIdentifier relatedIdentifierType="DOI" relationType="IsIdenticalTo">10.35940/ijeat.C6201.029320</relatedIdentifier>
</relatedIdentifiers>
<rightsList>
<rights rightsURI="info:eu-repo/semantics/openAccess">Open Access</rights>
</rightsList>
<descriptions>
<description descriptionType="Abstract">&lt;p&gt;A novel non-CMOS 4-1 multiplexer using heterogeneous logic style is presented in this brief. The heterogeneous logic design uses the combination of three basic logic styles such as Dual Value Logic (DVL), Transmission Gate Logic (TGL) and Simple Pass Transistor Logic (SPTL). The design uses only two stacking transistors in between the supply rails. Only 16 transistors are required for the actual logic function in the proposed state-of-the-art design. Number of transistors is reduced by distinctly choosing DVL and TGL in the first stage as per the input combination. Later stage of the multiplexer is constructed using SPTL. A required logic style is chosen at first and second stage in accordance with input bit combination to minimize the number of transistors, enhance the speed of logic transition and reduce the average power dissipation. The design and simulation analysis of proposed circuit is carried out at 22nm technology using Pyxis Schematic and Pyxis Simulator. Comparison of wide-ranging simulated results of proposed design, CMOS tree multiplexer and CMOS NOR multiplexer at various supply voltages and frequencies on same technology node manifests that the performance of proposed heterogeneous multiplexer is better in terms of speed and power dissipation. At minimum possible supply voltage of 0.8V and at moderate frequency of 1GHz, the proposed multiplexer achieves, reduced power dissipation of 17.3% and reduced in delay of 9.14%. The count of transistors including inverters is also less compared to CMOS tree type and CMOS NOR type multiplexers. However, robustness of mixed logic style designs is to be improved compared to CMOS designs.&lt;/p&gt;</description>
</descriptions>
</resource>

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