De-RISC: Launching RISC-V into space

An important challenge faced by mission-critical computers is the ability to scale the processing performance, while maintaining a high level of dependability in a harsh environment. The adoption of COTS multi-core processors, as in non-critical industries, poses difficulties both in terms of timing interference due to concurrent access to shared hardware resources, and reliability under thermal and radiation stress.
Specific dependability-related features are thus required for space computers. In this domain, the LEON processors [1] are a European success-story, adopting an open architecture, being available as open-source implementations to allow validation by a wide user base, and having fault-tolerant implementations available to support missions with high-reliability requirements. The recent RISC-V [2] open-source instruction set architecture is a great opportunity to push this concept further, with a renewed potential for growth and wide adoption.
The De-RISC project (Dependable Real-time Infrastructure for Safety-critical Computer) aims at providing the first complete processing platform for space, leveraging RISC-V cores and state-of-the-art hypervisor technology. The platform is composed of an FPGA-based SoC with high-performance NOEL-V cores [3], minimized interference channels and many space-grade peripherals. The SoC platform hosts both the XtratuM Next Generation (XNG) hypervisor [4] and LithOS guest operating system [5] for applications isolation and scheduling. In addition, the platform implements advanced monitoring techniques that help to ensure the real-time behaviour in a multicore context.
In order to validate the platform, in addition to basic benchmarks and tests, a realistic space use-case will be deployed, based on the LVCUGEN (Logiciel de Vol Charge Utile GENerique) framework [6], the CNES generic payload software based on Time & Space Partitioning. WIth the CCSDS123 hyperspectral image compression [7] as a high-throughput application and TM/TC communications as low-latency critical application, it covers a complete mixed-critical system.
The current status of the project is in line with the plans: the prototype platform is already functional and almost complete, with new features added in scheduled internal releases. The validation phase has started, and will proceed incrementally until the end of the project. The commercial release of the platform is expected for Q2 2022.

References:
[1] https://www.gaisler.com/index.php/products/processors/leon5
[2] https://riscv.org/
[3] https://www.gaisler.com/index.php/products/processors/noel-v
[4] https://fentiss.com/products/hypervisor/
[5] https://fentiss.com/products/lithos/
[6] Julien Galizzi, Jean-Jacques Metge, Paul Arberet, Eric Morand, Fabien Vigeant, et al.. LVCUGEN (TSP-based solution) and first porting feedback. Embedded Real Time Software and Systems (ERTS2012), Feb 2012, Toulouse, France.
[7] Lucana Santos Falcon, Roberto Camarero. Introduction to CCSDS compression standards and implementations offered by ESA, European Workshop on On-Board Data Processing (OBDP2019), Feb 2019, Noordwijk, Netherlands.