Journal article Open Access

CMOS Circuit Design for Classification of ST and VT Arrhythmia Based on Morphological Analysis using Neural Network Classifier

D. Hari Priya; D. Ravali


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    <subfield code="a">Sinus tachycardia, Ventricular tachycardia, arrhythmia classifier, Hamming Neural Network, WTA Networks</subfield>
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    <subfield code="u">M.Tech, Department of Electronics and Communication  Engineering, Anurag Group of Institutions, Hyderabad, India.</subfield>
    <subfield code="a">D. Ravali</subfield>
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    <subfield code="u">Associate Professor, Department of Electronics and  Communication Engineering, Anurag Group of Institutions, Hyderabad,  India</subfield>
    <subfield code="a">D. Hari Priya</subfield>
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    <subfield code="a">CMOS Circuit Design for Classification of ST and VT Arrhythmia Based on Morphological  Analysis using Neural Network Classifier</subfield>
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    <subfield code="a">&lt;p&gt;Ventricular tachycardia is a life threatening medical emergency. Discerning dangerous ventricular rhythms with safe Sinus tachycardia based on heart rate is very tough as they are having similar heart rate. Most of the existing research used time information for classification which may lead false alarm. Hence a CMOS circuit is proposed to classify ventricular-tachycardia based on morphological changes in QRS complex. The design includes sample and hold circuit for sampling QRS complex, mapping circuit for map the given input signal to unit length, hamming neural network and winner take all circuits for classification of ventricular tachycardia. This design is implemented using 180nm CMOS technology with the operating voltage and power consumption of 19.81&amp;micro;W.&lt;/p&gt;</subfield>
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