5546804
doi
10.35940/ijeat.E9313.069520
oai:zenodo.org:5546804
Blue Eyes Intelligence Engineering and Sciences Publication(BEIESP)
Publisher
A. Deepthi
VIGNAN INSTITUTE OF MANAGEMENT AND TECHNOLOGY FOR WOMEN, Ghatkesar, Hyderabad, India.
U. Kaveri
VIGNAN INSTITUTE OF MANAGEMENT AND TECHNOLOGY FOR WOMEN, Ghatkesar, Hyderabad, India.
N. Ravalika Sharma
VIGNAN INSTITUTE OF MANAGEMENT AND TECHNOLOGY FOR WOMEN, Ghatkesar, Hyderabad, India.
Assessment on the Adequacy of Current Supply Testing Methods in CMOS Operational Amplifier
J. Sunil Kumar
Assistant Professor, VIGNAN INSTITUTE OF MANAGEMENT AND TECHNOLOGY FOR WOMEN, Ghatkesar, Hyderabad, India.
issn:2249-8958
info:eu-repo/semantics/openAccess
Creative Commons Attribution 4.0 International
https://creativecommons.org/licenses/by/4.0/legalcode
Current testing; Fault infusion, operational amplifier.
<p>As the CMOS innovation is downsizing, spillage power has gotten one of the most basic structure worries for the chip fashioner. This paper proposes examination on the adequacy of current gracefully testing strategies in cmos operational amplifiers. In this work, a two phase operational amplifier is structured and faults are infused utilizing 250nm innovation. We will assess the viability of current checking systems in distinguishing Bridge and open deformities in CMOS operational amplifiers. We ought to assess the identification capacities by utilizing two current testing strategies. The principal strategy comprises the oversight of the transient flexible current (IDDT) and the subsequent procedure comprises the observing of quiet gracefully current (IDDQ).The most probable resistive and open defects are infused utilizing fault infusion extra transistors. Exhibitions of the CMOS operational amplifier are additionally assessed after each issue infusion. Spice stimulation ought to be done to compare about the proposed test systems and assess the best performing one. We ought to assess the recognition abilities by utilizing two current testing procedures. The primary system comprises the oversight of the transient gracefully current (IDDT) and the subsequent method comprises the checking of quiet flexibly current (IDDQ). The most probable resistive and open deformities are infused utilizing fault infusion extra transistors. Exhibitions of the CMOS operational amplifier are likewise assessed after each fault infusion. Flavor re-enactments ought to be done to look at the proposed test strategies and assess the best performing one.</p>
Zenodo
2020-06-30
info:eu-repo/semantics/article
5546803
1633355311.850559
1419990
md5:34bd192d4371a741b161041c883b8da6
https://zenodo.org/records/5546804/files/E9313069520.pdf
public
2249-8958
Is cited by
issn
International Journal of Engineering and Advanced Technology (IJEAT)
9
5
296-299
2020-06-30