Conference paper Open Access

Iterating Von Neumann’s Post-Processing under Hardware Constraints

Rozic, Vladimir; Yang, Bohan; Dehaene, Wim; Verbauwhede, Ingrid


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  <dc:creator>Rozic, Vladimir</dc:creator>
  <dc:creator>Yang, Bohan</dc:creator>
  <dc:creator>Dehaene, Wim</dc:creator>
  <dc:creator>Verbauwhede, Ingrid</dc:creator>
  <dc:date>2016-05-03</dc:date>
  <dc:description>In this paper we present a design methodology and hardware implementations of lightweight post-processing modules for debiasing random bit sequences. This work is based on the iterated Von Neumann procedure (IVN). We present a method to maximize the efficiency of IVN for applications with area and throughput constraints. The resulting hardware modules can be applied for post-processing raw numbers in random number generators.
 </dc:description>
  <dc:description>H2020 644052 / HECTOR</dc:description>
  <dc:identifier>https://zenodo.org/record/55456</dc:identifier>
  <dc:identifier>10.5281/zenodo.55456</dc:identifier>
  <dc:identifier>oai:zenodo.org:55456</dc:identifier>
  <dc:relation>info:eu-repo/grantAgreement/EC/H2020/644052/</dc:relation>
  <dc:relation>url:https://zenodo.org/communities/ecfunded</dc:relation>
  <dc:relation>url:https://zenodo.org/communities/hector</dc:relation>
  <dc:rights>info:eu-repo/semantics/openAccess</dc:rights>
  <dc:rights>https://creativecommons.org/licenses/by-nc-sa/4.0/legalcode</dc:rights>
  <dc:title>Iterating Von Neumann’s Post-Processing under Hardware Constraints</dc:title>
  <dc:type>info:eu-repo/semantics/conferencePaper</dc:type>
  <dc:type>publication-conferencepaper</dc:type>
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