Conference paper Open Access

Iterating Von Neumann’s Post-Processing under Hardware Constraints

Rozic, Vladimir; Yang, Bohan; Dehaene, Wim; Verbauwhede, Ingrid


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{
  "description": "<p>In this paper we present a design methodology and hardware implementations of lightweight post-processing modules for debiasing random bit sequences. This work is based on the iterated Von Neumann procedure (IVN). We present a method to maximize the efficiency of IVN for applications with area and throughput constraints. The resulting hardware modules can be applied for post-processing raw numbers in random number generators.<br>\n\u00a0</p>", 
  "license": "https://creativecommons.org/licenses/by-nc-sa/4.0/legalcode", 
  "creator": [
    {
      "affiliation": "KU Leuven", 
      "@type": "Person", 
      "name": "Rozic, Vladimir"
    }, 
    {
      "affiliation": "KU Leuven", 
      "@type": "Person", 
      "name": "Yang, Bohan"
    }, 
    {
      "affiliation": "KU Leuven", 
      "@type": "Person", 
      "name": "Dehaene, Wim"
    }, 
    {
      "affiliation": "KU Leuven", 
      "@type": "Person", 
      "name": "Verbauwhede, Ingrid"
    }
  ], 
  "headline": "Iterating Von Neumann\u2019s Post-Processing under Hardware Constraints", 
  "image": "https://zenodo.org/static/img/logos/zenodo-gradient-round.svg", 
  "datePublished": "2016-05-03", 
  "url": "https://zenodo.org/record/55456", 
  "@context": "https://schema.org/", 
  "identifier": "https://doi.org/10.5281/zenodo.55456", 
  "@id": "https://doi.org/10.5281/zenodo.55456", 
  "@type": "ScholarlyArticle", 
  "name": "Iterating Von Neumann\u2019s Post-Processing under Hardware Constraints"
}
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