Conference paper Open Access

Iterating Von Neumann’s Post-Processing under Hardware Constraints

Rozic, Vladimir; Yang, Bohan; Dehaene, Wim; Verbauwhede, Ingrid


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<?xml version='1.0' encoding='utf-8'?>
<resource xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xmlns="http://datacite.org/schema/kernel-4" xsi:schemaLocation="http://datacite.org/schema/kernel-4 http://schema.datacite.org/meta/kernel-4.1/metadata.xsd">
  <identifier identifierType="DOI">10.5281/zenodo.55456</identifier>
  <creators>
    <creator>
      <creatorName>Rozic, Vladimir</creatorName>
      <givenName>Vladimir</givenName>
      <familyName>Rozic</familyName>
      <affiliation>KU Leuven</affiliation>
    </creator>
    <creator>
      <creatorName>Yang, Bohan</creatorName>
      <givenName>Bohan</givenName>
      <familyName>Yang</familyName>
      <affiliation>KU Leuven</affiliation>
    </creator>
    <creator>
      <creatorName>Dehaene, Wim</creatorName>
      <givenName>Wim</givenName>
      <familyName>Dehaene</familyName>
      <affiliation>KU Leuven</affiliation>
    </creator>
    <creator>
      <creatorName>Verbauwhede, Ingrid</creatorName>
      <givenName>Ingrid</givenName>
      <familyName>Verbauwhede</familyName>
      <affiliation>KU Leuven</affiliation>
    </creator>
  </creators>
  <titles>
    <title>Iterating Von Neumann’s Post-Processing under Hardware Constraints</title>
  </titles>
  <publisher>Zenodo</publisher>
  <publicationYear>2016</publicationYear>
  <dates>
    <date dateType="Issued">2016-05-03</date>
  </dates>
  <resourceType resourceTypeGeneral="Text">Conference paper</resourceType>
  <alternateIdentifiers>
    <alternateIdentifier alternateIdentifierType="url">https://zenodo.org/record/55456</alternateIdentifier>
  </alternateIdentifiers>
  <relatedIdentifiers>
    <relatedIdentifier relatedIdentifierType="URL" relationType="IsPartOf">https://zenodo.org/communities/ecfunded</relatedIdentifier>
    <relatedIdentifier relatedIdentifierType="URL" relationType="IsPartOf">https://zenodo.org/communities/hector</relatedIdentifier>
  </relatedIdentifiers>
  <rightsList>
    <rights rightsURI="http://creativecommons.org/licenses/by-nc-sa/4.0/legalcode">Creative Commons Attribution Non Commercial Share Alike 4.0 International</rights>
    <rights rightsURI="info:eu-repo/semantics/openAccess">Open Access</rights>
  </rightsList>
  <descriptions>
    <description descriptionType="Abstract">&lt;p&gt;In this paper we present a design methodology and hardware implementations of lightweight post-processing modules for debiasing random bit sequences. This work is based on the iterated Von Neumann procedure (IVN). We present a method to maximize the efficiency of IVN for applications with area and throughput constraints. The resulting hardware modules can be applied for post-processing raw numbers in random number generators.&lt;br&gt;
 &lt;/p&gt;</description>
    <description descriptionType="Other">H2020 644052 / HECTOR</description>
  </descriptions>
  <fundingReferences>
    <fundingReference>
      <funderName>European Commission</funderName>
      <funderIdentifier funderIdentifierType="Crossref Funder ID">10.13039/501100000780</funderIdentifier>
      <awardNumber awardURI="info:eu-repo/grantAgreement/EC/H2020/644052/">644052</awardNumber>
      <awardTitle>HARDWARE ENABLED CRYPTO AND RANDOMNESS</awardTitle>
    </fundingReference>
  </fundingReferences>
</resource>
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