Conference paper Open Access

Iterating Von Neumann’s Post-Processing under Hardware Constraints

Rozic, Vladimir; Yang, Bohan; Dehaene, Wim; Verbauwhede, Ingrid


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{
  "publisher": "Zenodo", 
  "DOI": "10.5281/zenodo.55456", 
  "title": "Iterating Von Neumann\u2019s Post-Processing under Hardware Constraints", 
  "issued": {
    "date-parts": [
      [
        2016, 
        5, 
        3
      ]
    ]
  }, 
  "abstract": "<p>In this paper we present a design methodology and hardware implementations of lightweight post-processing modules for debiasing random bit sequences. This work is based on the iterated Von Neumann procedure (IVN). We present a method to maximize the efficiency of IVN for applications with area and throughput constraints. The resulting hardware modules can be applied for post-processing raw numbers in random number generators.<br>\n\u00a0</p>", 
  "author": [
    {
      "family": "Rozic, Vladimir"
    }, 
    {
      "family": "Yang, Bohan"
    }, 
    {
      "family": "Dehaene, Wim"
    }, 
    {
      "family": "Verbauwhede, Ingrid"
    }
  ], 
  "note": "H2020 644052 / HECTOR", 
  "type": "paper-conference", 
  "id": "55456"
}
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