Enhanced Reliability of Fully Differential Difference Amplifier Through On-chip Digital Calibration

This paper presents a novel on-chip digital method of calibration for a fully differential difference amplifier (FDDA), which is aimed at improved performance and reliability through enhanced robustness against variations of process parameters, voltage, temperature, and ageing drift. The proposed method was designed and verified within 130 nm CMOS technology design kit in Cadence environment. Calibration hardware is built-in with the calibrated FDDA, and the whole integrated system is able to operate with only 0.4 V power supply. The effectiveness of the proposed calibration method was examined mainly by evaluation of the FDDA input offset voltage using Monte Carlo, process corners and ageing analyses performed for the temperature range from -20° C to 85° C. The work established metrics for comparison of different calibration methods (i.e. digital calibration, chopper stabilization, analog calibration and autozero), which significantly differ in fundamentals of their operation. The proposed digital calibration outperforms its alternatives, while the precision of calibration, area and power consumption overhead are considered. The less advanced topology of digital calibration was previously implemented for variable-gain amplifier with considerable success (residual offset of the calibrated amplifier reaches fair levels of 13 μV to 167 μV). The concept proposed in this work utilizes advanced high precision calibration algorithm.


I. I n t r o d u c t io n
Integrated circuits (ICs) subject to a trend of constantly increasing density of integration of electronic components. Following the Moore's Law, the number of transistors packed on a single chip has grown from about 5 million to nearly 50 billion over the last 20 years [1]. Thanks to the enormous progress of fabrication processes of ICs, it is possible to implement smaller and smaller electronic components. Reduc ing the dimensions of these elements brings new possibilities for reducing the energy consumption of ICs. On the other 978-1-6654-3595-6/21/$31.00 ©2021 IEEE hand, the manufacturing process of integrated circuits is not ideal. During the production of every chip, the imperfection of process technology cause variations in parameters of sensitive analog ICs, which can significantly affect its overall func tionality and reliability. Pure digital circuits (without analog parts) are not significantly sensitive to parameter fluctuations caused by manufacturing technology due to their discrete nature. These circuits can work very reliably also with ultra low values of the supply voltage, since the tolerance of values of electrical voltage or current can be relatively large with respect to the defined value of the logic level.

II. M o t iv a t io n
On the contrary, analog and also mixed-signal ICs are extremely sensitive to fluctuations in their parameters due to their continuous nature. Therefore, analog designers are recently facing the challenge of robustness of IC design against these fluctuations. Without addressing this issue in the design phase, with continuous transistor size as well as the supply voltage scaling, analog ICs may loose their performance or/and reliability. An effective solution to this problem is to design a type of subcircuit, so-called calibration circuit that w ill be as resistant as possible to imperfections of the production process and will not affect the overall power consumption significantly.
In this work, the design of a calibration circuit, which can very effectively compensate the operational amplifier (OPAMP) input offset voltage, is presented. The bulk-driven fully differential difference amplifier for ultra-low voltage aplications -FDDA [2] is used as the calibrated device. In order to achieve the lowest possible sensitivity to the variations of manufacturing process and at the same time to achieve the lowest possible energy consumption, a digital calibration algo rithm is employed. It was designed as a complex system used as a calibration circuit for an FDDA. Section III presents the design of the calibration circuit and principle of its operation. Part I v brings results of circuit verification in the Cadence environment through Monte Carlo analysis, Corner analysis and Reliability analysis. Section V presents the conclusion of this work.
III. Op e r a t io n p r in c i p l e a n d im p l e m e n t a t i o n o f CALIBRATION CIRCUIT Calibration circuit consists of five blocks: a control circuit, two counters and two digital-to-analog converters (DAC). From higher level of abstraction view, it is divided into three main parts: the control block, the main calibration part and the correction part, as shown in block diagram in Fig. 1. The whole circuit works as voltage-current converter, since the input of the calibration circuit is represented by the FDDA differential output voltage and the output of the calibration circuit creates the pair of compensation currents for the FDDA.
The basic principle of calibration circuit operation is that before the FDDA is initiated into the proper operation (func tion mode), the variations in currents flowing through the input differential pair of the FDDA are compensated in two cycles. In the first cycle, the main calibration block is in action. It injects currents I c o m p + and I c o m p -with a greater step to the input differential pair of the FDDA. The result of this cycle is a lower absolute value of the difference between the DC voltages OUT + and OUT-. However, after this current compensation, the compensation of FDDA offset voltage is still not accurate enough. Therefore, in the second cycle, a correction calibration block injects compensation currents with a lower and more accurate step to the input differential pair of the FDDA. After its completion, the calibration circuit is switched off and the FDDA is ready for its use in application.
is redundantly set (for this time) to the value of logic 1 by delayed NXOR gate. Finally, when the main calibration cycle is finished, the Q output of D F F 2 is flipped to the value of logic 0 by rising edge of the signal from the inverter and grounded D input. Clock signal C L K m a I N controls the main part of calibration circuit and C L K a u x is static during this cycle.
Secondly, correction cycle starts at the moment when the main cycle is finished and comparator flips its output to logic 1. The rising edge of this change sets the Q output of D FF\ to the value of logic 0 by grounded D input. In this moment, clock signal C L K m a I N is gated and it remains in the state of logic 1. Again, the Q output of D F F 2 is set to the value of logic 1 by delayed NXOR gate and clock signal C L K a u x starts to control the correction part of the calibration circuit.
When the comparator flips its output to the value of logic 0 again, Q output of D F F 2 flips to the logic 0, the C L K a u x is also gated and the second, correction calibration cycle is finished. The overall process of calibration is completed in this way. Control block provides three main tasks: sensing the FDDA output differential voltage, evaluating the difference between these voltages and finally, generating the control clock signals C L K maIN and C L K a u x for the main and correction parts of the calibration system.    VOUT _ o f f s e t . One can observe the FDDA output voltage in the sequential calibration process. After the calibration cycle is finished, the FDDA is initiated for the proper operation (function mode). Its input is fed with differential harmonic signal with a peak-to-peak amplitude of 200 ¡iV . The output signal amplitude goes up to 290 m V . This reveal a voltage gain of 63 dB, which is in correspondence with FDDA's nominal design. The residual offset output voltage of the FDDA after calibration reaches 10 mV at highest, which represents the input offset voltage VI N _of f set approximately of 10 ¡iV . These results prove that the target of calibration was successfully met. Figure 5 displays results of reliability analysis of calibration process applied to the FDDA output voltage. For this purpose, RelXpert engine of Cadence environment was used. This analysis calculates a drift of IC parameters over 10 years of operation mainly due to ageing of material structures, and electrical stress (Hot carrier injection [5], and Bias temperature instability [6], [7]). One can easily observe shortening in duration of aged IC calibration cycle. This in turn, deteriorates resolution that the offset voltage is compensated with. There fore, the VI N _of f set is supposed to rise from 2.4 ¡iV to 10 ¡iV . When the calibrated FDDA is initiated to the proper function, the drift of VI N _of f set is obviously negligible according to differential output signals (see Figure 5).   V. Su m m a r y a n d Co n c l u s io n In this work, the design of the calibration circuit for the FDDA was realized in 130 nm CMOS technology. Its primary task is to suppress the effect of fluctuations of FDDA parameters caused by the variations in manufacturing process parameters, temperature and time-dependent drift over IC lifetime. To ensure the lowest possible power consumption and sensitivity of calibration hardware to imperfections of the manufacturing process, a digital algorithm has been imple mented. For efficient application of the calibration circuit to the ultra-low voltage FDDA, its outputs have been designed as bulk-driven current mirrors.
The presented results were acquired through process Cor ners analysis, Monte Carlo analysis and Reliability analysis. Based on obtained results, it can be stated that the digital calibration has high potential. Firstly, after the completion of both FDDA calibration cycles, it was observed that the differential harmonic signal with a peak-to-peak amplitude of 200 pV was amplified to a pure signal with an amplitude of 290 mV at 63 dB gain -the nominal value of FDDA gain. In this case, the output offset voltage was at most 10 m V, which means that the input offset voltage reached approximately 100 p V . Secondly, the calibration circuit is also highly resistant to ageing -after simulated 10 years of voltage stress and ageing, the FDDA was calibrated accurately, which proves the reliability of calibration circuit. Finally, the great benefit of this circuit lies not only in its reliability and accuracy but also in ability to work under ultra-low supply voltage: in the range of 0.4-0.6 V , and it occupies small die area on chip: 43.10-3 pm2, and exhibits low power consumption: 6 pW (p) and 1.2 pW (S).