Journal article Open Access

# An SRAM-Based Multibit In-Memory Matrix-Vector Multiplier With a Precision That Scales Linearly in Area, Time, and Power

Khaddam-Aljameh, Riduan; Francese, Pier-Andrea; Benini, Luca; Eleftheriou, Evangelos

### DataCite XML Export

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<identifier identifierType="URL">https://zenodo.org/record/5301067</identifier>
<creators>
<creator>
<givenName>Riduan</givenName>
<affiliation>IBM Zurich Research Laboratory</affiliation>
</creator>
<creator>
<creatorName>Francese, Pier-Andrea</creatorName>
<givenName>Pier-Andrea</givenName>
<familyName>Francese</familyName>
<affiliation>IBM Zurich Research Laboratory</affiliation>
</creator>
<creator>
<creatorName>Benini, Luca</creatorName>
<givenName>Luca</givenName>
<familyName>Benini</familyName>
<affiliation>ETH Zurich</affiliation>
</creator>
<creator>
<creatorName>Eleftheriou, Evangelos</creatorName>
<givenName>Evangelos</givenName>
<familyName>Eleftheriou</familyName>
<affiliation>IBM Zurich Research Laboratory</affiliation>
</creator>
</creators>
<titles>
<title>An SRAM-Based Multibit In-Memory Matrix-Vector Multiplier With a Precision That Scales Linearly in Area, Time, and Power</title>
</titles>
<publisher>Zenodo</publisher>
<publicationYear>2021</publicationYear>
<subjects>
<subject>in-memory computing, SRAM</subject>
</subjects>
<dates>
<date dateType="Issued">2021-08-28</date>
</dates>
<resourceType resourceTypeGeneral="JournalArticle"/>
<alternateIdentifiers>
<alternateIdentifier alternateIdentifierType="url">https://zenodo.org/record/5301067</alternateIdentifier>
</alternateIdentifiers>
<relatedIdentifiers>
<relatedIdentifier relatedIdentifierType="DOI" relationType="IsIdenticalTo">10.1109/TVLSI.2020.3037871</relatedIdentifier>
</relatedIdentifiers>
<rightsList>
<rights rightsURI="info:eu-repo/semantics/openAccess">Open Access</rights>
</rightsList>
<descriptions>
<description descriptionType="Abstract">&lt;p&gt;A novel interleaved switched-capacitor and SRAM-based multibit matrix-vector multiply-accumulate engine for in-memory computing is presented. Its operation principle is based on first converting an SRAM-stored n-bit weight into a proportional voltage using a pipeline D/A converter built from n+1 equally sized stages. A switched-capacitor stage then multiplies these voltages with an m-bit digital input activation. Finally, the output voltages that correspond to the different multiplication results are accumulated along one column by means of charge-sharing. With our proposed architecture, the required circuit area, computation time, and power consumption scale linearly versus the bit resolution of both the inputs and the weights. Analytical formulas are presented for the energy consumption in both capacitors and switches. Moreover, the impact of fabrication mismatch on analog computation accuracy is examined. The full system architecture is described, and the feasibility is demonstrated, via a full macro implementation study in 14 nm, detailing area and energy consumption, as well as the overall latency. Finally, a specific design of a 128 &amp;times; 2048 6 -bit weight and 6-bit input signed matrix-vector multiplication accelerator system in 14 nm is presented, which runs at 2.43 TOP/s at an efficiency of 16.94 TOP/s/W, while using the nominal supply voltage of 0.8 V. If the operands&amp;#39; precision is considered in the metric, then the efficiency becomes 609.7 TOP/s/W.&lt;/p&gt;</description>
</descriptions>
<fundingReferences>
<fundingReference>
<funderName>European Commission</funderName>
<funderIdentifier funderIdentifierType="Crossref Funder ID">10.13039/501100000780</funderIdentifier>
<awardNumber awardURI="info:eu-repo/grantAgreement/EC/H2020/682675/">682675</awardNumber>
<awardTitle>PROJECTED MEMRISTOR: A nanoscale device for cognitive computing</awardTitle>
</fundingReference>
</fundingReferences>
</resource>

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