Conference paper Open Access

# A Multi-Memristive Unit-Cell Array with Diagonal Interconnects for In-Memory Computing

Khaddam-Aljameh, Riduan; Martemucci, Michele; Kersting, Benedikt; Le Gallo, Manuel; Bruce, Robert, L.; BrightSky, Matthew; Sebastian, Abu

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<dc:creator>Martemucci, Michele</dc:creator>
<dc:creator>Kersting, Benedikt</dc:creator>
<dc:creator>Le Gallo, Manuel</dc:creator>
<dc:creator>Bruce, Robert, L.</dc:creator>
<dc:creator>BrightSky, Matthew</dc:creator>
<dc:creator>Sebastian, Abu</dc:creator>
<dc:date>2021-08-28</dc:date>
<dc:description>Memristive crossbar arrays can be used to realize () operations in constant time complexity by exploiting the Kirchhoff’s circuit laws. This is enabled by the parallel read of the entire array in a single time step. However, parallel writing is prohibitive in such arrays due to limitations on the current that could be accumulated along the wires. Hence, loading the matrix elements into such an array still incurs significant time penalty. Another key challenge is the achievable computational precision. To overcome these challenges, we propose a unit-cell array design where each unit-cell comprises four memristive devices each attached to a selection transistor. Moreover, the array is organized in such a way that the selection transistors can be turned on in a diagonal fashion. We experimentally demonstrated this concept by fabricating a 2×2 unit-cell array based on projected phase-change memory (PCM) devices in 90nm CMOS technology. It is shown that using the diagonal connections, the write operations can be parallelized while maintaining the current limit of the back-end-of-the-line metallization. Moreover, the increase in write time due to having more devices per unit-cell is minimized through a combination of single-shot and iterative programming schemes. Finally, we present experimental results on MVM operations that demonstrate improved computational precision exceeding that of a 4-bit fixed-point implementation.</dc:description>
<dc:identifier>https://zenodo.org/record/5300946</dc:identifier>
<dc:identifier>10.1109/TCSII.2021.3078614</dc:identifier>
<dc:identifier>oai:zenodo.org:5300946</dc:identifier>
<dc:relation>info:eu-repo/grantAgreement/EC/H2020/682675/</dc:relation>
<dc:rights>info:eu-repo/semantics/openAccess</dc:rights>
<dc:subject>in-memory computing, phase-change memory, deep learning</dc:subject>
<dc:title>A Multi-Memristive Unit-Cell Array with Diagonal Interconnects for In-Memory Computing</dc:title>
<dc:type>info:eu-repo/semantics/conferencePaper</dc:type>
<dc:type>publication-conferencepaper</dc:type>
</oai_dc:dc>

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