Journal article Open Access
Manica, M.; Polig, R.; Purandare, M.; Mathis, R.; Hagleitner, C.; Martinez, M.
<?xml version='1.0' encoding='utf-8'?> <oai_dc:dc xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:oai_dc="http://www.openarchives.org/OAI/2.0/oai_dc/" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:schemaLocation="http://www.openarchives.org/OAI/2.0/oai_dc/ http://www.openarchives.org/OAI/2.0/oai_dc.xsd"> <dc:creator>Manica, M.</dc:creator> <dc:creator>Polig, R.</dc:creator> <dc:creator>Purandare, M.</dc:creator> <dc:creator>Mathis, R.</dc:creator> <dc:creator>Hagleitner, C.</dc:creator> <dc:creator>Martinez, M.</dc:creator> <dc:date>2019-09-03</dc:date> <dc:description>Boolean models are a powerful abstraction for the qualitative modeling of gene regulatory networks. With the recent availability of advanced high-throughput technologies, Boolean models have increasingly grown in size and complexity, posing a challenge for existing software simulation tools that have not scaled at the same speed. Field Programmable Gate Arrays (FPGAs) are powerful reconfigurable integrated circuits that can offer massive performance improvements. Due to their highly parallel nature, FPGAs are well suited to simulate complex molecular networks. We present here a new simulation framework for Boolean models, which first converts the model to Verilog, a standardized hardware description language, and then connects it to an execution core that runs on an FPGA coherently attached to a POWER8 processor. We report an order of magnitude speedup over a multi-threaded software simulation tool running on the same processor on a selection of Boolean models. Analysis on a T-cell large granular lymphocyte leukemia (T-LGL) demonstrates that our framework achieves consistent performance improvements resulting in new biological insights. In addition, we show that our solution allows to perform attractor detection at an unprecedented speed, exhibiting a speedup ranging from one to three orders of magnitude compared to alternative software solutions.</dc:description> <dc:identifier>https://zenodo.org/record/4954146</dc:identifier> <dc:identifier>10.1109/TCBB.2019.2936836</dc:identifier> <dc:identifier>oai:zenodo.org:4954146</dc:identifier> <dc:language>eng</dc:language> <dc:relation>info:eu-repo/grantAgreement/EC/H2020/826121/</dc:relation> <dc:relation>url:https://zenodo.org/communities/ipc</dc:relation> <dc:rights>info:eu-repo/semantics/openAccess</dc:rights> <dc:rights>https://creativecommons.org/licenses/by/4.0/legalcode</dc:rights> <dc:source>IEEE Xplore 17(6) 2141 - 2147</dc:source> <dc:title>FPGA Accelerated Analysis of Boolean Gene Regulatory Networks</dc:title> <dc:type>info:eu-repo/semantics/article</dc:type> <dc:type>publication-article</dc:type> </oai_dc:dc>