Room Temperature Interconnection Technology for Bonding Fine Pitch Bumps Using NanoWiring, KlettWelding, KlettSintering and KlettGlueing

With further development in the fabrication technologies the density of electronic packages has increased. Ball grid arrays (BGA) and land grid array (LGA) with high density of connecting terminals have given rise to higher miniaturization of the integrated circuits (IC) and advancement in their performance. Fan-Out is one of the main solutions to fill the I/O gaps between the IC and PCB evolution. In this solution the chip is embedded in a mold compound like epoxy and the connecting terminals are fanned out using a redistribution layer (RDL). No PCB type layer is needed. The major challengers of this solution are fan-In solution like wafer level chip scale packaging (WL-CSP) and flip-chip CSP (FCCSP) or flip-chip BGA (FCBGA). Anyway, all surface mounting technologies depend primarily on the high temperature treated processes like soldering, sintering and reflow. Such processes raise the need of using new rare metals or toxic alloys. The environmental pollution caused by such metals and their recycling is a challenge. Furthermore, thermal processes have limited the technologies in terms of bumps and pitch sizes and placement accuracy. Also, the electrical conductivity, shear strength and the life cycle of the pads are affected by high temperature surface mounting processes. Especially Fan-out packaging on panel level (FOPLP) is not adopted yet due to technical challenges in assembly, die placement on large panels and fabrication and mounting connections/spaces below $10 \mu \mathrm{m}/ 10 \mu \mathrm{m}$. With KlettWelding technology, the die placement takes place immediately at room temperature by using standard pick and place machines, needing no inert gas or under fill. KlettWelding technology can enable bonding ultrahigh dense pads with $3 \mu \mathrm{m}$ edge length and $5 \mu \mathrm{m}$ pitches. The KlettWelding interconnections are from pure copper and free of any rare or toxic metals and no multi-layer structure as well. Also, in this technique the mismatch of the thermal expansions between the BGA and substrates by rapid temperature changes [1] vanishes.


INTRODUCTION
With further development in the fabrication technologies the density of electronic packages has increased. Ball grid arrays (BGA) and land grid array (LGA) with high density of connecting terminals have given rise to higher miniaturization of the integrated circuits (IC) and advancement in their performance. Fan-Out is one of the main solutions to fill the I/O gaps between the IC and PCB evolution. In this solution the chip is embedded in a mold compound like epoxy and the connecting terminals are fanned out using a redistribution layer (RDL). No PCB type layer is needed. The major challengers of this solution are fan-In solution like wafer level chip scale packaging (WL-CSP) and flip-chip CSP (FCCSP) or flip-chip BGA (FCBGA). Anyway, all surface mounting technologies depend primarily on the high temperature treated processes like soldering, sintering and reflow. Such processes raise the need of using new rare metals or toxic alloys. The environmental pollution caused by such metals and their recycling is a challenge. Furthermore, thermal processes have limited the technologies in terms of bumps and pitch sizes and placement accuracy. Also, the electrical conductivity, shear strength and the life cycle of the pads are affected by high temperature surface mounting processes. Especially Fan-out packaging on panel level (FOPLP) is not adopted yet due to technical challenges in assembly, die placement on large panels and fabrication and mounting connections/spaces below 10μm/10μm. With KlettWelding technology, the die placement takes place immediately at room temperature by using standard pick and place machines, needing no inert gas or under fill. KlettWelding technology can enable bonding ultrahigh dense pads with 3μm edge length and 5μm pitches. The KlettWelding interconnections are from pure copper and free of any rare or toxic metals and no multi-layer structure as well. Also, in this technique the mismatch of the thermal expansions between the BGA and substrates by rapid temperature changes [1] vanishes.

NANOWIRING PROCESS
The first step in the process is covering the connection surfaces with metallic nanowires, so called NanoWiring. This is done by a standard electrochemical deposition process [2,3,4] as shown in Figure 1. At the first step the pads are defined by a lithography step. The synthesis of the wires takes place in a NanoWiring machine with automatically controlled parameters at temperatures below 35 °C for Cu nanowires. In this process the connecting pads/bumps are covered with a sponge-template compound. The sponge is soaked in the electrolyte. The sponge-template compound is pressed on the defined pads with a controlled and homogenous distributed force. The deposition begins by applying the voltage between the anode and the working electrode. The NanoWiring process takes between 15 to 40 minutes depending on the active surface area to be covered and the concentration of metal ions and other additives in the electrolyte for ULSI applications. By controlling the height of the photo resist the deposition of the copper pillars and the NanoWiring process can be done in just one step in the NanoWiring machine. In the next step the substrates are stripped. The stripping process can be done either wet chemical or in a plasma ashing machine. With this method the diameter of the wires can be adjusted between 30 to 4000 nm and their length are ranged from 4 μm to 50 μm. The wires fill factor ranges between 5% to 50% depending on the application. The NanoWiring machine is shown in Figure 2. The machine needs about 500 ml of electrolyte for each batch. The electrolyte is recycled and reused in a containment system to minimize the environmental pollution. This makes the process more cost efficient as well. The process is scaled up to 12-inch wafers or 300×400 mm² panels. In this machine NanoWiring with different metals like copper, gold, silver, nickel and platinum are possible. Active NanoWiring surface ranges between 3×3 μm² to 300×400 mm². The synthesis of the wires is homogeneous and the wires angles can also be adjusted between 90° to 60 °. The deviation in the wire length is less than 10% of the maximum wire length. The max. allowed surface roughness for the NanoWiring seed layer is ±10 μm.  The NanoWiring can be performed not just on flat surfaces. The curved surfaces can be covered with nanowires as well. Also covering the inside and outside surfaces of tubes enabled [5]. In Figure 3 are some samples with NanoWiring on their surfaces shown. Figure 3. The NanoWiring can be performed on different types of substrate like silicon, glass, ceramics, flexible polymers and metals. a), b) NanoWiring on pads with 6 μm edge length and 10 μm pitches on a 6-inch wafer. The wires have an Aspect ratio of 4 μm / 100 nm. c), d) NanoWiring on copper pillars with 60 μm width a silicon chip. The pillars are grown directly with the nanowires on the chips. e) The Wires on a diode chip have overcome the dicing process. f) Wires with aspect ratio 50 μm/ 1 μm on a bus-bar sample with 4×5 mm². The bus-bar is a laser cut specimen.

USE CASES OF THE NANOWIRED SURFACES
The nanowires overcome the dicing step. The diced chips can be bonded by adjusting the chip and pressing the NanoWired bumps on top of each other at room temperature, using the standard bonding devices. For a better diffusion a prior copper oxide reducing step for the copper Nanowires is needed. This can be done by using standard processes like forming-gas plasma or formic acid vapor.

KlettWelding
The room temperature bonding with nanowires, the so-called KlettWelding, can be explained as superposition of two physical phenomena. The first one is the mechanical weaving of the wires and the second one is the diffusion of the nanowires into each other by migration of the atoms from crystal lattice of one wire to the other one. The very large achieved surface to volume quotient of NanoWired surface increases the rate of the diffusion enormously. The KlettWelding appears in less than 60 ms. Immediately after bonding, 70% of the maximum strengths is achieved. After approx. 12 hours the final strength is reached. For this process the NanoWiring must be done on both contact surfaces.

KlettSintering
The atomic motion process can be enhanced by additional thermal energy to increase the strength of the joints, the socalled KlettSintering. This process needs a temperature 170 °C to 270 °C, that is lower than other technologies with ca. 350°C and 40 MPa minimum process temperature and bonding pressure [6]. The needed pressure ranges from 10 MPa to 70 MPa. For this technique only one side of the surfaces must be covered with nanowires. The joining time ranges between 10 s to 120 s depending on the surface sizes and the substrate material. μm. The KlettSintering techniques can also be combined with the KlettWelding process by sintering two surfaces with nanowires to each other. Then, the connection appears immediately and the tempering step can be done later and in the absence of pressure in a standard oven at 230 °C. However, evacuating the oven or using inert gas is advantageous but it is not necessary.

KlettGlueing
In many cases an adhesive material can be used as an under fill or for a better sealing in the interior cavities and also as an extra sticking medium in the contacts. Especially the KlettGlueing can be done with just one NanoWired surface and pressure about 1 MPa without any impact on the electrical conductance of the connection. For KlettGlueing a drying temperature of about 70 °C to 170 °C, depending on the under-fill material is needed. Like KlettSintering, the KlettGlueing process can also be combined with KlettWelding method. The cross-section images of the all three connections are shown in Figure 5.

KlettWelding-Tape
In cases that a NanoWiring on the both surfaces is not desired a so called KlettWelding-Tape (KWT) can be used. This tape is shown in Figure 6. This is a copper foil covered with Nanowires at the both sides. The KWT can be cut or punched in the desired dimension with a standard cutting machine or even scissors. The bonding can be done by putting the KWT between the two surfaces and applying the same pressure / temperature conditions as the KlettSintering.     A long-term electrical current test at 30 A through a KlettWelding joint in compare to a 4-point laser welding joint as battery connector samples is performed. It shows a maximum contact temperature of 45.7 °C in the KlettWelding joint while the 4-point laser welding sample exceeded 150 °C (see Figure 9).

Sealing test
A helium gas sealing test shows a leakage rate of 9.5×10 -9 mbar×l/s for KlettSintering connections and 1.0×10 -8 mbar×l/s for KlettWelding+ structures. The burst pressure measurement of the KlettWelding-Tape connection for copper tube connection is about 250 bar and its leakage rate is about -33 g/a.

CONCOLUTION AND OUTLOOK
With the method introduced in this paper the NanoWiring of almost all kinds of substrates like Polymers, Silicon, Glass, Ceramics, Aluminum, Steel, Copper is possible. By adjusting the parameters like wire diameter, height, density and material the bonding pressure and shear strength can be adjusted. As the contacts are made of pure copper, the connections have overcome more than 1000 cycles of -40 °C / 150 °C temperature shocks. The reason is the same expansion coefficient of the substrate and wires. The aging of the wires in storage and the aging of the connections in different ambient conditions are under test and the results will be introduced in the next papers. The first tests show a contact thermal conductivity of about 350 W/mK. An investigation on higher number of samples is ongoing as well. With this technique stacking more than 4 stages of chips on top of each other is also feasible which is a walkthrough for many problems in mobile devices and RAM chips.